Loop Id: 1287 | Module: exec | Source: forall.hpp:59-59 [...] | Coverage: 1.6% |
---|
Loop Id: 1287 | Module: exec | Source: forall.hpp:59-59 [...] | Coverage: 1.6% |
---|
0x46a0b0 VMOVSD (%RSI,%R12,8),%XMM0 [8] |
0x46a0b6 VADDSD %XMM0,%XMM0,%XMM0 |
0x46a0ba MOV -0x1f8(%RBP),%RDX [11] |
0x46a0c1 VDIVSD (%RDX,%R9,1),%XMM0,%XMM0 [2] |
0x46a0c7 VMOVSD (%R14,%R12,8),%XMM1 [10] |
0x46a0cd MOV %RDI,%RDX |
0x46a0d0 MOV -0x210(%RBP),%RDI [11] |
0x46a0d7 VMOVHPD (%RDI,%R12,8),%XMM1,%XMM1 [6] |
0x46a0dd VADDPD %XMM1,%XMM1,%XMM1 |
0x46a0e1 MOV -0x218(%RBP),%RDI [11] |
0x46a0e8 MOV -0xa0(%RBP),%RCX [11] |
0x46a0ef VMOVSD (%RDI,%RCX,8),%XMM2 [4] |
0x46a0f4 MOV -0x208(%RBP),%RDI [11] |
0x46a0fb VMOVHPD (%RDI,%R13,8),%XMM2,%XMM2 [13] |
0x46a101 VDIVPD %XMM2,%XMM1,%XMM1 |
0x46a105 VMOVSD (%RDX,%RAX,8),%XMM2 [15] |
0x46a10a MOV -0x48(%RBP),%RCX [11] |
0x46a10e VFMADD213SD (%RCX,%R11,1),%XMM0,%XMM2 [12] |
0x46a114 MOV -0x98(%RBP),%RCX [11] |
0x46a11b VFMADD231SD (%RCX,%R9,1),%XMM1,%XMM2 [7] |
0x46a121 VSHUFPD $0x1,%XMM1,%XMM1,%XMM3 |
0x46a126 VFMADD231SD (%R15,%R9,1),%XMM3,%XMM2 [5] |
0x46a12c VADDSD %XMM0,%XMM1,%XMM0 |
0x46a130 MOV %R15,%RDI |
0x46a133 MOV %R13,%R15 |
0x46a136 MOV %RCX,%R13 |
0x46a139 MOV %R14,%RCX |
0x46a13c MOV %R8,%R14 |
0x46a13f MOV %RSI,%R8 |
0x46a142 MOV -0x50(%RBP),%RSI [11] |
0x46a146 VADDSD (%RSI,%R11,1),%XMM3,%XMM1 [9] |
0x46a14c MOV %R8,%RSI |
0x46a14f MOV %R14,%R8 |
0x46a152 MOV %RCX,%R14 |
0x46a155 MOV %R13,%RCX |
0x46a158 MOV %R15,%R13 |
0x46a15b MOV %RDI,%R15 |
0x46a15e MOV %RDX,%RDI |
0x46a161 VADDSD %XMM0,%XMM1,%XMM0 |
0x46a165 VDIVSD %XMM0,%XMM2,%XMM0 |
0x46a169 VMOVSD %XMM0,(%R10,%R11,1) [1] |
0x46a16f VADDSD %XMM0,%XMM0,%XMM0 |
0x46a173 VSUBSD (%RDX,%RAX,8),%XMM0,%XMM1 [15] |
0x46a178 VMOVSD %XMM1,(%RDX,%RAX,8) [15] |
0x46a17d VSUBSD (%RCX,%R9,1),%XMM0,%XMM1 [14] |
0x46a183 VMOVSD %XMM1,(%RCX,%R9,1) [14] |
0x46a189 VSUBSD (%R15,%R9,1),%XMM0,%XMM0 [3] |
0x46a18f VMOVSD %XMM0,(%R15,%R9,1) [3] |
0x46a195 ADD -0x200(%RBP),%R9 [11] |
0x46a19c ADD %R8,%R11 |
0x46a19f DEC %RBX |
0x46a1a2 JNE 46a0b0 |
/scratch_na/users/xoserete/qaas_runs/171-416-9860/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/loop/forall.hpp: 59 - 59 |
-------------------------------------------------------------------------------- |
59: for (decltype(distance_it) i = 0; i < distance_it; ++i) { |
/scratch_na/users/xoserete/qaas_runs/171-416-9860/intel/Kripke/build/Kripke/src/Kripke/Kernel/SweepSubdomain.cpp: 87 - 105 |
-------------------------------------------------------------------------------- |
87: double xcos_dxi = 2.0 * xcos(d) / dx(i); |
88: double ycos_dyj = 2.0 * ycos(d) / dy(j); |
[...] |
95: + psi_lf(d, g, j, k) * xcos_dxi |
96: + psi_fr(d, g, i, k) * ycos_dyj |
97: + psi_bo(d, g, i, j) * zcos_dzk) |
98: / (xcos_dxi + ycos_dyj + zcos_dzk + sigt(g, z)); |
99: |
100: psi(d, g, z) = psi_d_g_z; |
101: |
102: /* Apply diamond-difference relationships */ |
103: psi_lf(d, g, j, k) = 2.0 * psi_d_g_z - psi_lf(d, g, j, k); |
104: psi_fr(d, g, i, k) = 2.0 * psi_d_g_z - psi_fr(d, g, i, k); |
105: psi_bo(d, g, i, j) = 2.0 * psi_d_g_z - psi_bo(d, g, i, j); |
Coverage (%) | Name | Source Location | Module |
---|---|---|---|
►100.00+ | __kmp_invoke_microtask | libiomp5.so | |
○ | __kmp_invoke_task_func | libiomp5.so |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.50 |
CQA speedup if fully vectorized | 1.50 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.18 |
Bottlenecks | P0, |
Function | void Kripke::DispatchHelper |
Source | forall.hpp:59-59,SweepSubdomain.cpp:87-88,SweepSubdomain.cpp:95-105 |
Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
Source loop unroll confidence level | max |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 12.00 |
CQA cycles if no scalar integer | 12.00 |
CQA cycles if FP arith vectorized | 8.00 |
CQA cycles if fully vectorized | 8.00 |
Front-end cycles | 10.17 |
DIV/SQRT cycles | 4.00 |
P0 cycles | 7.00 |
P1 cycles | 7.67 |
P2 cycles | 7.67 |
P3 cycles | 2.00 |
P4 cycles | 7.00 |
P5 cycles | 1.60 |
P6 cycles | 2.00 |
P7 cycles | 2.00 |
P8 cycles | 2.00 |
P9 cycles | 1.40 |
P10 cycles | 7.67 |
P11 cycles | 12.00 |
Inter-iter dependencies cycles | 2 |
FE+BE cycles (UFS) | 12.75 - 12.89 |
Stall cycles (UFS) | 1.75 - 1.92 |
Nb insns | 52.00 |
Nb uops | 51.00 |
Nb loads | 23.00 |
Nb stores | 4.00 |
Nb stack references | 9.00 |
FLOP/cycle | 1.67 |
Nb FLOP add-sub | 10.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 3.00 |
Nb FLOP div | 4.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 18.00 |
Bytes prefetched | 0.00 |
Bytes loaded | 184.00 |
Bytes stored | 32.00 |
Stride 0 | 1.00 |
Stride 1 | 0.00 |
Stride n | 0.00 |
Stride unknown | 3.00 |
Stride indirect | 9.00 |
Vectorization ratio all | 10.71 |
Vectorization ratio load | 0.00 |
Vectorization ratio store | 0.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | 11.11 |
Vectorization ratio fma | 0.00 |
Vectorization ratio div_sqrt | 33.33 |
Vectorization ratio other | 33.33 |
Vector-efficiency ratio all | 13.84 |
Vector-efficiency ratio load | 12.50 |
Vector-efficiency ratio store | 12.50 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | 13.89 |
Vector-efficiency ratio fma | 12.50 |
Vector-efficiency ratio div_sqrt | 16.67 |
Vector-efficiency ratio other | 16.67 |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.50 |
CQA speedup if fully vectorized | 1.50 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.18 |
Bottlenecks | P0, |
Function | void Kripke::DispatchHelper |
Source | forall.hpp:59-59,SweepSubdomain.cpp:87-88,SweepSubdomain.cpp:95-105 |
Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
Source loop unroll confidence level | max |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 12.00 |
CQA cycles if no scalar integer | 12.00 |
CQA cycles if FP arith vectorized | 8.00 |
CQA cycles if fully vectorized | 8.00 |
Front-end cycles | 10.17 |
DIV/SQRT cycles | 4.00 |
P0 cycles | 7.00 |
P1 cycles | 7.67 |
P2 cycles | 7.67 |
P3 cycles | 2.00 |
P4 cycles | 7.00 |
P5 cycles | 1.60 |
P6 cycles | 2.00 |
P7 cycles | 2.00 |
P8 cycles | 2.00 |
P9 cycles | 1.40 |
P10 cycles | 7.67 |
P11 cycles | 12.00 |
Inter-iter dependencies cycles | 2 |
FE+BE cycles (UFS) | 12.75 - 12.89 |
Stall cycles (UFS) | 1.75 - 1.92 |
Nb insns | 52.00 |
Nb uops | 51.00 |
Nb loads | 23.00 |
Nb stores | 4.00 |
Nb stack references | 9.00 |
FLOP/cycle | 1.67 |
Nb FLOP add-sub | 10.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 3.00 |
Nb FLOP div | 4.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 18.00 |
Bytes prefetched | 0.00 |
Bytes loaded | 184.00 |
Bytes stored | 32.00 |
Stride 0 | 1.00 |
Stride 1 | 0.00 |
Stride n | 0.00 |
Stride unknown | 3.00 |
Stride indirect | 9.00 |
Vectorization ratio all | 10.71 |
Vectorization ratio load | 0.00 |
Vectorization ratio store | 0.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | 11.11 |
Vectorization ratio fma | 0.00 |
Vectorization ratio div_sqrt | 33.33 |
Vectorization ratio other | 33.33 |
Vector-efficiency ratio all | 13.84 |
Vector-efficiency ratio load | 12.50 |
Vector-efficiency ratio store | 12.50 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | 13.89 |
Vector-efficiency ratio fma | 12.50 |
Vector-efficiency ratio div_sqrt | 16.67 |
Vector-efficiency ratio other | 16.67 |
Path / |
Function | void Kripke::DispatchHelper |
Source file and lines | forall.hpp:59-59 |
Module | exec |
nb instructions | 52 |
nb uops | 51 |
loop length | 248 |
used x86 registers | 15 |
used mmx registers | 0 |
used xmm registers | 4 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 9 |
micro-operation queue | 10.17 cycles |
front end | 10.17 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 4.00 | 7.00 | 7.67 | 7.67 | 2.00 | 7.00 | 1.60 | 2.00 | 2.00 | 2.00 | 1.40 | 7.67 |
cycles | 4.00 | 7.00 | 7.67 | 7.67 | 2.00 | 7.00 | 1.60 | 2.00 | 2.00 | 2.00 | 1.40 | 7.67 |
Cycles executing div or sqrt instructions | 12.00 |
Longest recurrence chain latency (RecMII) | 2.00 |
FE+BE cycles | 12.75-12.89 |
Stall cycles | 1.75-1.92 |
LB full (events) | 2.41-2.59 |
Front-end | 10.17 |
Dispatch | 7.67 |
DIV/SQRT | 12.00 |
Data deps. | 2.00 |
Overall L1 | 12.00 |
all | 0% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 0% |
all | 11% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 11% |
fma | 0% |
div/sqrt | 33% |
other | 100% |
all | 10% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 11% |
fma | 0% |
div/sqrt | 33% |
other | 33% |
all | 12% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 12% |
all | 13% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 13% |
fma | 12% |
div/sqrt | 16% |
other | 25% |
all | 13% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 13% |
fma | 12% |
div/sqrt | 16% |
other | 16% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
VMOVSD (%RSI,%R12,8),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VADDSD %XMM0,%XMM0,%XMM0 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
MOV -0x1f8(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VDIVSD (%RDX,%R9,1),%XMM0,%XMM0 | 1 | 1 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 13-15 | 4 |
VMOVSD (%R14,%R12,8),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDI,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV -0x210(%RBP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVHPD (%RDI,%R12,8),%XMM1,%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4-12 | 1 |
VADDPD %XMM1,%XMM1,%XMM1 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
MOV -0x218(%RBP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0xa0(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD (%RDI,%RCX,8),%XMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x208(%RBP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVHPD (%RDI,%R13,8),%XMM2,%XMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4-12 | 1 |
VDIVPD %XMM2,%XMM1,%XMM1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 13-15 | 4 |
VMOVSD (%RDX,%RAX,8),%XMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x48(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VFMADD213SD (%RCX,%R11,1),%XMM0,%XMM2 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
MOV -0x98(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VFMADD231SD (%RCX,%R9,1),%XMM1,%XMM2 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VSHUFPD $0x1,%XMM1,%XMM1,%XMM3 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VFMADD231SD (%R15,%R9,1),%XMM3,%XMM2 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VADDSD %XMM0,%XMM1,%XMM0 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
MOV %R15,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R13,%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RCX,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R14,%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R8,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RSI,%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV -0x50(%RBP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VADDSD (%RSI,%R11,1),%XMM3,%XMM1 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
MOV %R8,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R14,%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RCX,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R13,%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R15,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RDI,%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RDX,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
VADDSD %XMM0,%XMM1,%XMM0 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VDIVSD %XMM0,%XMM2,%XMM0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 13-15 | 4 |
VMOVSD %XMM0,(%R10,%R11,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VADDSD %XMM0,%XMM0,%XMM0 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VSUBSD (%RDX,%RAX,8),%XMM0,%XMM1 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
VMOVSD %XMM1,(%RDX,%RAX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VSUBSD (%RCX,%R9,1),%XMM0,%XMM1 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
VMOVSD %XMM1,(%RCX,%R9,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VSUBSD (%R15,%R9,1),%XMM0,%XMM0 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
VMOVSD %XMM0,(%R15,%R9,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD -0x200(%RBP),%R9 | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
ADD %R8,%R11 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
DEC %RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
JNE 46a0b0 <_ZNK6Kripke14DispatchHelperINS_12ArchT_OpenMPEEclINS_11LayoutT_DGZE9SweepSdomJRNS_4Core9DataStoreERNS_6SdomIdEEEEvT_RKT0_DpOT1_.extracted+0x760> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
Function | void Kripke::DispatchHelper |
Source file and lines | forall.hpp:59-59 |
Module | exec |
nb instructions | 52 |
nb uops | 51 |
loop length | 248 |
used x86 registers | 15 |
used mmx registers | 0 |
used xmm registers | 4 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 9 |
micro-operation queue | 10.17 cycles |
front end | 10.17 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 4.00 | 7.00 | 7.67 | 7.67 | 2.00 | 7.00 | 1.60 | 2.00 | 2.00 | 2.00 | 1.40 | 7.67 |
cycles | 4.00 | 7.00 | 7.67 | 7.67 | 2.00 | 7.00 | 1.60 | 2.00 | 2.00 | 2.00 | 1.40 | 7.67 |
Cycles executing div or sqrt instructions | 12.00 |
Longest recurrence chain latency (RecMII) | 2.00 |
FE+BE cycles | 12.75-12.89 |
Stall cycles | 1.75-1.92 |
LB full (events) | 2.41-2.59 |
Front-end | 10.17 |
Dispatch | 7.67 |
DIV/SQRT | 12.00 |
Data deps. | 2.00 |
Overall L1 | 12.00 |
all | 0% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 0% |
all | 11% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 11% |
fma | 0% |
div/sqrt | 33% |
other | 100% |
all | 10% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 11% |
fma | 0% |
div/sqrt | 33% |
other | 33% |
all | 12% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 12% |
all | 13% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 13% |
fma | 12% |
div/sqrt | 16% |
other | 25% |
all | 13% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 13% |
fma | 12% |
div/sqrt | 16% |
other | 16% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
VMOVSD (%RSI,%R12,8),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VADDSD %XMM0,%XMM0,%XMM0 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
MOV -0x1f8(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VDIVSD (%RDX,%R9,1),%XMM0,%XMM0 | 1 | 1 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 13-15 | 4 |
VMOVSD (%R14,%R12,8),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDI,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV -0x210(%RBP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVHPD (%RDI,%R12,8),%XMM1,%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4-12 | 1 |
VADDPD %XMM1,%XMM1,%XMM1 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
MOV -0x218(%RBP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0xa0(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD (%RDI,%RCX,8),%XMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x208(%RBP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVHPD (%RDI,%R13,8),%XMM2,%XMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4-12 | 1 |
VDIVPD %XMM2,%XMM1,%XMM1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 13-15 | 4 |
VMOVSD (%RDX,%RAX,8),%XMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x48(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VFMADD213SD (%RCX,%R11,1),%XMM0,%XMM2 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
MOV -0x98(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VFMADD231SD (%RCX,%R9,1),%XMM1,%XMM2 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VSHUFPD $0x1,%XMM1,%XMM1,%XMM3 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VFMADD231SD (%R15,%R9,1),%XMM3,%XMM2 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VADDSD %XMM0,%XMM1,%XMM0 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
MOV %R15,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R13,%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RCX,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R14,%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R8,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RSI,%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV -0x50(%RBP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VADDSD (%RSI,%R11,1),%XMM3,%XMM1 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
MOV %R8,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R14,%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RCX,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R13,%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R15,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RDI,%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RDX,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
VADDSD %XMM0,%XMM1,%XMM0 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VDIVSD %XMM0,%XMM2,%XMM0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 13-15 | 4 |
VMOVSD %XMM0,(%R10,%R11,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VADDSD %XMM0,%XMM0,%XMM0 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VSUBSD (%RDX,%RAX,8),%XMM0,%XMM1 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
VMOVSD %XMM1,(%RDX,%RAX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VSUBSD (%RCX,%R9,1),%XMM0,%XMM1 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
VMOVSD %XMM1,(%RCX,%R9,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VSUBSD (%R15,%R9,1),%XMM0,%XMM0 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
VMOVSD %XMM0,(%R15,%R9,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD -0x200(%RBP),%R9 | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
ADD %R8,%R11 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
DEC %RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
JNE 46a0b0 <_ZNK6Kripke14DispatchHelperINS_12ArchT_OpenMPEEclINS_11LayoutT_DGZE9SweepSdomJRNS_4Core9DataStoreERNS_6SdomIdEEEEvT_RKT0_DpOT1_.extracted+0x760> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |