Loop Id: 1423 | Module: exec | Source: forall.hpp:59-59 [...] | Coverage: 0.01% |
---|
Loop Id: 1423 | Module: exec | Source: forall.hpp:59-59 [...] | Coverage: 0.01% |
---|
0x4a4bc0 MOV -0x78(%RBP),%RAX |
0x4a4bc4 ADD -0x3c0(%RBP),%RAX |
0x4a4bcb MOV %RAX,-0x78(%RBP) |
0x4a4bcf MOV -0x3b8(%RBP),%RAX |
0x4a4bd6 MOV -0xd0(%RBP),%R14 |
0x4a4bdd ADD %RAX,%R14 |
0x4a4be0 MOV -0xc8(%RBP),%R15 |
0x4a4be7 ADD %RAX,%R15 |
0x4a4bea MOV -0x458(%RBP),%R13 |
0x4a4bf1 ADD %RAX,%R13 |
0x4a4bf4 MOV -0x3e8(%RBP),%R11 |
0x4a4bfb MOV -0x450(%RBP),%RDX |
0x4a4c02 CMP %R11,%RDX |
0x4a4c05 LEA 0x1(%RDX),%RDX |
0x4a4c09 JE 4a4740 |
0x4a4c0f MOV -0xf8(%RBP),%RAX |
0x4a4c16 MOV %RAX,-0x520(%RBP) |
0x4a4c1d MOV %RAX,-0x518(%RBP) |
0x4a4c24 MOV -0x3d0(%RBP),%RAX |
0x4a4c2b MOV %RAX,-0x510(%RBP) |
0x4a4c32 MOV -0x3c8(%RBP),%RAX |
0x4a4c39 MOV %RAX,-0x508(%RBP) |
0x4a4c40 MOV -0x58(%RBP),%RAX |
0x4a4c44 MOV %RAX,-0x500(%RBP) |
0x4a4c4b MOV %RAX,-0x4f8(%RBP) |
0x4a4c52 MOV -0x3e0(%RBP),%RAX |
0x4a4c59 MOV %RAX,-0x4f0(%RBP) |
0x4a4c60 MOV -0x3d8(%RBP),%RAX |
0x4a4c67 MOV %RAX,-0x4e8(%RBP) |
0x4a4c6e MOV -0x118(%RBP),%RAX |
0x4a4c75 MOV %RAX,-0x4e0(%RBP) |
0x4a4c7c MOV %RAX,-0x4d8(%RBP) |
0x4a4c83 MOV -0x218(%RBP),%RCX |
0x4a4c8a MOV %RDX,-0x450(%RBP) |
0x4a4c91 IMUL %RDX,%RCX |
0x4a4c95 MOV -0x68(%RBP),%RAX |
0x4a4c99 ADD %RCX,%RAX |
0x4a4c9c MOV -0x3f0(%RBP),%RDX |
0x4a4ca3 LEA (%RDX,%RAX,8),%RAX |
0x4a4ca7 MOV %RAX,-0x4d0(%RBP) |
0x4a4cae MOV %RAX,-0x230(%RBP) |
0x4a4cb5 MOV %RAX,-0x4c8(%RBP) |
0x4a4cbc MOV %RCX,%RSI |
0x4a4cbf IMUL -0x208(%RBP),%RSI |
0x4a4cc7 MOV -0x428(%RBP),%RAX |
0x4a4cce ADD %RSI,%RAX |
0x4a4cd1 MOV -0xf0(%RBP),%RDX |
0x4a4cd8 LEA (%RDX,%RAX,8),%RAX |
0x4a4cdc MOV %RAX,-0x4c0(%RBP) |
0x4a4ce3 MOV -0x420(%RBP),%RAX |
0x4a4cea MOV %RSI,-0x220(%RBP) |
0x4a4cf1 ADD %RSI,%RAX |
0x4a4cf4 LEA (%RDX,%RAX,8),%RAX |
0x4a4cf8 MOV %RAX,-0x4b8(%RBP) |
0x4a4cff MOV %RCX,%RAX |
0x4a4d02 IMUL -0xb8(%RBP),%RAX |
0x4a4d0a MOV -0x430(%RBP),%RDX |
0x4a4d11 ADD %RAX,%RDX |
0x4a4d14 MOV -0x210(%RBP),%RSI |
0x4a4d1b LEA (%RSI,%RDX,8),%RDX |
0x4a4d1f MOV %RDX,-0x4b0(%RBP) |
0x4a4d26 MOV -0x448(%RBP),%RDX |
0x4a4d2d ADD %RAX,%RDX |
0x4a4d30 LEA (%RSI,%RDX,8),%RDX |
0x4a4d34 MOV %RDX,-0x4a8(%RBP) |
0x4a4d3b IMUL -0xb0(%RBP),%RCX |
0x4a4d43 MOV -0x418(%RBP),%RDX |
0x4a4d4a ADD %RCX,%RDX |
0x4a4d4d MOV -0x200(%RBP),%RSI |
0x4a4d54 LEA (%RSI,%RDX,8),%RDX |
0x4a4d58 MOV %RDX,-0x4a0(%RBP) |
0x4a4d5f ADD -0x440(%RBP),%RCX |
0x4a4d66 LEA (%RSI,%RCX,8),%RCX |
0x4a4d6a MOV %RCX,-0x498(%RBP) |
0x4a4d71 MOV -0x410(%RBP),%RCX |
0x4a4d78 MOV %RCX,-0x490(%RBP) |
0x4a4d7f MOV -0x408(%RBP),%RCX |
0x4a4d86 MOV %RCX,-0x488(%RBP) |
0x4a4d8d MOV -0x400(%RBP),%RCX |
0x4a4d94 ADD %RAX,%RCX |
0x4a4d97 MOV -0x1f8(%RBP),%RDX |
0x4a4d9e LEA (%RDX,%RCX,8),%RCX |
0x4a4da2 MOV %RCX,-0x480(%RBP) |
0x4a4da9 MOV -0xc0(%RBP),%RCX |
0x4a4db0 ADD %RAX,%RCX |
0x4a4db3 LEA (%RDX,%RCX,8),%RCX |
0x4a4db7 MOV %RCX,-0x478(%RBP) |
0x4a4dbe MOV -0x3f8(%RBP),%RCX |
0x4a4dc5 ADD %RAX,%RCX |
0x4a4dc8 MOV -0x1f0(%RBP),%RDX |
0x4a4dcf LEA (%RDX,%RCX,8),%RCX |
0x4a4dd3 MOV %RCX,-0x470(%RBP) |
0x4a4dda ADD -0x438(%RBP),%RAX |
0x4a4de1 LEA (%RDX,%RAX,8),%RAX |
0x4a4de5 MOV %RAX,-0x468(%RBP) |
0x4a4dec MOV $0xc,%ESI |
0x4a4df1 LEA -0x520(%RBP),%RDI |
0x4a4df8 CALL 50ef70 <__intel_rtdd_indep> |
0x4a4dfd TEST %RAX,%RAX |
0x4a4e00 MOV %R13,-0x458(%RBP) |
0x4a4e07 MOV %R14,-0xd0(%RBP) |
0x4a4e0e MOV %R15,-0xc8(%RBP) |
0x4a4e15 JE 4a5000 |
0x4a4e1b MOV -0x3b0(%RBP),%RSI |
0x4a4e22 MOVQ $0,-0x110(%RBP) |
0x4a4e2d MOV -0x78(%RBP),%RCX |
0x4a4e31 MOV -0x230(%RBP),%RBX |
0x4a4e38 JMP 4a4e88 |
(1426) 0x4a4e40 ADD -0x50(%RBP),%RSI |
(1426) 0x4a4e44 MOV -0x100(%RBP),%RDI |
(1426) 0x4a4e4b MOV -0x38(%RBP),%R8 |
(1426) 0x4a4e4f ADD %RDI,%R8 |
(1426) 0x4a4e52 MOV -0x30(%RBP),%RDX |
(1426) 0x4a4e56 ADD %RDI,%RDX |
(1426) 0x4a4e59 MOV -0x88(%RBP),%R13 |
(1426) 0x4a4e60 ADD %RDI,%R13 |
(1426) 0x4a4e63 MOV -0x110(%RBP),%RAX |
(1426) 0x4a4e6a CMP -0x108(%RBP),%RAX |
(1426) 0x4a4e71 LEA 0x1(%RAX),%RAX |
(1426) 0x4a4e75 MOV %RAX,-0x110(%RBP) |
(1426) 0x4a4e7c MOV %RDX,%R15 |
(1426) 0x4a4e7f MOV %R8,%R14 |
(1426) 0x4a4e82 JE 4a4bc0 |
(1426) 0x4a4e88 MOV %R14,-0x38(%RBP) |
(1426) 0x4a4e8c MOV %R15,-0x30(%RBP) |
(1426) 0x4a4e90 MOV %R13,-0x88(%RBP) |
(1426) 0x4a4e97 CMPQ $0,-0x80(%RBP) |
(1426) 0x4a4e9c MOV -0x70(%RBP),%RDI |
(1426) 0x4a4ea0 MOV -0xe8(%RBP),%R13 |
(1426) 0x4a4ea7 MOV -0x48(%RBP),%RAX |
(1426) 0x4a4eab MOV -0xf0(%RBP),%R14 |
(1426) 0x4a4eb2 MOV -0x228(%RBP),%RDX |
(1426) 0x4a4eb9 MOV -0xf8(%RBP),%R15 |
(1426) 0x4a4ec0 JLE 4a4e40 |
(1426) 0x4a4ec6 MOV -0xd8(%RBP),%R8 |
(1426) 0x4a4ecd IMUL -0x110(%RBP),%R8 |
(1426) 0x4a4ed5 MOV -0x40(%RBP),%R9 |
(1426) 0x4a4ed9 ADD %R8,%R9 |
(1426) 0x4a4edc MOV %R9,-0x120(%RBP) |
(1426) 0x4a4ee3 ADD -0x220(%RBP),%R8 |
(1426) 0x4a4eea ADD -0xe0(%RBP),%R8 |
(1426) 0x4a4ef1 XOR %R10D,%R10D |
(1426) 0x4a4ef4 XOR %R11D,%R11D |
(1426) 0x4a4ef7 MOV -0x80(%RBP),%R12 |
(1426) 0x4a4efb NOPL (%RAX,%RAX,1) |
(1427) 0x4a4f00 VMOVSD (%R15),%XMM0 |
(1427) 0x4a4f05 VADDSD %XMM0,%XMM0,%XMM0 |
(1427) 0x4a4f09 VDIVSD (%RDX,%R11,1),%XMM0,%XMM0 |
(1427) 0x4a4f0f MOV -0x58(%RBP),%R9 |
(1427) 0x4a4f13 VMOVSD (%R9),%XMM1 |
(1427) 0x4a4f18 MOV -0x118(%RBP),%R9 |
(1427) 0x4a4f1f VMOVHPD (%R9),%XMM1,%XMM1 |
(1427) 0x4a4f24 VADDPD %XMM1,%XMM1,%XMM1 |
(1427) 0x4a4f28 MOV -0x120(%RBP),%R9 |
(1427) 0x4a4f2f VMOVSD (%R13,%R9,8),%XMM2 |
(1427) 0x4a4f36 VMOVHPD (%RBX),%XMM2,%XMM2 |
(1427) 0x4a4f3a VDIVPD %XMM2,%XMM1,%XMM1 |
(1427) 0x4a4f3e VMOVSD (%R14,%R8,8),%XMM2 |
(1427) 0x4a4f44 MOV %R15,%R9 |
(1427) 0x4a4f47 MOV %RDX,%R15 |
(1427) 0x4a4f4a MOV %RAX,%RDX |
(1427) 0x4a4f4d MOV %R13,%RAX |
(1427) 0x4a4f50 MOV %RDI,%R13 |
(1427) 0x4a4f53 MOV -0x88(%RBP),%RDI |
(1427) 0x4a4f5a VFMADD213SD (%RDI,%R10,1),%XMM0,%XMM2 |
(1427) 0x4a4f60 VFMADD231SD (%RCX,%R11,1),%XMM1,%XMM2 |
(1427) 0x4a4f66 VSHUFPD $0x1,%XMM1,%XMM1,%XMM3 |
(1427) 0x4a4f6b VFMADD231SD (%RSI,%R11,1),%XMM3,%XMM2 |
(1427) 0x4a4f71 VADDSD %XMM0,%XMM1,%XMM0 |
(1427) 0x4a4f75 MOV -0x30(%RBP),%RDI |
(1427) 0x4a4f79 VADDSD (%RDI,%R10,1),%XMM3,%XMM1 |
(1427) 0x4a4f7f VADDSD %XMM0,%XMM1,%XMM0 |
(1427) 0x4a4f83 VDIVSD %XMM0,%XMM2,%XMM0 |
(1427) 0x4a4f87 MOV -0x38(%RBP),%RDI |
(1427) 0x4a4f8b VMOVSD %XMM0,(%RDI,%R10,1) |
(1427) 0x4a4f91 MOV %R13,%RDI |
(1427) 0x4a4f94 MOV %RAX,%R13 |
(1427) 0x4a4f97 MOV %RDX,%RAX |
(1427) 0x4a4f9a MOV %R15,%RDX |
(1427) 0x4a4f9d MOV %R9,%R15 |
(1427) 0x4a4fa0 VADDSD %XMM0,%XMM0,%XMM0 |
(1427) 0x4a4fa4 VSUBSD (%R14,%R8,8),%XMM0,%XMM1 |
(1427) 0x4a4faa VMOVSD %XMM1,(%R14,%R8,8) |
(1427) 0x4a4fb0 VSUBSD (%RCX,%R11,1),%XMM0,%XMM1 |
(1427) 0x4a4fb6 VMOVSD %XMM1,(%RCX,%R11,1) |
(1427) 0x4a4fbc VSUBSD (%RSI,%R11,1),%XMM0,%XMM0 |
(1427) 0x4a4fc2 VMOVSD %XMM0,(%RSI,%R11,1) |
(1427) 0x4a4fc8 ADD %RDI,%R11 |
(1427) 0x4a4fcb ADD %RAX,%R10 |
(1427) 0x4a4fce DEC %R12 |
(1427) 0x4a4fd1 JNE 4a4f00 |
(1426) 0x4a4fd7 JMP 4a4e40 |
0x4a5000 MOV %R13,%RAX |
0x4a5003 MOV %R15,%RCX |
0x4a5006 MOV %R14,%RDX |
0x4a5009 MOV -0x3a8(%RBP),%RSI |
0x4a5010 XOR %EDI,%EDI |
0x4a5012 MOV -0xf0(%RBP),%R12 |
0x4a5019 MOV -0x70(%RBP),%R15 |
0x4a501d MOV -0x48(%RBP),%RBX |
0x4a5021 MOV -0x228(%RBP),%R14 |
0x4a5028 MOV -0x78(%RBP),%R13 |
0x4a502c JMP 4a5065 |
(1424) 0x4a5040 ADD -0x50(%RBP),%RSI |
(1424) 0x4a5044 MOV -0x100(%RBP),%R8 |
(1424) 0x4a504b ADD %R8,%RDX |
(1424) 0x4a504e ADD %R8,%RCX |
(1424) 0x4a5051 ADD %R8,%RAX |
(1424) 0x4a5054 CMP -0x108(%RBP),%RDI |
(1424) 0x4a505b LEA 0x1(%RDI),%RDI |
(1424) 0x4a505f JE 4a4bc0 |
(1424) 0x4a5065 CMPQ $0,-0x80(%RBP) |
(1424) 0x4a506a JLE 4a5040 |
(1424) 0x4a506c MOV -0xf8(%RBP),%R8 |
(1424) 0x4a5073 VMOVSD (%R8),%XMM1 |
(1424) 0x4a5078 MOV -0xd8(%RBP),%R8 |
(1424) 0x4a507f IMUL %RDI,%R8 |
(1424) 0x4a5083 MOV -0x40(%RBP),%R9 |
(1424) 0x4a5087 ADD %R8,%R9 |
(1424) 0x4a508a ADD -0x220(%RBP),%R8 |
(1424) 0x4a5091 ADD -0xe0(%RBP),%R8 |
(1424) 0x4a5098 VMOVSD (%R12,%R8,8),%XMM0 |
(1424) 0x4a509e MOV -0x58(%RBP),%R10 |
(1424) 0x4a50a2 VMOVSD (%R10),%XMM2 |
(1424) 0x4a50a7 MOV -0x118(%RBP),%R10 |
(1424) 0x4a50ae VMOVHPD (%R10),%XMM2,%XMM2 |
(1424) 0x4a50b3 MOV -0xe8(%RBP),%R10 |
(1424) 0x4a50ba VMOVSD (%R10,%R9,8),%XMM3 |
(1424) 0x4a50c0 MOV -0x230(%RBP),%R9 |
(1424) 0x4a50c7 VMOVHPD (%R9),%XMM3,%XMM3 |
(1424) 0x4a50cc VADDSD %XMM1,%XMM1,%XMM1 |
(1424) 0x4a50d0 VADDPD %XMM2,%XMM2,%XMM2 |
(1424) 0x4a50d4 VDIVPD %XMM3,%XMM2,%XMM2 |
(1424) 0x4a50d8 VSHUFPD $0x1,%XMM2,%XMM2,%XMM3 |
(1424) 0x4a50dd VADDSD %XMM3,%XMM2,%XMM4 |
(1424) 0x4a50e1 XOR %R9D,%R9D |
(1424) 0x4a50e4 XOR %R10D,%R10D |
(1424) 0x4a50e7 MOV -0x80(%RBP),%R11 |
(1424) 0x4a50eb NOPL (%RAX,%RAX,1) |
(1425) 0x4a50f0 VDIVSD (%R14,%R10,1),%XMM1,%XMM5 |
(1425) 0x4a50f6 VMOVSD (%RAX,%R9,1),%XMM6 |
(1425) 0x4a50fc VMOVSD (%R13,%R10,1),%XMM7 |
(1425) 0x4a5103 VFMADD231SD %XMM5,%XMM0,%XMM6 |
(1425) 0x4a5108 VMOVSD (%RSI,%R10,1),%XMM8 |
(1425) 0x4a510e VADDSD %XMM5,%XMM4,%XMM5 |
(1425) 0x4a5112 VADDSD (%RCX,%R9,1),%XMM5,%XMM5 |
(1425) 0x4a5118 VFMADD231SD %XMM2,%XMM7,%XMM6 |
(1425) 0x4a511d VFMADD231SD %XMM3,%XMM8,%XMM6 |
(1425) 0x4a5122 VDIVSD %XMM5,%XMM6,%XMM5 |
(1425) 0x4a5126 VADDSD %XMM5,%XMM5,%XMM6 |
(1425) 0x4a512a VSUBSD %XMM7,%XMM6,%XMM7 |
(1425) 0x4a512e VMOVSD %XMM5,(%RDX,%R9,1) |
(1425) 0x4a5134 VMOVSD %XMM7,(%R13,%R10,1) |
(1425) 0x4a513b VSUBSD %XMM0,%XMM6,%XMM0 |
(1425) 0x4a513f VSUBSD %XMM8,%XMM6,%XMM5 |
(1425) 0x4a5144 VMOVSD %XMM5,(%RSI,%R10,1) |
(1425) 0x4a514a ADD %R15,%R10 |
(1425) 0x4a514d ADD %RBX,%R9 |
(1425) 0x4a5150 DEC %R11 |
(1425) 0x4a5153 JNE 4a50f0 |
(1424) 0x4a5155 VMOVSD %XMM0,(%R12,%R8,8) |
(1424) 0x4a515b JMP 4a5040 |
/scratch_na/users/xoserete/qaas_runs/171-416-9860/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/loop/forall.hpp: 59 - 59 |
-------------------------------------------------------------------------------- |
59: for (decltype(distance_it) i = 0; i < distance_it; ++i) { |
/scratch_na/users/xoserete/qaas_runs/171-416-9860/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/View.hpp: 110 - 110 |
-------------------------------------------------------------------------------- |
110: return data[idx]; |
/scratch_na/users/xoserete/qaas_runs/171-416-9860/intel/Kripke/build/Kripke/src/Kripke/Kernel/SweepSubdomain.cpp: 87 - 105 |
-------------------------------------------------------------------------------- |
87: double xcos_dxi = 2.0 * xcos(d) / dx(i); |
88: double ycos_dyj = 2.0 * ycos(d) / dy(j); |
89: double zcos_dzk = 2.0 * zcos(d) / dz(k); |
90: |
91: Zone z(zone_layout(*i, *j, *k)); |
92: |
93: /* Calculate new zonal flux */ |
94: double psi_d_g_z = (rhs(d,g,z) |
95: + psi_lf(d, g, j, k) * xcos_dxi |
96: + psi_fr(d, g, i, k) * ycos_dyj |
97: + psi_bo(d, g, i, j) * zcos_dzk) |
98: / (xcos_dxi + ycos_dyj + zcos_dzk + sigt(g, z)); |
99: |
100: psi(d, g, z) = psi_d_g_z; |
101: |
102: /* Apply diamond-difference relationships */ |
103: psi_lf(d, g, j, k) = 2.0 * psi_d_g_z - psi_lf(d, g, j, k); |
104: psi_fr(d, g, i, k) = 2.0 * psi_d_g_z - psi_fr(d, g, i, k); |
105: psi_bo(d, g, i, j) = 2.0 * psi_d_g_z - psi_bo(d, g, i, j); |
Coverage (%) | Name | Source Location | Module |
---|---|---|---|
►100.00+ | __kmp_invoke_microtask | libiomp5.so | |
○ | __kmp_invoke_task_func | libiomp5.so |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 9.41 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.15 |
Bottlenecks | |
Function | void Kripke::DispatchHelper |
Source | forall.hpp:59-59,View.hpp:110-110,SweepSubdomain.cpp:89-89,SweepSubdomain.cpp:94-100,SweepSubdomain.cpp:103-104 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 18.67 |
CQA cycles if no scalar integer | 18.67 |
CQA cycles if FP arith vectorized | 18.67 |
CQA cycles if fully vectorized | 1.98 |
Front-end cycles | 18.67 |
DIV/SQRT cycles | 4.80 |
P0 cycles | 7.60 |
P1 cycles | 14.17 |
P2 cycles | 14.17 |
P3 cycles | 16.25 |
P4 cycles | 4.80 |
P5 cycles | 4.80 |
P6 cycles | 16.25 |
P7 cycles | 16.25 |
P8 cycles | 16.25 |
P9 cycles | 4.80 |
P10 cycles | 14.17 |
P11 cycles | 0.00 |
Inter-iter dependencies cycles | 0 |
FE+BE cycles (UFS) | 18.63 |
Stall cycles (UFS) | 0.00 |
Nb insns | 111.00 |
Nb uops | 112.00 |
Nb loads | 42.50 |
Nb stores | 31.50 |
Nb stack references | 67.00 |
FLOP/cycle | 0.00 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 31.73 |
Bytes prefetched | 0.00 |
Bytes loaded | 340.00 |
Bytes stored | 252.00 |
Stride 0 | 1.00 |
Stride 1 | 0.00 |
Stride n | 0.50 |
Stride unknown | 5.00 |
Stride indirect | 0.00 |
Vectorization ratio all | 0.00 |
Vectorization ratio load | 0.00 |
Vectorization ratio store | 0.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | 0.00 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 0.00 |
Vector-efficiency ratio all | 12.35 |
Vector-efficiency ratio load | 12.50 |
Vector-efficiency ratio store | 12.40 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | 12.50 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 10.94 |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 9.74 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.20 |
Bottlenecks | micro-operation queue, |
Function | void Kripke::DispatchHelper |
Source | forall.hpp:59-59,View.hpp:110-110,SweepSubdomain.cpp:89-89,SweepSubdomain.cpp:94-100,SweepSubdomain.cpp:103-104 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 19.17 |
CQA cycles if no scalar integer | 19.17 |
CQA cycles if FP arith vectorized | 19.17 |
CQA cycles if fully vectorized | 1.97 |
Front-end cycles | 19.17 |
DIV/SQRT cycles | 4.80 |
P0 cycles | 7.60 |
P1 cycles | 14.67 |
P2 cycles | 14.67 |
P3 cycles | 16.00 |
P4 cycles | 4.80 |
P5 cycles | 4.80 |
P6 cycles | 16.00 |
P7 cycles | 16.00 |
P8 cycles | 16.00 |
P9 cycles | 4.80 |
P10 cycles | 14.67 |
P11 cycles | 0.00 |
Inter-iter dependencies cycles | 0 |
FE+BE cycles (UFS) | 19.13 |
Stall cycles (UFS) | 0.00 |
Nb insns | 114.00 |
Nb uops | 115.00 |
Nb loads | 44.00 |
Nb stores | 31.00 |
Nb stack references | 68.00 |
FLOP/cycle | 0.00 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 31.30 |
Bytes prefetched | 0.00 |
Bytes loaded | 352.00 |
Bytes stored | 248.00 |
Stride 0 | 1.00 |
Stride 1 | 0.00 |
Stride n | 1.00 |
Stride unknown | 10.00 |
Stride indirect | 0.00 |
Vectorization ratio all | 0.00 |
Vectorization ratio load | 0.00 |
Vectorization ratio store | 0.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | 0.00 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 0.00 |
Vector-efficiency ratio all | 12.36 |
Vector-efficiency ratio load | 12.50 |
Vector-efficiency ratio store | 12.50 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | 12.50 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 9.38 |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 9.08 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.10 |
Bottlenecks | micro-operation queue, |
Function | void Kripke::DispatchHelper |
Source | forall.hpp:59-59,View.hpp:110-110,SweepSubdomain.cpp:89-89,SweepSubdomain.cpp:94-100,SweepSubdomain.cpp:103-104 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 18.17 |
CQA cycles if no scalar integer | 18.17 |
CQA cycles if FP arith vectorized | 18.17 |
CQA cycles if fully vectorized | 2.00 |
Front-end cycles | 18.17 |
DIV/SQRT cycles | 4.80 |
P0 cycles | 7.60 |
P1 cycles | 13.67 |
P2 cycles | 13.67 |
P3 cycles | 16.50 |
P4 cycles | 4.80 |
P5 cycles | 4.80 |
P6 cycles | 16.50 |
P7 cycles | 16.50 |
P8 cycles | 16.50 |
P9 cycles | 4.80 |
P10 cycles | 13.67 |
P11 cycles | 0.00 |
Inter-iter dependencies cycles | 0 |
FE+BE cycles (UFS) | 18.13 |
Stall cycles (UFS) | 0.00 |
Nb insns | 108.00 |
Nb uops | 109.00 |
Nb loads | 41.00 |
Nb stores | 32.00 |
Nb stack references | 66.00 |
FLOP/cycle | 0.00 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 32.15 |
Bytes prefetched | 0.00 |
Bytes loaded | 328.00 |
Bytes stored | 256.00 |
Stride 0 | 1.00 |
Stride 1 | 0.00 |
Stride n | 0.00 |
Stride unknown | 0.00 |
Stride indirect | 0.00 |
Vectorization ratio all | 0.00 |
Vectorization ratio load | 0.00 |
Vectorization ratio store | 0.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | 0.00 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 0.00 |
Vector-efficiency ratio all | 12.35 |
Vector-efficiency ratio load | 12.50 |
Vector-efficiency ratio store | 12.30 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | 12.50 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 12.50 |
Path / |
Function | void Kripke::DispatchHelper |
Source file and lines | forall.hpp:59-59 |
Module | exec |
nb instructions | 111 |
nb uops | 112 |
loop length | 641.50 |
used x86 registers | 11.50 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 67 |
micro-operation queue | 18.67 cycles |
front end | 18.67 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 4.80 | 4.80 | 14.17 | 14.17 | 16.25 | 4.80 | 4.80 | 16.25 | 16.25 | 16.25 | 4.80 | 14.17 |
cycles | 4.80 | 7.60 | 14.17 | 14.17 | 16.25 | 4.80 | 4.80 | 16.25 | 16.25 | 16.25 | 4.80 | 14.17 |
Cycles executing div or sqrt instructions | NA |
Longest recurrence chain latency (RecMII) | 0.00 |
FE+BE cycles | 18.63 |
Stall cycles | 0.00 |
Front-end | 18.67 |
Dispatch | 16.25 |
Data deps. | 0.00 |
Overall L1 | 18.67 |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 12% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 10% |
Function | void Kripke::DispatchHelper |
Source file and lines | forall.hpp:59-59 |
Module | exec |
nb instructions | 114 |
nb uops | 115 |
loop length | 649 |
used x86 registers | 12 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 68 |
micro-operation queue | 19.17 cycles |
front end | 19.17 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 4.80 | 4.80 | 14.67 | 14.67 | 16.00 | 4.80 | 4.80 | 16.00 | 16.00 | 16.00 | 4.80 | 14.67 |
cycles | 4.80 | 7.60 | 14.67 | 14.67 | 16.00 | 4.80 | 4.80 | 16.00 | 16.00 | 16.00 | 4.80 | 14.67 |
Cycles executing div or sqrt instructions | NA |
Longest recurrence chain latency (RecMII) | 0.00 |
FE+BE cycles | 19.13 |
Stall cycles | 0.00 |
Front-end | 19.17 |
Dispatch | 16.00 |
Data deps. | 0.00 |
Overall L1 | 19.17 |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 12% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 9% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MOV -0x78(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD -0x3c0(%RBP),%RAX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x78(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV -0x3b8(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0xd0(%RBP),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %RAX,%R14 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV -0xc8(%RBP),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %RAX,%R15 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV -0x458(%RBP),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %RAX,%R13 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV -0x3e8(%RBP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x450(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CMP %R11,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA 0x1(%RDX),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JE 4a4740 <_ZNK6Kripke14DispatchHelperINS_12ArchT_OpenMPEEclINS_11LayoutT_DGZE9SweepSdomJRNS_4Core9DataStoreERNS_6SdomIdEEEEvT_RKT0_DpOT1_.extracted+0x8f0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV -0xf8(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x520(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RAX,-0x518(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV -0x3d0(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x510(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV -0x3c8(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x508(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV -0x58(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x500(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RAX,-0x4f8(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV -0x3e0(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x4f0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV -0x3d8(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x4e8(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV -0x118(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x4e0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RAX,-0x4d8(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV -0x218(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDX,-0x450(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
IMUL %RDX,%RCX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV -0x68(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %RCX,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV -0x3f0(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (%RDX,%RAX,8),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RAX,-0x4d0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RAX,-0x230(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RAX,-0x4c8(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RCX,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
IMUL -0x208(%RBP),%RSI | 1 | 0 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 1 |
MOV -0x428(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %RSI,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV -0xf0(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (%RDX,%RAX,8),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RAX,-0x4c0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV -0x420(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,-0x220(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %RSI,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA (%RDX,%RAX,8),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RAX,-0x4b8(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RCX,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
IMUL -0xb8(%RBP),%RAX | 1 | 0 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 1 |
MOV -0x430(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %RAX,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV -0x210(%RBP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (%RSI,%RDX,8),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RDX,-0x4b0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV -0x448(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %RAX,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA (%RSI,%RDX,8),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RDX,-0x4a8(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
IMUL -0xb0(%RBP),%RCX | 1 | 0 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 1 |
MOV -0x418(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %RCX,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV -0x200(%RBP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (%RSI,%RDX,8),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RDX,-0x4a0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD -0x440(%RBP),%RCX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
LEA (%RSI,%RCX,8),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RCX,-0x498(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV -0x410(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RCX,-0x490(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV -0x408(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RCX,-0x488(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV -0x400(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %RAX,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV -0x1f8(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (%RDX,%RCX,8),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RCX,-0x480(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV -0xc0(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %RAX,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA (%RDX,%RCX,8),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RCX,-0x478(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV -0x3f8(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %RAX,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV -0x1f0(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (%RDX,%RCX,8),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RCX,-0x470(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD -0x438(%RBP),%RAX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
LEA (%RDX,%RAX,8),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RAX,-0x468(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV $0xc,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA -0x520(%RBP),%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CALL 50ef70 <__intel_rtdd_indep> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
TEST %RAX,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
MOV %R13,-0x458(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R14,-0xd0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R15,-0xc8(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JE 4a5000 <_ZNK6Kripke14DispatchHelperINS_12ArchT_OpenMPEEclINS_11LayoutT_DGZE9SweepSdomJRNS_4Core9DataStoreERNS_6SdomIdEEEEvT_RKT0_DpOT1_.extracted+0x11b0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R13,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R15,%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R14,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV -0x3a8(%RBP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
XOR %EDI,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV -0xf0(%RBP),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x70(%RBP),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x48(%RBP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x228(%RBP),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x78(%RBP),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JMP 4a5065 <_ZNK6Kripke14DispatchHelperINS_12ArchT_OpenMPEEclINS_11LayoutT_DGZE9SweepSdomJRNS_4Core9DataStoreERNS_6SdomIdEEEEvT_RKT0_DpOT1_.extracted+0x1215> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
Function | void Kripke::DispatchHelper |
Source file and lines | forall.hpp:59-59 |
Module | exec |
nb instructions | 108 |
nb uops | 109 |
loop length | 634 |
used x86 registers | 11 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 66 |
micro-operation queue | 18.17 cycles |
front end | 18.17 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 4.80 | 4.80 | 13.67 | 13.67 | 16.50 | 4.80 | 4.80 | 16.50 | 16.50 | 16.50 | 4.80 | 13.67 |
cycles | 4.80 | 7.60 | 13.67 | 13.67 | 16.50 | 4.80 | 4.80 | 16.50 | 16.50 | 16.50 | 4.80 | 13.67 |
Cycles executing div or sqrt instructions | NA |
Longest recurrence chain latency (RecMII) | 0.00 |
FE+BE cycles | 18.13 |
Stall cycles | 0.00 |
Front-end | 18.17 |
Dispatch | 16.50 |
Data deps. | 0.00 |
Overall L1 | 18.17 |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 12% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MOV -0x78(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD -0x3c0(%RBP),%RAX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x78(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV -0x3b8(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0xd0(%RBP),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %RAX,%R14 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV -0xc8(%RBP),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %RAX,%R15 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV -0x458(%RBP),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %RAX,%R13 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV -0x3e8(%RBP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x450(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CMP %R11,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA 0x1(%RDX),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JE 4a4740 <_ZNK6Kripke14DispatchHelperINS_12ArchT_OpenMPEEclINS_11LayoutT_DGZE9SweepSdomJRNS_4Core9DataStoreERNS_6SdomIdEEEEvT_RKT0_DpOT1_.extracted+0x8f0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV -0xf8(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x520(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RAX,-0x518(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV -0x3d0(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x510(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV -0x3c8(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x508(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV -0x58(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x500(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RAX,-0x4f8(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV -0x3e0(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x4f0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV -0x3d8(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x4e8(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV -0x118(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x4e0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RAX,-0x4d8(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV -0x218(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDX,-0x450(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
IMUL %RDX,%RCX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV -0x68(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %RCX,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV -0x3f0(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (%RDX,%RAX,8),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RAX,-0x4d0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RAX,-0x230(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RAX,-0x4c8(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RCX,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
IMUL -0x208(%RBP),%RSI | 1 | 0 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 1 |
MOV -0x428(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %RSI,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV -0xf0(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (%RDX,%RAX,8),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RAX,-0x4c0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV -0x420(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,-0x220(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %RSI,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA (%RDX,%RAX,8),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RAX,-0x4b8(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RCX,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
IMUL -0xb8(%RBP),%RAX | 1 | 0 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 1 |
MOV -0x430(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %RAX,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV -0x210(%RBP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (%RSI,%RDX,8),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RDX,-0x4b0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV -0x448(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %RAX,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA (%RSI,%RDX,8),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RDX,-0x4a8(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
IMUL -0xb0(%RBP),%RCX | 1 | 0 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 1 |
MOV -0x418(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %RCX,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV -0x200(%RBP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (%RSI,%RDX,8),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RDX,-0x4a0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD -0x440(%RBP),%RCX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
LEA (%RSI,%RCX,8),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RCX,-0x498(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV -0x410(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RCX,-0x490(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV -0x408(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RCX,-0x488(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV -0x400(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %RAX,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV -0x1f8(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (%RDX,%RCX,8),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RCX,-0x480(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV -0xc0(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %RAX,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA (%RDX,%RCX,8),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RCX,-0x478(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV -0x3f8(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %RAX,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV -0x1f0(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (%RDX,%RCX,8),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RCX,-0x470(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD -0x438(%RBP),%RAX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
LEA (%RDX,%RAX,8),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RAX,-0x468(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV $0xc,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA -0x520(%RBP),%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CALL 50ef70 <__intel_rtdd_indep> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
TEST %RAX,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
MOV %R13,-0x458(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R14,-0xd0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R15,-0xc8(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JE 4a5000 <_ZNK6Kripke14DispatchHelperINS_12ArchT_OpenMPEEclINS_11LayoutT_DGZE9SweepSdomJRNS_4Core9DataStoreERNS_6SdomIdEEEEvT_RKT0_DpOT1_.extracted+0x11b0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV -0x3b0(%RBP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOVQ $0,-0x110(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV -0x78(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x230(%RBP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JMP 4a4e88 <_ZNK6Kripke14DispatchHelperINS_12ArchT_OpenMPEEclINS_11LayoutT_DGZE9SweepSdomJRNS_4Core9DataStoreERNS_6SdomIdEEEEvT_RKT0_DpOT1_.extracted+0x1038> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |