OV - exec - Loop 1391

0x4606cc ADD	W4, W4, #1

0x4606d0 MOVZ	X18, #0

0x4606d4 SCVTF	D27, W4

0x4606d8 FMUL	D28, D27, D9

0x4606dc FMADD	D29, D8, D28, D19

0x4606e0 FABS	D31, D29

0x4606e4 FCMPE	D31, D17

0x4606e8 CSINC	W25, WZR, WZR, #8

0x4606ec AND	W17, W2, W25

0x4606f0 CMP	W1, #0

0x4606f4 CCMP	W17, #0, #4, #1

0x4606f8 B.NE	46070c

0x4606fc CMP	W3, #0

0x460700 CCMP	W17, #0, #4, #1

0x460704 CSINC	X18, XZR, XZR, #0

0x460708 SUB	X18, X6, X18

0x46070c ADD	W4, W4, #1

0x460710 LDR	D0, [X0, X18,LSL #3]    [1]

0x460714 MOVZ	X17, #0

0x460718 SCVTF	D2, W4

0x46071c FADD	D4, D0, D10

0x460720 FMUL	D1, D2, D9

0x460724 STR	D4, [X0, X18,LSL #3]    [1]

0x460728 FMADD	D23, D8, D1, D19

0x46072c FABS	D24, D23

0x460730 FCMPE	D24, D17

0x460734 CSINC	W25, WZR, WZR, #8

0x460738 AND	W18, W2, W25

0x46073c CMP	W1, #0

0x460740 CCMP	W18, #0, #4, #1

0x460744 B.NE	460758

0x460748 CMP	W3, #0

0x46074c CCMP	W18, #0, #4, #1

0x460750 CSINC	X17, XZR, XZR, #0

0x460754 SUB	X17, X6, X17

0x460758 LDR	D25, [X0, X17,LSL #3]    [2]

0x46075c FADD	D26, D25, D10

0x460760 STR	D26, [X0, X17,LSL #3]    [2]

0x460764 CMP	W20, W4

0x460768 B.NE	4606cc

/usr/include/c++/11/bits/std_abs.h: 72 - 72

--------------------------------------------------------------------------------

72:   { return __builtin_fabs(__x); }

/home/hbollore/qaas/qaas-runs/169-817-5851/intel/Kripke/build/Kripke/src/Kripke/Generate/Space.cpp: 151 - 228

--------------------------------------------------------------------------------

151:     if(x <= 10.0 && y <= 10.0 && z <= 10.0){

152:       return Material{0};

153:     }

154:

155:     // Leg 1 of Region 2

156:     if(x <= 10.0 && y <= 60.0 && z <= 10.0){

[...]

221:               for(int sk = 0;sk < num_subsamples;++ sk){

222:

223:                 double x = xi + dx*(si+1)/(num_subsamples+1);

224:                 double y = yi + dy*(sj+1)/(num_subsamples+1);

225:                 double z = zi + dz*(sk+1)/(num_subsamples+1);

226:

227:                 Material mat = material_fcn(x, y, z);

228:                 sdom_mix[zone].fraction[*mat] += sample_vol_frac;

Coverage (%)	Name	Source Location	Module
►100.00+	Kripke::generateProblem(Kripke[...]	Generate.cpp:53	exec
○	main	kripke.cpp:482	exec
○	__libc_start_main		libc-2.31.so
○	_start	iostream:74	exec

Path /

Metric	Value
CQA speedup if no scalar integer	4.31
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.15
Bottlenecks	P2, P3, P4, P5,
Function	Kripke::Generate::generateSpace(Kripke::Core::DataStore&, InputVariables const&)
Source	std_abs.h:72-72,Space.cpp:151-156,Space.cpp:221-228
Source loop unroll info	multi-versionned
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	5.75
CQA cycles if no scalar integer	1.33
CQA cycles if FP arith vectorized	5.75
CQA cycles if fully vectorized	0.72
Front-end cycles	5.00
DIV/SQRT cycles	1.50
P0 cycles	1.50
P1 cycles	5.75
P2 cycles	5.75
P3 cycles	5.75
P4 cycles	5.75
P5 cycles	3.00
P6 cycles	3.00
P7 cycles	3.00
P8 cycles	3.00
P9 cycles	1.33
P10 cycles	1.33
P11 cycles	1.33
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	40.00
Nb uops	40.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	1.39
Nb FLOP add-sub	2.00
Nb FLOP mul	2.00
Nb FLOP fma	2.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	5.57
Bytes prefetched	0.00
Bytes loaded	16.00
Bytes stored	16.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	16.07
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Metric	Value
CQA speedup if no scalar integer	4.31
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.15
Bottlenecks	P2, P3, P4, P5,
Function	Kripke::Generate::generateSpace(Kripke::Core::DataStore&, InputVariables const&)
Source	std_abs.h:72-72,Space.cpp:151-156,Space.cpp:221-228
Source loop unroll info	multi-versionned
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	5.75
CQA cycles if no scalar integer	1.33
CQA cycles if FP arith vectorized	5.75
CQA cycles if fully vectorized	0.72
Front-end cycles	5.00
DIV/SQRT cycles	1.50
P0 cycles	1.50
P1 cycles	5.75
P2 cycles	5.75
P3 cycles	5.75
P4 cycles	5.75
P5 cycles	3.00
P6 cycles	3.00
P7 cycles	3.00
P8 cycles	3.00
P9 cycles	1.33
P10 cycles	1.33
P11 cycles	1.33
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	40.00
Nb uops	40.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	1.39
Nb FLOP add-sub	2.00
Nb FLOP mul	2.00
Nb FLOP fma	2.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	5.57
Bytes prefetched	0.00
Bytes loaded	16.00
Bytes stored	16.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	16.07
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	Kripke::Generate::generateSpace(Kripke::Core::DataStore&, InputVariables const&)
Source file and lines	Space.cpp:151-228
Module	exec

The loop is defined in:

/usr/include/c++/11/bits/std_abs.h:72
/home/hbollore/qaas/qaas-runs/169-817-5851/intel/Kripke/build/Kripke/src/Kripke/Generate/Space.cpp:151-156,221-228

The related source loop is multi-versionned.
Warnings:

Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 5.75 to 1.33 cycles (4.31x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 16% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 5.75 to 0.72 cycles (8.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 2 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Conversion instructions

Detected expensive conversion instructions.

Details

SCVTF: 2 occurrences

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 8 FP arithmetical operations:

4: addition or subtraction (2 inside FMA instructions)
4: multiply (2 inside FMA instructions)

The binary loop is loading 16 bytes. The binary loop is storing 16 bytes.

Arithmetic intensity

Arithmetic intensity is 0.25 FP operations per loaded or stored byte.

General properties

nb instructions	40
loop length	160
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

5.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	5.75	5.75	5.75	5.75	3.00	3.00	3.00	3.00	1.33	1.33	1.33	0.00	0.00
cycles	1.50	1.50	5.75	5.75	5.75	5.75	3.00	3.00	3.00	3.00	1.33	1.33	1.33	0.00	0.00

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	5.00
Overall L1	5.75

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 5.75 cycles. At this rate:

2% of peak load performance is reached (2.78 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (2.78 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 46072c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput
ADD W4, W4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MOVZ X18, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
SCVTF D27, W4	1	0	0	0	0	1	0	0	0	0	0	0	0	0	3	1
FMUL D28, D27, D9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FMADD D29, D8, D28, D19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FABS D31, D29	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FCMPE D31, D17	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
CSINC W25, WZR, WZR, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
AND W17, W2, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP W1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
CCMP W17, #0, #4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
B.NE 46070c <_ZN6Kripke8Generate13generateSpaceERNS_4Core9DataStoreERK14InputVariables+0x1784>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W3, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
CCMP W17, #0, #4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CSINC X18, XZR, XZR, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
SUB X18, X6, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD W4, W4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D0, [X0, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
MOVZ X17, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
SCVTF D2, W4	1	0	0	0	0	1	0	0	0	0	0	0	0	0	3	1
FADD D4, D0, D10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FMUL D1, D2, D9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
STR D4, [X0, X18,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
FMADD D23, D8, D1, D19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FABS D24, D23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FCMPE D24, D17	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
CSINC W25, WZR, WZR, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
AND W18, W2, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP W1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
CCMP W18, #0, #4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
B.NE 460758 <_ZN6Kripke8Generate13generateSpaceERNS_4Core9DataStoreERK14InputVariables+0x17d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W3, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
CCMP W18, #0, #4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CSINC X17, XZR, XZR, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
SUB X17, X6, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D25, [X0, X17,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FADD D26, D25, D10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
STR D26, [X0, X17,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
CMP W20, W4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.NE 4606cc <_ZN6Kripke8Generate13generateSpaceERNS_4Core9DataStoreERK14InputVariables+0x1744>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	Kripke::Generate::generateSpace(Kripke::Core::DataStore&, InputVariables const&)
Source file and lines	Space.cpp:151-228
Module	exec

The loop is defined in:

/usr/include/c++/11/bits/std_abs.h:72
/home/hbollore/qaas/qaas-runs/169-817-5851/intel/Kripke/build/Kripke/src/Kripke/Generate/Space.cpp:151-156,221-228

The related source loop is multi-versionned.
Warnings:

Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 5.75 to 1.33 cycles (4.31x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 16% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 5.75 to 0.72 cycles (8.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 2 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Conversion instructions

Detected expensive conversion instructions.

Details

SCVTF: 2 occurrences

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 8 FP arithmetical operations:

4: addition or subtraction (2 inside FMA instructions)
4: multiply (2 inside FMA instructions)

The binary loop is loading 16 bytes. The binary loop is storing 16 bytes.

Arithmetic intensity

Arithmetic intensity is 0.25 FP operations per loaded or stored byte.

General properties

nb instructions	40
loop length	160
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

5.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	5.75	5.75	5.75	5.75	3.00	3.00	3.00	3.00	1.33	1.33	1.33	0.00	0.00
cycles	1.50	1.50	5.75	5.75	5.75	5.75	3.00	3.00	3.00	3.00	1.33	1.33	1.33	0.00	0.00

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	5.00
Overall L1	5.75

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 5.75 cycles. At this rate:

2% of peak load performance is reached (2.78 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (2.78 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 46072c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput
ADD W4, W4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MOVZ X18, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
SCVTF D27, W4	1	0	0	0	0	1	0	0	0	0	0	0	0	0	3	1
FMUL D28, D27, D9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FMADD D29, D8, D28, D19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FABS D31, D29	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FCMPE D31, D17	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
CSINC W25, WZR, WZR, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
AND W17, W2, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP W1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
CCMP W17, #0, #4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
B.NE 46070c <_ZN6Kripke8Generate13generateSpaceERNS_4Core9DataStoreERK14InputVariables+0x1784>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W3, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
CCMP W17, #0, #4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CSINC X18, XZR, XZR, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
SUB X18, X6, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD W4, W4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D0, [X0, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
MOVZ X17, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
SCVTF D2, W4	1	0	0	0	0	1	0	0	0	0	0	0	0	0	3	1
FADD D4, D0, D10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FMUL D1, D2, D9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
STR D4, [X0, X18,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
FMADD D23, D8, D1, D19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FABS D24, D23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FCMPE D24, D17	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
CSINC W25, WZR, WZR, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
AND W18, W2, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP W1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
CCMP W18, #0, #4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
B.NE 460758 <_ZN6Kripke8Generate13generateSpaceERNS_4Core9DataStoreERK14InputVariables+0x17d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W3, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
CCMP W18, #0, #4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CSINC X17, XZR, XZR, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
SUB X17, X6, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D25, [X0, X17,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FADD D26, D25, D10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
STR D26, [X0, X17,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
CMP W20, W4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.NE 4606cc <_ZN6Kripke8Generate13generateSpaceERNS_4Core9DataStoreERK14InputVariables+0x1744>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Workaround

Conversion instructions

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Workaround

Conversion instructions

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code