OV - exec - Loop 472

0x421cec ORR	X8, XZR, XZR

0x421cf0 LDR	D7, [X3, X8,LSL #3]    [1]

0x421cf4 CMP	W25, W7

0x421cf8 FADD	D7, D13, D7

0x421cfc STR	D7, [X3, X8,LSL #3]    [1]

0x421d00 B.EQ	421c84

0x421d04 ADD	W7, W7, #1

0x421d08 SCVTF	D7, W7

0x421d0c FMUL	D7, D11, D7

0x421d10 FDIV	D7, D7, D12

0x421d14 FADD	D7, D5, D7

0x421d18 FABS	D7, D7

0x421d1c FCMP	D7, D15

0x421d20 CSEL	W8, WZR, W24, #8

0x421d24 TBNZ	W8, #0, 421cec

/usr/lib/gcc/aarch64-linux-gnu/11/../../../../include/c++/11/bits/std_abs.h: 72 - 72

--------------------------------------------------------------------------------

72:   { return __builtin_fabs(__x); }

/home/hbollore/qaas/qaas-runs/169-817-5851/intel/Kripke/build/Kripke/src/Kripke/Generate/Space.cpp: 151 - 228

--------------------------------------------------------------------------------

151:     if(x <= 10.0 && y <= 10.0 && z <= 10.0){

[...]

220:             for(int sj = 0;sj < num_subsamples;++ sj){

221:               for(int sk = 0;sk < num_subsamples;++ sk){

222:

223:                 double x = xi + dx*(si+1)/(num_subsamples+1);

224:                 double y = yi + dy*(sj+1)/(num_subsamples+1);

225:                 double z = zi + dz*(sk+1)/(num_subsamples+1);

226:

227:                 Material mat = material_fcn(x, y, z);

228:                 sdom_mix[zone].fraction[*mat] += sample_vol_frac;

Coverage (%)	Name	Source Location	Module
►100.00+	Kripke::generateProblem(Kripke[...]	Generate.cpp:53	exec
○	main	kripke.cpp:482	exec
○	__libc_start_main		libc-2.31.so
○	_start	kripke.cpp:0	exec

Path /

Metric	Value
CQA speedup if no scalar integer	1.07
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	3.75 - 7.06
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.07
Bottlenecks	micro-operation queue,
Function	Kripke::Generate::generateSpace(Kripke::Core::DataStore&, InputVariables const&)
Source	std_abs.h:72-72,Space.cpp:151-151,Space.cpp:220-228
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	1.88
CQA cycles if no scalar integer	1.75
CQA cycles if FP arith vectorized	1.88
CQA cycles if fully vectorized	0.50 - 0.27
Front-end cycles	1.88
DIV/SQRT cycles	1.00
P0 cycles	1.00
P1 cycles	1.25
P2 cycles	1.25
P3 cycles	1.25
P4 cycles	1.25
P5 cycles	1.75
P6 cycles	1.75
P7 cycles	1.75
P8 cycles	1.75
P9 cycles	0.83
P10 cycles	0.50
P11 cycles	0.67
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	1.00 - 0.50
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	15.00
Nb uops	15.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	2.13
Nb FLOP add-sub	2.00
Nb FLOP mul	1.00
Nb FLOP fma	0.00
Nb FLOP div	1.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	8.53
Bytes prefetched	0.00
Bytes loaded	8.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	18.75
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Metric	Value
CQA speedup if no scalar integer	1.07
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	3.75 - 7.06
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.07
Bottlenecks	micro-operation queue,
Function	Kripke::Generate::generateSpace(Kripke::Core::DataStore&, InputVariables const&)
Source	std_abs.h:72-72,Space.cpp:151-151,Space.cpp:220-228
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	1.88
CQA cycles if no scalar integer	1.75
CQA cycles if FP arith vectorized	1.88
CQA cycles if fully vectorized	0.50 - 0.27
Front-end cycles	1.88
DIV/SQRT cycles	1.00
P0 cycles	1.00
P1 cycles	1.25
P2 cycles	1.25
P3 cycles	1.25
P4 cycles	1.25
P5 cycles	1.75
P6 cycles	1.75
P7 cycles	1.75
P8 cycles	1.75
P9 cycles	0.83
P10 cycles	0.50
P11 cycles	0.67
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	1.00 - 0.50
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	15.00
Nb uops	15.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	2.13
Nb FLOP add-sub	2.00
Nb FLOP mul	1.00
Nb FLOP fma	0.00
Nb FLOP div	1.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	8.53
Bytes prefetched	0.00
Bytes loaded	8.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	18.75
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	Kripke::Generate::generateSpace(Kripke::Core::DataStore&, InputVariables const&)
Source file and lines	Space.cpp:151-228
Module	exec

The loop is defined in:

/usr/lib/gcc/aarch64-linux-gnu/11/../../../../include/c++/11/bits/std_abs.h:72
/home/hbollore/qaas/qaas-runs/169-817-5851/intel/Kripke/build/Kripke/src/Kripke/Generate/Space.cpp:151,220-228

The related source loop is not unrolled or unrolled with no peel/tail loop.
Warnings:

Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 1.88 to 1.75 cycles (1.07x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 18% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 1.88 to 0.27 cycles (7.06x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Conversion instructions

Detected expensive conversion instructions.

Details

SCVTF: 1 occurrences

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 4 FP arithmetical operations:

2: addition or subtraction
1: multiply
1: divide

The binary loop is loading 8 bytes. The binary loop is storing 8 bytes.

Arithmetic intensity

Arithmetic intensity is 0.25 FP operations per loaded or stored byte.

General properties

nb instructions	15
loop length	60
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.00	1.00	1.25	1.25	1.25	1.25	1.75	1.75	1.75	1.75	0.83	0.50	0.67	0.00	0.00
cycles	1.00	1.00	1.25	1.25	1.25	1.25	1.75	1.75	1.75	1.75	0.83	0.50	0.67	0.00	0.00

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	1.88
Overall L1	1.88

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 1.88 cycles. At this rate:

4% of peak load performance is reached (4.27 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
8% of peak store performance is reached (4.27 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 421d04

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D7, [X3, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
CMP W25, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
FADD D7, D13, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
STR D7, [X3, X8,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
B.EQ 421c84 <_ZN6Kripke8Generate13generateSpaceERNS_4Core9DataStoreERK14InputVariables+0x21a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD W7, W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
SCVTF D7, W7	1	0	0	0	0	1	0	0	0	0	0	0	0	0	3	1
FMUL D7, D11, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FDIV D7, D7, D12	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1-0.50
FADD D7, D5, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FABS D7, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FCMP D7, D15	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
CSEL W8, WZR, W24, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
TBNZ W8, #0, 421cec <_ZN6Kripke8Generate13generateSpaceERNS_4Core9DataStoreERK14InputVariables+0x220c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	Kripke::Generate::generateSpace(Kripke::Core::DataStore&, InputVariables const&)
Source file and lines	Space.cpp:151-228
Module	exec

The loop is defined in:

/usr/lib/gcc/aarch64-linux-gnu/11/../../../../include/c++/11/bits/std_abs.h:72
/home/hbollore/qaas/qaas-runs/169-817-5851/intel/Kripke/build/Kripke/src/Kripke/Generate/Space.cpp:151,220-228

The related source loop is not unrolled or unrolled with no peel/tail loop.
Warnings:

Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 1.88 to 1.75 cycles (1.07x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 18% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 1.88 to 0.27 cycles (7.06x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Conversion instructions

Detected expensive conversion instructions.

Details

SCVTF: 1 occurrences

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 4 FP arithmetical operations:

2: addition or subtraction
1: multiply
1: divide

The binary loop is loading 8 bytes. The binary loop is storing 8 bytes.

Arithmetic intensity

Arithmetic intensity is 0.25 FP operations per loaded or stored byte.

General properties

nb instructions	15
loop length	60
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.00	1.00	1.25	1.25	1.25	1.25	1.75	1.75	1.75	1.75	0.83	0.50	0.67	0.00	0.00
cycles	1.00	1.00	1.25	1.25	1.25	1.25	1.75	1.75	1.75	1.75	0.83	0.50	0.67	0.00	0.00

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	1.88
Overall L1	1.88

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 1.88 cycles. At this rate:

4% of peak load performance is reached (4.27 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
8% of peak store performance is reached (4.27 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 421d04

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D7, [X3, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
CMP W25, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
FADD D7, D13, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
STR D7, [X3, X8,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
B.EQ 421c84 <_ZN6Kripke8Generate13generateSpaceERNS_4Core9DataStoreERK14InputVariables+0x21a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD W7, W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
SCVTF D7, W7	1	0	0	0	0	1	0	0	0	0	0	0	0	0	3	1
FMUL D7, D11, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FDIV D7, D7, D12	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1-0.50
FADD D7, D5, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FABS D7, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FCMP D7, D15	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
CSEL W8, WZR, W24, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
TBNZ W8, #0, 421cec <_ZN6Kripke8Generate13generateSpaceERNS_4Core9DataStoreERK14InputVariables+0x220c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Workaround

Conversion instructions

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Workaround

Conversion instructions

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code