OV - exec - Loop 751

0x433dec CMP	X24, #0

0x433df0 CSEL	X12, XZR, X11, #0

0x433df4 CSINC	X13, XZR, X11, #0

0x433df8 ADD	X11, X11, #2

0x433dfc CMP	X11, X10

0x433e00 STR	XZR, [X26, X12,LSL #3]    [1]

0x433e04 STR	XZR, [X26, X13,LSL #3]    [2]

0x433e08 B.NE	433dec

/home/hbollore/qaas-runs/170-289-7893/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/Layout.hpp: 55 - 55

--------------------------------------------------------------------------------

55:     return a * b;

/home/hbollore/qaas-runs/170-289-7893/intel/Kripke/build/Kripke/src/Kripke/Kernel.h: 45 - 45

--------------------------------------------------------------------------------

45: 			 	  view1d(i) = value;

/home/hbollore/qaas-runs/170-289-7893/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/loop/forall.hpp: 59 - 59

--------------------------------------------------------------------------------

59:   for (decltype(distance_it) i = 0; i < distance_it; ++i) {

Coverage (%)	Name	Source Location	Module
►100.00+	main	kripke.cpp:482	exec
○	__libc_start_main		libc-2.31.so
○	_start	kripke.cpp:0	exec

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.25
Bottlenecks	P2, P3, P4, P5,
Function	Kripke::SteadyStateSolver(Kripke::Core::DataStore&, unsigned long, bool)
Source	Layout.hpp:55-55,Kernel.h:45-45,forall.hpp:59-59
Source loop unroll info	unrolled by 8
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	2
CQA cycles	1.25
CQA cycles if no scalar integer	1.25
CQA cycles if FP arith vectorized	1.25
CQA cycles if fully vectorized	0.31
Front-end cycles	1.00
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	1.25
P2 cycles	1.25
P3 cycles	1.25
P4 cycles	1.25
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	1.00
P10 cycles	1.00
P11 cycles	0.00
P12 cycles	1.00
P13 cycles	1.00
P14 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	8.00
Nb uops	8.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	12.80
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	16.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.25
Bottlenecks	P2, P3, P4, P5,
Function	Kripke::SteadyStateSolver(Kripke::Core::DataStore&, unsigned long, bool)
Source	Layout.hpp:55-55,Kernel.h:45-45,forall.hpp:59-59
Source loop unroll info	unrolled by 8
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	2
CQA cycles	1.25
CQA cycles if no scalar integer	1.25
CQA cycles if FP arith vectorized	1.25
CQA cycles if fully vectorized	0.31
Front-end cycles	1.00
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	1.25
P2 cycles	1.25
P3 cycles	1.25
P4 cycles	1.25
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	1.00
P10 cycles	1.00
P11 cycles	0.00
P12 cycles	1.00
P13 cycles	1.00
P14 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	8.00
Nb uops	8.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	12.80
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	16.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	Kripke::SteadyStateSolver(Kripke::Core::DataStore&, unsigned long, bool)
Source file and lines	forall.hpp:59-59
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/170-289-7893/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/Layout.hpp:55
/home/hbollore/qaas-runs/170-289-7893/intel/Kripke/build/Kripke/src/Kripke/Kernel.h:45
/home/hbollore/qaas-runs/170-289-7893/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/loop/forall.hpp:59

The related source loop is unrolled by 8 (including vectorization).

gain
potential
hint
expert

Unrolling/vectorization cost

This loop is peel/tail of a unrolled/vectorized loop. If its cost is not negligible compared to the main (unrolled/vectorized) loop, unrolling/vectorization is counterproductive due to low trip count.

Details

The more iterations the main loop is processing, the higher the trip count must be to amortize peel/tail overhead.

Workaround

use profile-guided optimization flags of your compiler
hardcode most frequent values of loop bounds by adding specialized paths.:
- For instance, replace for (i=0; i<n; i++) foo(i) with: switch (n) { case (4): for (i=0; i<4; i++) foo(i); break; case (6): for (i=0; i<6; i++) foo(i); break; default : for (i=0; i<n; i++) foo(i); break; }

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers.

Details

All VPU instructions are used in scalar version (process only one data element in vector registers).

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is storing 16 bytes.

General properties

nb instructions	8
loop length	32
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	1.25	1.25	1.25	1.25	0.00	0.00	0.00	0.00	1.00	1.00	0.00	1.00	1.00
cycles	0.50	0.50	1.25	1.25	1.25	1.25	0.00	0.00	0.00	0.00	1.00	1.00	0.00	1.00	1.00

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	1.00
Data deps.	1.00
Overall L1	1.25

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 1.25 cycles. At this rate:

26% of peak store performance is reached (12.80 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 433dec

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P13	P14	Latency	Recip. throughput
CMP X24, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33
CSEL X12, XZR, X11, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
CSINC X13, XZR, X11, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
ADD X11, X11, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
CMP X11, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33
STR XZR, [X26, X12,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50
STR XZR, [X26, X13,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50
B.NE 433dec <_ZN6Kripke17SteadyStateSolverERNS_4Core9DataStoreEmb+0x10cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	1	0.50

Function	Kripke::SteadyStateSolver(Kripke::Core::DataStore&, unsigned long, bool)
Source file and lines	forall.hpp:59-59
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/170-289-7893/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/Layout.hpp:55
/home/hbollore/qaas-runs/170-289-7893/intel/Kripke/build/Kripke/src/Kripke/Kernel.h:45
/home/hbollore/qaas-runs/170-289-7893/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/loop/forall.hpp:59

The related source loop is unrolled by 8 (including vectorization).

gain
potential
hint
expert

Unrolling/vectorization cost

This loop is peel/tail of a unrolled/vectorized loop. If its cost is not negligible compared to the main (unrolled/vectorized) loop, unrolling/vectorization is counterproductive due to low trip count.

Details

The more iterations the main loop is processing, the higher the trip count must be to amortize peel/tail overhead.

Workaround

use profile-guided optimization flags of your compiler
hardcode most frequent values of loop bounds by adding specialized paths.:
- For instance, replace for (i=0; i<n; i++) foo(i) with: switch (n) { case (4): for (i=0; i<4; i++) foo(i); break; case (6): for (i=0; i<6; i++) foo(i); break; default : for (i=0; i<n; i++) foo(i); break; }

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers.

Details

All VPU instructions are used in scalar version (process only one data element in vector registers).

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is storing 16 bytes.

General properties

nb instructions	8
loop length	32
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	1.25	1.25	1.25	1.25	0.00	0.00	0.00	0.00	1.00	1.00	0.00	1.00	1.00
cycles	0.50	0.50	1.25	1.25	1.25	1.25	0.00	0.00	0.00	0.00	1.00	1.00	0.00	1.00	1.00

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	1.00
Data deps.	1.00
Overall L1	1.25

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 1.25 cycles. At this rate:

26% of peak store performance is reached (12.80 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 433dec

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P13	P14	Latency	Recip. throughput
CMP X24, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33
CSEL X12, XZR, X11, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
CSINC X13, XZR, X11, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
ADD X11, X11, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
CMP X11, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33
STR XZR, [X26, X12,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50
STR XZR, [X26, X13,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50
B.NE 433dec <_ZN6Kripke17SteadyStateSolverERNS_4Core9DataStoreEmb+0x10cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Unrolling/vectorization cost

Details

Workaround

Vectorization

Details

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Unrolling/vectorization cost

Details

Workaround

Vectorization

Details

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code