OV - exec - Loop 2072

0x484564 ADD	X0, X18, X17

0x484568 STR	XZR, [X18]    [6]

0x48456c ADD	X1, X1, #8

0x484570 ADD	X24, X0, X17

0x484574 STR	XZR, [X18, X17]    [1]

0x484578 ADD	X25, X24, X17

0x48457c STR	XZR, [X0, X17]    [5]

0x484580 ADD	X30, X25, X17

0x484584 STR	XZR, [X24, X17]    [3]

0x484588 ADD	X3, X30, X17

0x48458c STR	XZR, [X25, X17]    [4]

0x484590 ADD	X4, X3, X17

0x484594 STR	XZR, [X30, X17]    [2]

0x484598 STR	XZR, [X3, X17]    [8]

0x48459c ADD	X18, X4, X17,LSL #1

0x4845a0 STR	XZR, [X4, X17]    [7]

0x4845a4 CMP	X21, X1

0x4845a8 B.NE	484564

/home/hbollore/qaas-runs/170-289-7893/intel/Kripke/build/Kripke/src/Kripke/Kernel.h: 45 - 45

--------------------------------------------------------------------------------

45: 			 	  view1d(i) = value;

/home/hbollore/qaas-runs/170-289-7893/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/loop/forall.hpp: 59 - 59

--------------------------------------------------------------------------------

59:   for (decltype(distance_it) i = 0; i < distance_it; ++i) {

Coverage (%)	Name	Source Location	Module
►100.00+	main	new_allocator.h:79	exec
○	__libc_start_main		libc-2.31.so
○	_start	iostream:74	exec

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	NA
CQA speedup if fully vectorized	NA
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.75
Bottlenecks
Function	Kripke::SteadyStateSolver(Kripke::Core::DataStore&, unsigned long, bool)
Source	Kernel.h:45-45,forall.hpp:59-59
Source loop unroll info	multi-versionned
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	7.00
CQA cycles if no scalar integer	7.00
CQA cycles if FP arith vectorized	NA
CQA cycles if fully vectorized	NA
Front-end cycles	2.25
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	2.25
P2 cycles	2.25
P3 cycles	2.25
P4 cycles	2.25
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	4.00
P10 cycles	4.00
P11 cycles	0.00
P12 cycles	4.00
P13 cycles	4.00
P14 cycles	0.00
Inter-iter dependencies cycles	7
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	18.00
Nb uops	18.00
Nb loads	NA
Nb stores	8.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	9.14
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	64.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	NA
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	NA
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	NA
CQA speedup if fully vectorized	NA
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.75
Bottlenecks
Function	Kripke::SteadyStateSolver(Kripke::Core::DataStore&, unsigned long, bool)
Source	Kernel.h:45-45,forall.hpp:59-59
Source loop unroll info	multi-versionned
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	7.00
CQA cycles if no scalar integer	7.00
CQA cycles if FP arith vectorized	NA
CQA cycles if fully vectorized	NA
Front-end cycles	2.25
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	2.25
P2 cycles	2.25
P3 cycles	2.25
P4 cycles	2.25
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	4.00
P10 cycles	4.00
P11 cycles	0.00
P12 cycles	4.00
P13 cycles	4.00
P14 cycles	0.00
Inter-iter dependencies cycles	7
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	18.00
Nb uops	18.00
Nb loads	NA
Nb stores	8.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	9.14
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	64.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	NA
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	NA
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	Kripke::SteadyStateSolver(Kripke::Core::DataStore&, unsigned long, bool)
Source file and lines	forall.hpp:59-59
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/170-289-7893/intel/Kripke/build/Kripke/src/Kripke/Kernel.h:45
/home/hbollore/qaas-runs/170-289-7893/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/loop/forall.hpp:59

The related source loop is multi-versionned.

gain
potential
hint
expert

Vectorization

Your loop is not vectorized.

Details

No VPU instruction: only general purpose registers are used and data elements are processed one at a time.

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is storing 64 bytes.

General properties

nb instructions	18
loop length	72
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	2.25	2.25	2.25	2.25	0.00	0.00	0.00	0.00	4.00	4.00	0.00	4.00	4.00
cycles	0.50	0.50	2.25	2.25	2.25	2.25	0.00	0.00	0.00	0.00	4.00	4.00	0.00	4.00	4.00

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	7.00

Cycles summary

Front-end	2.25
Data deps.	7.00
Overall L1	7.00

Vectorization ratios

No vectorizable/vectorized instructions

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 7.00 cycles. At this rate:

19% of peak store performance is reached (9.14 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 484564

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P13	P14	Latency	Recip. throughput
ADD X0, X18, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
STR XZR, [X18]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50
ADD X1, X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
ADD X24, X0, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
STR XZR, [X18, X17]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50
ADD X25, X24, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
STR XZR, [X0, X17]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50
ADD X30, X25, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
STR XZR, [X24, X17]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50
ADD X3, X30, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
STR XZR, [X25, X17]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50
ADD X4, X3, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
STR XZR, [X30, X17]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50
STR XZR, [X3, X17]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50
ADD X18, X4, X17,LSL #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
STR XZR, [X4, X17]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50
CMP X21, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33
B.NE 484564 <_ZN6Kripke17SteadyStateSolverERNS_4Core9DataStoreEmb+0x404>	1	0.50	0.50	0	0	0	0	0	0	0	0	1	0.50

Function	Kripke::SteadyStateSolver(Kripke::Core::DataStore&, unsigned long, bool)
Source file and lines	forall.hpp:59-59
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/170-289-7893/intel/Kripke/build/Kripke/src/Kripke/Kernel.h:45
/home/hbollore/qaas-runs/170-289-7893/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/loop/forall.hpp:59

The related source loop is multi-versionned.

gain
potential
hint
expert

Vectorization

Your loop is not vectorized.

Details

No VPU instruction: only general purpose registers are used and data elements are processed one at a time.

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is storing 64 bytes.

General properties

nb instructions	18
loop length	72
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	2.25	2.25	2.25	2.25	0.00	0.00	0.00	0.00	4.00	4.00	0.00	4.00	4.00
cycles	0.50	0.50	2.25	2.25	2.25	2.25	0.00	0.00	0.00	0.00	4.00	4.00	0.00	4.00	4.00

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	7.00

Cycles summary

Front-end	2.25
Data deps.	7.00
Overall L1	7.00

Vectorization ratios

No vectorizable/vectorized instructions

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 7.00 cycles. At this rate:

19% of peak store performance is reached (9.14 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 484564

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P13	P14	Latency	Recip. throughput
ADD X0, X18, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
STR XZR, [X18]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50
ADD X1, X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
ADD X24, X0, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
STR XZR, [X18, X17]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50
ADD X25, X24, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
STR XZR, [X0, X17]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50
ADD X30, X25, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
STR XZR, [X24, X17]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50
ADD X3, X30, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
STR XZR, [X25, X17]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50
ADD X4, X3, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
STR XZR, [X30, X17]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50
STR XZR, [X3, X17]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50
ADD X18, X4, X17,LSL #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
STR XZR, [X4, X17]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50
CMP X21, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33
B.NE 484564 <_ZN6Kripke17SteadyStateSolverERNS_4Core9DataStoreEmb+0x404>	1	0.50	0.50	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code