OV - exec - Loop 707

0x430c84 CMP	X24, #0

0x430c88 CSEL	X11, XZR, X9, #0

0x430c8c STR	XZR, [X20, X11,LSL #3]    [8]

0x430c90 CSINC	X11, XZR, X9, #0

0x430c94 STR	XZR, [X20, X11,LSL #3]    [7]

0x430c98 ADD	X11, X9, #2

0x430c9c CSEL	X11, XZR, X11, #0

0x430ca0 STR	XZR, [X20, X11,LSL #3]    [6]

0x430ca4 ADD	X11, X9, #3

0x430ca8 CSEL	X11, XZR, X11, #0

0x430cac STR	XZR, [X20, X11,LSL #3]    [5]

0x430cb0 ADD	X11, X9, #4

0x430cb4 CSEL	X11, XZR, X11, #0

0x430cb8 STR	XZR, [X20, X11,LSL #3]    [4]

0x430cbc ADD	X11, X9, #5

0x430cc0 CSEL	X11, XZR, X11, #0

0x430cc4 STR	XZR, [X20, X11,LSL #3]    [3]

0x430cc8 ADD	X11, X9, #6

0x430ccc CSEL	X11, XZR, X11, #0

0x430cd0 STR	XZR, [X20, X11,LSL #3]    [2]

0x430cd4 ADD	X11, X9, #7

0x430cd8 ADD	X9, X9, #8

0x430cdc CSEL	X11, XZR, X11, #0

0x430ce0 CMP	X9, X10

0x430ce4 STR	XZR, [X20, X11,LSL #3]    [1]

0x430ce8 B.NE	430c84

/home/hbollore/qaas-runs/170-289-7893/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/Layout.hpp: 55 - 55

--------------------------------------------------------------------------------

55:     return a * b;

/home/hbollore/qaas-runs/170-289-7893/intel/Kripke/build/Kripke/src/Kripke/Kernel.h: 45 - 45

--------------------------------------------------------------------------------

45: 			 	  view1d(i) = value;

/home/hbollore/qaas-runs/170-289-7893/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/loop/forall.hpp: 59 - 59

--------------------------------------------------------------------------------

59:   for (decltype(distance_it) i = 0; i < distance_it; ++i) {

Coverage (%)	Name	Source Location	Module
►100.00+	main	kripke.cpp:482	exec
○	__libc_start_main		libc-2.31.so
○	_start	kripke.cpp:0	exec

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.06
Bottlenecks	P2, P3, P4, P5,
Function	Kripke::SteadyStateSolver(Kripke::Core::DataStore&, unsigned long, bool)
Source	Layout.hpp:55-55,Kernel.h:45-45,forall.hpp:59-59
Source loop unroll info	unrolled by 8
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	8
CQA cycles	4.25
CQA cycles if no scalar integer	4.25
CQA cycles if FP arith vectorized	4.25
CQA cycles if fully vectorized	1.06
Front-end cycles	3.25
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	4.25
P2 cycles	4.25
P3 cycles	4.25
P4 cycles	4.25
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	4.00
P10 cycles	4.00
P11 cycles	0.00
P12 cycles	4.00
P13 cycles	4.00
P14 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	26.00
Nb uops	26.00
Nb loads	NA
Nb stores	8.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	15.06
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	64.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.06
Bottlenecks	P2, P3, P4, P5,
Function	Kripke::SteadyStateSolver(Kripke::Core::DataStore&, unsigned long, bool)
Source	Layout.hpp:55-55,Kernel.h:45-45,forall.hpp:59-59
Source loop unroll info	unrolled by 8
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	8
CQA cycles	4.25
CQA cycles if no scalar integer	4.25
CQA cycles if FP arith vectorized	4.25
CQA cycles if fully vectorized	1.06
Front-end cycles	3.25
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	4.25
P2 cycles	4.25
P3 cycles	4.25
P4 cycles	4.25
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	4.00
P10 cycles	4.00
P11 cycles	0.00
P12 cycles	4.00
P13 cycles	4.00
P14 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	26.00
Nb uops	26.00
Nb loads	NA
Nb stores	8.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	15.06
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	64.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	Kripke::SteadyStateSolver(Kripke::Core::DataStore&, unsigned long, bool)
Source file and lines	forall.hpp:59-59
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/170-289-7893/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/Layout.hpp:55
/home/hbollore/qaas-runs/170-289-7893/intel/Kripke/build/Kripke/src/Kripke/Kernel.h:45
/home/hbollore/qaas-runs/170-289-7893/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/loop/forall.hpp:59

The related source loop is unrolled by 8 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 4.25 to 1.06 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is storing 64 bytes.

General properties

nb instructions	26
loop length	104
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	4.25	4.25	4.25	4.25	0.00	0.00	0.00	0.00	4.00	4.00	0.00	4.00	4.00
cycles	0.50	0.50	4.25	4.25	4.25	4.25	0.00	0.00	0.00	0.00	4.00	4.00	0.00	4.00	4.00

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	3.25
Data deps.	1.00
Overall L1	4.25

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 4.25 cycles. At this rate:

31% of peak store performance is reached (15.06 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 430c84

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P13	P14	Latency	Recip. throughput
CMP X24, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33
CSEL X11, XZR, X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
STR XZR, [X20, X11,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50
CSINC X11, XZR, X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
STR XZR, [X20, X11,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50
ADD X11, X9, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
CSEL X11, XZR, X11, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
STR XZR, [X20, X11,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50
ADD X11, X9, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
CSEL X11, XZR, X11, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
STR XZR, [X20, X11,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50
ADD X11, X9, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
CSEL X11, XZR, X11, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
STR XZR, [X20, X11,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50
ADD X11, X9, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
CSEL X11, XZR, X11, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
STR XZR, [X20, X11,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50
ADD X11, X9, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
CSEL X11, XZR, X11, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
STR XZR, [X20, X11,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50
ADD X11, X9, #7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
ADD X9, X9, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
CSEL X11, XZR, X11, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
CMP X9, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33
STR XZR, [X20, X11,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50
B.NE 430c84 <_ZN6Kripke17SteadyStateSolverERNS_4Core9DataStoreEmb+0xca4>	1	0.50	0.50	0	0	0	0	0	0	0	0	1	0.50

Function	Kripke::SteadyStateSolver(Kripke::Core::DataStore&, unsigned long, bool)
Source file and lines	forall.hpp:59-59
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/170-289-7893/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/Layout.hpp:55
/home/hbollore/qaas-runs/170-289-7893/intel/Kripke/build/Kripke/src/Kripke/Kernel.h:45
/home/hbollore/qaas-runs/170-289-7893/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/loop/forall.hpp:59

The related source loop is unrolled by 8 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 4.25 to 1.06 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is storing 64 bytes.

General properties

nb instructions	26
loop length	104
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	4.25	4.25	4.25	4.25	0.00	0.00	0.00	0.00	4.00	4.00	0.00	4.00	4.00
cycles	0.50	0.50	4.25	4.25	4.25	4.25	0.00	0.00	0.00	0.00	4.00	4.00	0.00	4.00	4.00

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	3.25
Data deps.	1.00
Overall L1	4.25

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 4.25 cycles. At this rate:

31% of peak store performance is reached (15.06 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 430c84

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P13	P14	Latency	Recip. throughput
CMP X24, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33
CSEL X11, XZR, X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
STR XZR, [X20, X11,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50
CSINC X11, XZR, X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
STR XZR, [X20, X11,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50
ADD X11, X9, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
CSEL X11, XZR, X11, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
STR XZR, [X20, X11,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50
ADD X11, X9, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
CSEL X11, XZR, X11, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
STR XZR, [X20, X11,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50
ADD X11, X9, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
CSEL X11, XZR, X11, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
STR XZR, [X20, X11,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50
ADD X11, X9, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
CSEL X11, XZR, X11, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
STR XZR, [X20, X11,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50
ADD X11, X9, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
CSEL X11, XZR, X11, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
STR XZR, [X20, X11,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50
ADD X11, X9, #7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
ADD X9, X9, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
CSEL X11, XZR, X11, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
CMP X9, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33
STR XZR, [X20, X11,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50
B.NE 430c84 <_ZN6Kripke17SteadyStateSolverERNS_4Core9DataStoreEmb+0xca4>	1	0.50	0.50	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code