	*************************************************
	*                                               *
	*          ONE-View report generation           *
	*                                               *
	*************************************************

[MAQAO] Info: Experiment configuration summary is available adding -dbg=1 in command line

* [MAQAO] Warning: Experiment directory /beegfs/hackathon/users/eoseret/qaas_runs_test/178-668-9279/intel/Kripke/run/oneview_runs/defaults/icx/oneview_results_1786689771 already exists and is reused.
           It can be replaced using --replace in the command line.
[MAQAO] Info: 
[MAQAO] Info: START THE APPLICATION PROFILING
[MAQAO] Info: -> RUNNING THE PROFILER...
[MAQAO] Info:   LPROF has already been run
[MAQAO] Info: STOP THE APPLICATION PROFILING
[MAQAO] Info: 
[MAQAO] Info: START FUNCTIONS AND LOOPS ANALYSIS ...
[MAQAO] Info: STOP FUNCTIONS AND LOOPS ANALYSIS ...
[MAQAO] Info: 
[MAQAO] Info: START THE REPORT GENERATION
[MAQAO] Info: -> ONE-VIEW EXPERIMENT DIRECTORY: /beegfs/hackathon/users/eoseret/qaas_runs_test/178-668-9279/intel/Kripke/run/oneview_runs/defaults/icx/oneview_results_1786689771


+====================================================================================================================+
+                                                    1  -  GLOBAL                                                    +
+====================================================================================================================+


+--------------------------------------------------------------------------------------------------------------------+
+                                             1.1  -  Experiment Summary                                             +
+--------------------------------------------------------------------------------------------------------------------+

  Application:			/beegfs/hackathon/users/eoseret/qaas_runs_test/178-668-9279/intel/Kripke/run/oneview_runs/defaults/orig/exec
  Timestamp:			2026-08-14 08:42:51
  Universal Timestamp:		1786689771
  Experiment Type:		MPI; OpenMP; Throughput; 
  Machine:			isix06.benchmarkcenter.megware.com
  Architecture:			x86_64
  Micro Architecture:		GRANITE_RAPIDS
  Model Name:			Intel(R) Xeon(R) 6972P
  Cache Size:			491520 KB
  Number of Cores:		96
  OS Version:			Linux 5.14.0-687.31.1.el9_8.x86_64 #1 SMP PREEMPT_DYNAMIC Sat Aug 1 05:38:01 EDT 2026
  Compilation Options:		
		exec:  --driver-mode=g++ --intel -I /beegfs/hackathon/users/eoseret/qaas_runs_test/178-668-9279/intel/Kripke/build/Kripke/src -I /beegfs/hackathon/users/eoseret/qaas_runs_test/178-668-9279/intel/Kripke/build/build/kripke-build/include -I /beegfs/hackathon/users/eoseret/qaas_runs_test/178-668-9279/intel/Kripke/build/Kripke/tpl/raja/include -I /beegfs/hackathon/users/eoseret/qaas_runs_test/178-668-9279/intel/Kripke/build/build/kripke-build/raja/include -I /beegfs/hackathon/users/eoseret/qaas_runs_test/178-668-9279/intel/Kripke/build/Kripke/tpl/raja/tpl/camp/include -I /beegfs/hackathon/users/eoseret/qaas_runs_test/178-668-9279/intel/Kripke/build/build/kripke-build/raja/tpl/camp/include -O3 -g -fno-omit-frame-pointer -fcf-protection=none -no-pie -grecord-command-line -O3 -D NDEBUG -std=c++17 -fPIC -fiopenmp -MD -MT CMakeFiles/kripke.dir/beegfs/hackathon/users/eoseret/qaas_runs_test/178-668-9279/intel/Kripke/build/Kripke/src/Kripke/Kernel/Scattering.cpp.o -MF CMakeFiles/kripke.dir/beegfs/hackathon/users/eoseret/qaas_runs_test/178-668-9279/intel/Kripke/build/Kripke/src/Kripke/Kernel/Scattering.cpp.o.d -o CMakeFiles/kripke.dir/beegfs/hackathon/users/eoseret/qaas_runs_test/178-668-9279/intel/Kripke/build/Kripke/src/Kripke/Kernel/Scattering.cpp.o -c /beegfs/hackathon/users/eoseret/qaas_runs_test/178-668-9279/intel/Kripke/build/Kripke/src/Kripke/Kernel/Scattering.cpp -I /cluster/hpcx/2.22/ompi5-ifx-mt/include -I /cluster/hpcx/2.22/ompi5-ifx-mt/include/openmpi -fveclib=SVML 
  Number of processes observed:	1
  Number of threads observed:	191
  MAQAO version:		2026.1.0
  MAQAO build:			6d1be1d51c1e63266254997eb301734a7264775d::20260810-150026




+--------------------------------------------------------------------------------------------------------------------+
+                                               1.2  -  Global Metrics                                               +
+--------------------------------------------------------------------------------------------------------------------+

  Total Time:				38.33 s
  Max (Thread Active Time):		37.74 s
  Average Active Time:			34.79 s
  Activity Ratio:			92.3 %
  Average number of active threads:	173.330
  Affinity Stability:			99.7 %
  Time spent in analyzed loops:		39.1 %
  Time spent in analyzed innermost loops: 19.4 %
  Time spent in user code:		72.1 %
  Compilation Options Score:		66.67
  Array Access Efficiency:		94.9 %

   Potential Speedups
  ----------------------------------------------------
  Perfect Flow Complexity:		1.00
  Perfect OpenMP/MPI/Pthread/TBB:	1.06
  Perfect OpenMP/MPI/Pthread/TBB + Load Distribution:	1.48
  If No Scalar Integer:
      Potential Speedup:		1.23
      Nb Loops to get 80%:		2
  If FP Vectorized:
      Potential Speedup:		1.27
      Nb Loops to get 80%:		3
  If Fully Vectorized:
      Potential Speedup:		1.45
      Nb Loops to get 80%:		3
  If Only FP Arithmetic:
      Potential Speedup:		1.25
      Nb Loops to get 80%:		2




+--------------------------------------------------------------------------------------------------------------------+
+                                             1.3  -  Potential Speedups                                             +
+--------------------------------------------------------------------------------------------------------------------+

  If No Scalar Integer:
      Number of loops   | 1      | 1      | 3      | 4      | 6      | 
      Cumulated Speedup | 1.1695 | 1.1695 | 1.2251 | 1.2251 | 1.2251 | 
  Top 5 loops:
    exec - 1212:	1.1695
    exec - 813:	1.1979
    exec - 957:	1.2251
    exec - 1393:	1.2251
    exec - 1105:	1.2251

  If FP Vectorized:
      Number of loops   | 1      | 1      | 3      | 4      | 6      | 
      Cumulated Speedup | 1.1256 | 1.1256 | 1.2551 | 1.2636 | 1.2663 | 
  Top 5 loops:
    exec - 1212:	1.1256
    exec - 813:	1.1898
    exec - 957:	1.2551
    exec - 1393:	1.2636
    exec - 1105:	1.2663

  If Fully Vectorized:
      Number of loops   | 1      | 1      | 3      | 4      | 6      | 
      Cumulated Speedup | 1.2085 | 1.2085 | 1.4355 | 1.4467 | 1.4517 | 
  Top 5 loops:
    exec - 1212:	1.2085
    exec - 813:	1.3174
    exec - 957:	1.4355
    exec - 1393:	1.4467
    exec - 1105:	1.4514

  If Only FP Arithmetic:
      Number of loops   | 1      | 1      | 3      | 4      | 6      | 
      Cumulated Speedup | 1.1695 | 1.1695 | 1.2549 | 1.2550 | 1.2550 | 
  Top 5 loops:
    exec - 1212:	1.1695
    exec - 813:	1.2127
    exec - 957:	1.2549
    exec - 1392:	1.255
    exec - 1105:	1.255



+====================================================================================================================+
+                                                   2  -  SUMMARY                                                    +
+====================================================================================================================+


+--------------------------------------------------------------------------------------------------------------------+
+                                             2.1  -  EXPERIMENT QUALITY                                             +
+--------------------------------------------------------------------------------------------------------------------+

  [4 / 4] Application profile is long enough (37.74 s)
To have good quality measurements, it is advised that the application profiling time is greater than 10 seconds.

  [3 / 3] Most of time spent in analyzed modules comes from functions with source/debug info
-g option gives access to debugging informations, such are source locations.

  [0 / 3] Compilation of some functions is not optimized for the target processor
Architecture specific options are needed to produce efficient code for a specific processor ( -march=(target) ).

  [3 / 3] Most of time spent in analyzed modules comes from functions with compilation options informations and
-fno-omit-frame-pointer is present
-fno-omit-frame-pointer improves the accuracy of callchains found during the application profiling.

  [3 / 3] Optimization level option is correctly used


  [3 / 3] Host configuration allows retrieval of all necessary metrics.


  [2 / 2] Application is correctly profiled ("Others" category represents 0.00 % of the execution time)
To have a representative profiling, it is advised that the category "Others" represents less than 20% of the execution
time in order to analyze as much as possible of the user code

  [1 / 1] Lstopo present. The Topology lstopo report will be generated.



+--------------------------------------------------------------------------------------------------------------------+
+                                                2.2  -  CODE QUALITY                                                +
+--------------------------------------------------------------------------------------------------------------------+

  [4 / 4] Enough time of the experiment time spent in analyzed loops (39.10%)
If the time spent in analyzed loops is less than 30%, standard loop optimizations will have a limited impact on
application performances.

  [4 / 4] Threads activity is good
On average, more than 90.75% of observed threads are actually active 

  [4 / 4] CPU activity is good
CPU cores are active 92.27% of time

  [4 / 4] Loop profile is not flat
At least one loop coverage is greater than 4% (19.72%), representing an hotspot for the application

  [4 / 4] Enough time of the experiment time spent in analyzed innermost loops (19.37%)
If the time spent in analyzed innermost loops is less than 15%, standard innermost loop optimizations such as
vectorisation will have a limited impact on application performances.

  [4 / 4] Affinity is good (99.71%)
Threads are not migrating to CPU cores: probably successfully pinned

  [3 / 3] Less than 10% (0.00%) is spend in BLAS1 operations
It could be more efficient to inline by hand BLAS1 operations

  [0 / 3] Too many functions do not use all threads
Functions running on a reduced number of threads (typically sequential code) cover at least 10% of application
walltime (20.91%). Check both "Max Inclusive Time Over Threads" and "Nb Threads" in Functions or Loops tabs and
consider parallelizing sequential regions or improving parallelization of regions running on a reduced number of
threads

  [0 / 3] Cumulative Outermost/In between loops coverage (19.74%) greater than cumulative innermost loop coverage (19.37%)
Having cumulative Outermost/In between loops coverage greater than cumulative innermost loop coverage will make loop
optimization more complex

  [2 / 2] Less than 10% (0.00%) is spend in BLAS2 operations
BLAS2 calls usually could make a poor cache usage and could benefit from inlining.

  [2 / 2] Less than 10% (0.00%) is spend in Libm/SVML (special functions)



+--------------------------------------------------------------------------------------------------------------------+
+                                               2.3  -  LOOPS OVERVIEW                                               +
+--------------------------------------------------------------------------------------------------------------------+

  Top 5 loops:
   + exec - 1212:
     analysis: Execution Time: 19 % - Vectorization Ratio: 10.00 % - Vector Length Use: 13.75 %
     Loop Computation Issues: 6
        [4] [SA] Less than 10% of the FP ADD/SUB/MUL arithmetic operations are performed using FMA - Reorganize
            arithmetic expressions to exhibit potential for FMA. This issue costs 4 points.
        [2] [SA] Presence of a large number of scalar integer instructions - Simplify loop structure, perform loop
            splitting or perform unroll and jam. This issue costs 2 points.
     Control Flow Issues: 2
        [2] [SA] Non innermost loop (Outermost) - Collapse loop with innermost ones. This issue costs 2 points.
     Data Access Issues: 2
        [2] [SA] More than 20% of the loads are accessing the stack - Perform loop splitting to decrease pressure on
            registers. This issue costs 2 points.
     Vectorization Roadblocks: 1002
        [1000] [SA] Too many paths (at least 1000 paths) - Simplify control structure. There are at least 1000 issues ( =
            paths) costing 1 point.
        [2] [SA] Non innermost loop (Outermost) - Collapse loop with innermost ones. This issue costs 2 points.

   + exec - 813 :
     analysis: Execution Time: 9 % - Vectorization Ratio: 100.00 % - Vector Length Use: 25.00 %
     Loop Computation Issues: 6
        [4] [SA] Less than 10% of the FP ADD/SUB/MUL arithmetic operations are performed using FMA - Reorganize
            arithmetic expressions to exhibit potential for FMA. This issue costs 4 points.
        [2] [SA] Presence of a large number of scalar integer instructions - Simplify loop structure, perform loop
            splitting or perform unroll and jam. This issue costs 2 points.
     Data Access Issues: 0
        [0] [SA] Inefficient vectorization: more than 10% of the vector loads instructions are unaligned - When
            allocating arrays, don’t forget to align them. There are 0 issues ( = arrays) costing 2 points each

   + exec - 957 :
     analysis: Execution Time: 8 % - Vectorization Ratio: 100.00 % - Vector Length Use: 25.00 %
     Loop Computation Issues: 6
        [4] [SA] Less than 10% of the FP ADD/SUB/MUL arithmetic operations are performed using FMA - Reorganize
            arithmetic expressions to exhibit potential for FMA. This issue costs 4 points.
        [2] [SA] Presence of a large number of scalar integer instructions - Simplify loop structure, perform loop
            splitting or perform unroll and jam. This issue costs 2 points.
     Data Access Issues: 0
        [0] [SA] Inefficient vectorization: more than 10% of the vector loads instructions are unaligned - When
            allocating arrays, don’t forget to align them. There are 0 issues ( = arrays) costing 2 points each

   + exec - 1393:
     analysis: Execution Time: 1 % - Vectorization Ratio: 25.00 % - Vector Length Use: 15.63 %
     Loop Computation Issues: 16
        [12] [SA] Presence of expensive FP instructions - Perform hoisting, change algorithm, use SVML or proper
            numerical library or perform value profiling (count the number of distinct input values). There are 3
            issues (= instructions) costing 4 points each.
        [4] [SA] Less than 10% of the FP ADD/SUB/MUL arithmetic operations are performed using FMA - Reorganize
            arithmetic expressions to exhibit potential for FMA. This issue costs 4 points.
     Data Access Issues: 43
        [18] [SA] Presence of constant non unit stride data access - Use array restructuring, perform loop interchange
            or use gather instructions to lower a bit the cost. There are 9 issues ( = data accesses) costing 2 point
            each.
        [16] [SA] Presence of indirect accesses - Use array restructuring or gather instructions to lower the cost.
            There are 4 issues ( = indirect data accesses) costing 4 point each.
        [7] [SA] Presence of special instructions executing on a single port (INSERT/EXTRACT, BLEND/MERGE) - Simplify
            data access and try to get stride 1 access. There are 7 issues (= instructions) costing 1 point each.
        [2] [SA] More than 20% of the loads are accessing the stack - Perform loop splitting to decrease pressure on
            registers. This issue costs 2 points.
     Vectorization Roadblocks: 34
        [18] [SA] Presence of constant non unit stride data access - Use array restructuring, perform loop interchange
            or use gather instructions to lower a bit the cost. There are 9 issues ( = data accesses) costing 2 point
            each.
        [16] [SA] Presence of indirect accesses - Use array restructuring or gather instructions to lower the cost.
            There are 4 issues ( = indirect data accesses) costing 4 point each.
     Inefficient Vectorization: 7
        [7] [SA] Presence of special instructions executing on a single port (INSERT/EXTRACT, BLEND/MERGE) - Simplify
            data access and try to get stride 1 access. There are 7 issues (= instructions) costing 1 point each.

   + exec - 1105:
     analysis: Execution Time: 0 % - Vectorization Ratio: 100.00 % - Vector Length Use: 25.00 %
     Loop Computation Issues: 4
        [4] [SA] Less than 10% of the FP ADD/SUB/MUL arithmetic operations are performed using FMA - Reorganize
            arithmetic expressions to exhibit potential for FMA. This issue costs 4 points.
     Data Access Issues: 0
        [0] [SA] Inefficient vectorization: more than 10% of the vector loads instructions are unaligned - When
            allocating arrays, don’t forget to align them. There are 0 issues ( = arrays) costing 2 points each



+====================================================================================================================+
+                                                 3  -  APPLICATION                                                  +
+====================================================================================================================+


+--------------------------------------------------------------------------------------------------------------------+
+                                               3.1  -  Categorization                                               +
+--------------------------------------------------------------------------------------------------------------------+

   Category | IO     | Exe    | System  | Others  | Memory | String | MPI   | TBB   | OMP   | Pthread | Math  |
  ----------+--------+--------+---------+---------+--------+--------+-------+-------+-------+---------+-------+
   Time (%) | 0.00   | 72.09  | 1.13    | 0.00    | 0.12   | 0.00   | 0.00  | 0.00  | 26.66 | 0.00    | 0.00  |




+--------------------------------------------------------------------------------------------------------------------+
+                                          3.2  -  Function Based Profiling                                          +
+--------------------------------------------------------------------------------------------------------------------+

   Buckets                    | Nb Functions              | Coverage                  | Cumulated Coverage        |
  ----------------------------+---------------------------+---------------------------+---------------------------+
   > 8%                       | 4                         | 96.41                     | 96.41                     |
   4% to 8%                   | 0                         | 0.00                      | 96.41                     |
   2% to 4%                   | 0                         | 0.00                      | 96.41                     |
   1% to 2%                   | 1                         | 1.63                      | 98.04                     |
   0.5% to 1%                 | 1                         | 0.99                      | 99.03                     |
   0.25% to 0.5%              | 2                         | 0.66                      | 99.69                     |
   0.125% to 0.25%            | 1                         | 0.14                      | 99.84                     |
   < 0.125%                   | 36                        | 0.16                      | 100.00                    |




+--------------------------------------------------------------------------------------------------------------------+
+                                            3.3  -  Loop Based Profiling                                            +
+--------------------------------------------------------------------------------------------------------------------+

   Buckets                    | Nb Loops                  | Coverage                  | Cumulated Coverage        |
  ----------------------------+---------------------------+---------------------------+---------------------------+
   > 8%                       | 2                         | 17.45                     | 17.45                     |
   4% to 8%                   | 0                         | 0.00                      | 17.45                     |
   2% to 4%                   | 0                         | 0.00                      | 17.45                     |
   1% to 2%                   | 1                         | 1.61                      | 19.07                     |
   0.5% to 1%                 | 0                         | 0.00                      | 19.07                     |
   0.25% to 0.5%              | 1                         | 0.30                      | 19.36                     |
   0.125% to 0.25%            | 0                         | 0.00                      | 19.36                     |
   < 0.125%                   | 3                         | 0.00                      | 19.37                     |


+====================================================================================================================+
+                                                  4  -  FUNCTIONS                                                   +
+====================================================================================================================+


+--------------------------------------------------------------------------------------------------------------------+
+                                              4.1  -  Top 10 Functions                                              +
+--------------------------------------------------------------------------------------------------------------------+

   Function                                               | Module              | Coverage (%)   | Time (s)       |
  --------------------------------------------------------+---------------------+----------------+----------------+
   void Kripke::DispatchHelper<Kripke::ArchT_OpenMP>::... | exec                | 52.70          | 18.33          |
   kmp_flag_64<false, true>::wait(kmp_info*, int, void*)  | libiomp5.so         | 26.25          | 9.13           |
   void LPlusTimesSdom::operator()<Kripke::ArchLayoutT... | exec                | 9.12           | 3.17           |
   void Kripke::DispatchHelper<Kripke::ArchT_OpenMP>::... | exec                | 8.33           | 2.90           |
   void Kripke::DispatchHelper<Kripke::ArchT_OpenMP>::... | exec                | 1.63           | 0.57           |
   unknown_kernel_region                                  | kernel              | 0.99           | 0.35           |
   kmp_flag_native<unsigned long long, (flag_type)1, t... | libiomp5.so         | 0.36           | 0.13           |
   void PopulationSdom::operator()<Kripke::ArchLayoutT... | exec                | 0.30           | 0.10           |
   __GI___sched_yield                                     | libc.so.6           | 0.14           | 0.05           |
   __intel_avx_rep_memset                                 | exec                | 0.12           | 7.77           |


+====================================================================================================================+
+                                                    5  -  LOOPS                                                     +
+====================================================================================================================+


+--------------------------------------------------------------------------------------------------------------------+
+                                                5.1  -  Top 10 Loops                                                +
+--------------------------------------------------------------------------------------------------------------------+

   Loop Id        | Module              | Source Location                                        | Coverage (%)   |
  ----------------+---------------------+--------------------------------------------------------+----------------+
   1212           | exec                | Layout.hpp:191-191,For.hpp:142-142,Scattering.cpp:8... | 19.72          |
   813            | exec                | LPlusTimes.cpp:57-57,For.hpp:142-142                   | 9.12           |
   957            | exec                | LTimes.cpp:62-62,For.hpp:142-142                       | 8.33           |
   1393           | exec                | Iterators.hpp:449-449,Layout.hpp:191-191,SweepSubdo... | 1.61           |
   1105           | exec                | Population.cpp:58-58,For.hpp:142-142,Operators.hpp:... | 0.30           |
   1392           | exec                | Iterators.hpp:449-449,Layout.hpp:191-191,For.hpp:14... | 0.01           |
   1211           | exec                | Iterators.hpp:291-291,Layout.hpp:191-191,Collapse.h... | 0.00           |
   955            | exec                | LTimes.cpp:62-62,For.hpp:142-142                       | 0.00           |
   1311           | exec                | Source.cpp:65-71,Collapse.hpp:131-131,Collapse.hpp:... | 0.00           |
   808            | exec                | TypedViewBase.hpp:216-216,Iterators.hpp:291-291,Lay... | 0.00           |





+====================================================================================================================+
+                                                     6  -  CQA                                                      +
+====================================================================================================================+


+--------------------------------------------------------------------------------------------------------------------+
+                                                   6.1  -  Loops                                                    +
+--------------------------------------------------------------------------------------------------------------------+





      6.1.1  -  Loop 1212 from exec
  ==========================================================================================================

The loop is defined in:
 - /beegfs/hackathon/users/eoseret/qaas_runs_test/178-668-9279/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/internal/Iterators.hpp:291
 - /beegfs/hackathon/users/eoseret/qaas_runs_test/178-668-9279/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/Layout.hpp:191
 - /beegfs/hackathon/users/eoseret/qaas_runs_test/178-668-9279/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/openmp/kernel/Collapse.hpp:131,140
 - /beegfs/hackathon/users/eoseret/qaas_runs_test/178-668-9279/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/pattern/kernel/For.hpp:142
 - /beegfs/hackathon/users/eoseret/qaas_runs_test/178-668-9279/intel/Kripke/build/Kripke/src/Kripke/Kernel/Scattering.cpp:82-97


Warnings:
 - Non-innermost loop: analyzing only self part (ignoring child loops).
 - Ignoring paths for analysis
 - Failed to get the number of paths
 - RecMII not computed since number of paths is unknown or > max_paths
 - Streams not analyzed since number of paths is unknown or > max_paths


      6.1.1.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

1% of peak computational performance is used (0.35 out of 32.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.1.1.1  -  Code clean check
  ----------------------------------------------------------------------------------------------------------

Detected a slowdown caused by scalar integer instructions (typically used for address computation).
By removing them, you can lower the cost of an iteration from 5.67 to 1.50 cycles (3.78x speedup).

Workaround
 - Try to reorganize arrays of structures to structures of arrays
 - Consider to permute loops (see vectorization gain report)



      6.1.1.1.2  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is probably not vectorized.
Only 13% of vector register length is used (average across all SSE/AVX instructions).
By vectorizing your loop, you can lower the cost of an iteration from 5.67 to 0.71 cycles (8.00x speedup).

Details
Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers).
Since your execution units are vector units, only a vectorized loop can use their full power.


Workaround
 - Try another compiler or update/tune your current one:
  * recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
 - Remove inter-iterations dependences from your loop and make it unit-stride:
  * If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly:
C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)<<image_row_maj>>
  * If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA):
for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)



      6.1.1.1.3  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Performance is limited by reading data from caches/RAM (load units are a bottleneck).

By removing all these bottlenecks, you can lower the cost of an iteration from 5.67 to 5.17 cycles (1.10x speedup).


Workaround
 - Read less array elements
 - Provide more information to your compiler:
  * hardcode the bounds of the corresponding 'for' loop





      6.1.1.1.4  -  FMA
  ----------------------------------------------------------------------------------------------------------

Presence of both ADD/SUB and MUL operations.

Workaround
 - Pass to your compiler a micro-architecture specialization option:
  * use march=native
 - Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible.
For instance a + b*c is a valid FMA (MUL then ADD).
However (a+b)* c cannot be translated into an FMA (ADD then MUL).





      6.1.1.1.5  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

2 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).



      6.1.1.1.6  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 2 FP arithmetical operations:
 - 1: addition or subtraction
 - 1: multiply
The binary loop is loading 132 bytes (16 double precision FP elements).
The binary loop is storing 16 bytes (2 double precision FP elements).


      6.1.1.1.7  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.01 FP operations per loaded or stored byte.







      6.1.2  -  Loop 813 from exec
  ==========================================================================================================

The loop is defined in:
 - /beegfs/hackathon/users/eoseret/qaas_runs_test/178-668-9279/intel/Kripke/build/Kripke/src/Kripke/Kernel/LPlusTimes.cpp:57
 - /beegfs/hackathon/users/eoseret/qaas_runs_test/178-668-9279/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/pattern/kernel/For.hpp:142


It is main loop of related source loop which is unrolled by 2 (including vectorization).

      6.1.2.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

8% of peak computational performance is used (2.67 out of 32.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.2.1.1  -  Code clean check
  ----------------------------------------------------------------------------------------------------------

Detected a slowdown caused by scalar integer instructions (typically used for address computation).
By removing them, you can lower the cost of an iteration from 1.50 to 1.17 cycles (1.29x speedup).

Workaround
 - Try to reorganize arrays of structures to structures of arrays
 - Consider to permute loops (see vectorization gain report)



      6.1.2.1.2  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is vectorized, but using only 128 out of 512 bits (SSE/AVX-128 instructions on AVX-512 processors).
<<image_2x64_512>>By fully vectorizing your loop, you can lower the cost of an iteration from 1.50 to 0.37 cycles (4.00x speedup).

Details
All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).
Since your execution units are vector units, only a fully vectorized loop can use their full power.


Workaround
 - Pass to your compiler a micro-architecture specialization option:
  * use march=native
 - Use vector aligned instructions:
  1) align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
  2) inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.



      6.1.2.1.3  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Found no such bottlenecks but see expert reports for more complex bottlenecks.




      6.1.2.1.4  -  FMA
  ----------------------------------------------------------------------------------------------------------

Presence of both ADD/SUB and MUL operations.

Workaround
 - Pass to your compiler a micro-architecture specialization option:
  * use march=native
 - Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible.
For instance a + b*c is a valid FMA (MUL then ADD).
However (a+b)* c cannot be translated into an FMA (ADD then MUL).





      6.1.2.1.5  -  Vector unaligned load/store instructions
  ----------------------------------------------------------------------------------------------------------

Detected 3 suboptimal vector unaligned load/store instructions.


Details
 - MOVUPD: 3 occurrences<<list_path_1_vec_align_1>>


Workaround
 - Pass to your compiler a micro-architecture specialization option:
  * use march=native
 - Use vector aligned instructions:
  1) align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
  2) inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.
<<image_vec_align>>


      6.1.2.1.6  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

2 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).



      6.1.2.1.7  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 4 FP arithmetical operations:
 - 2: addition or subtraction
 - 2: multiply
The binary loop is loading 32 bytes (4 double precision FP elements).
The binary loop is storing 16 bytes (2 double precision FP elements).


      6.1.2.1.8  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.







      6.1.3  -  Loop 957 from exec
  ==========================================================================================================

The loop is defined in:
 - /beegfs/hackathon/users/eoseret/qaas_runs_test/178-668-9279/intel/Kripke/build/Kripke/src/Kripke/Kernel/LTimes.cpp:62
 - /beegfs/hackathon/users/eoseret/qaas_runs_test/178-668-9279/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/pattern/kernel/For.hpp:142


It is main loop of related source loop which is unrolled by 2 (including vectorization).

      6.1.3.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

8% of peak computational performance is used (2.67 out of 32.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.3.1.1  -  Code clean check
  ----------------------------------------------------------------------------------------------------------

Detected a slowdown caused by scalar integer instructions (typically used for address computation).
By removing them, you can lower the cost of an iteration from 1.50 to 1.17 cycles (1.29x speedup).

Workaround
 - Try to reorganize arrays of structures to structures of arrays
 - Consider to permute loops (see vectorization gain report)



      6.1.3.1.2  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is vectorized, but using only 128 out of 512 bits (SSE/AVX-128 instructions on AVX-512 processors).
<<image_2x64_512>>By fully vectorizing your loop, you can lower the cost of an iteration from 1.50 to 0.37 cycles (4.00x speedup).

Details
All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).
Since your execution units are vector units, only a fully vectorized loop can use their full power.


Workaround
 - Pass to your compiler a micro-architecture specialization option:
  * use march=native
 - Use vector aligned instructions:
  1) align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
  2) inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.



      6.1.3.1.3  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Found no such bottlenecks but see expert reports for more complex bottlenecks.




      6.1.3.1.4  -  FMA
  ----------------------------------------------------------------------------------------------------------

Presence of both ADD/SUB and MUL operations.

Workaround
 - Pass to your compiler a micro-architecture specialization option:
  * use march=native
 - Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible.
For instance a + b*c is a valid FMA (MUL then ADD).
However (a+b)* c cannot be translated into an FMA (ADD then MUL).





      6.1.3.1.5  -  Vector unaligned load/store instructions
  ----------------------------------------------------------------------------------------------------------

Detected 3 suboptimal vector unaligned load/store instructions.


Details
 - MOVUPD: 3 occurrences<<list_path_1_vec_align_1>>


Workaround
 - Pass to your compiler a micro-architecture specialization option:
  * use march=native
 - Use vector aligned instructions:
  1) align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
  2) inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.
<<image_vec_align>>


      6.1.3.1.6  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

2 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).



      6.1.3.1.7  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 4 FP arithmetical operations:
 - 2: addition or subtraction
 - 2: multiply
The binary loop is loading 32 bytes (4 double precision FP elements).
The binary loop is storing 16 bytes (2 double precision FP elements).


      6.1.3.1.8  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.







      6.1.4  -  Loop 1393 from exec
  ==========================================================================================================

The loop is defined in:
 - /beegfs/hackathon/users/eoseret/qaas_runs_test/178-668-9279/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/internal/Iterators.hpp:449
 - /beegfs/hackathon/users/eoseret/qaas_runs_test/178-668-9279/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/Layout.hpp:191
 - /beegfs/hackathon/users/eoseret/qaas_runs_test/178-668-9279/intel/Kripke/build/Kripke/src/Kripke/Kernel/SweepSubdomain.cpp:88-89,96-106
 - /beegfs/hackathon/users/eoseret/qaas_runs_test/178-668-9279/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/pattern/kernel/For.hpp:142
 - /beegfs/hackathon/users/eoseret/qaas_runs_test/178-668-9279/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/Operators.hpp:369


The related source loop is not unrolled or unrolled with no peel/tail loop.

      6.1.4.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

5% of peak computational performance is used (1.67 out of 32.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.4.1.1  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is poorly vectorized.
Only 15% of vector register length is used (average across all SSE/AVX instructions).
By fully vectorizing your loop, you can lower the cost of an iteration from 12.00 to 8.00 cycles (1.50x speedup).

Details
25% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):
 - 0% of SSE/AVX loads are used in vector version.
 - 0% of SSE/AVX stores are used in vector version.
 - 27% of SSE/AVX addition or subtraction instructions are used in vector version.
 - 50% of SSE/AVX multiply instructions are used in vector version.
 - 33% of SSE/AVX divide and square root instructions are used in vector version.
 - 50% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.
Since your execution units are vector units, only a fully vectorized loop can use their full power.


Workaround
 - Try another compiler or update/tune your current one:
  * recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
 - Remove inter-iterations dependences from your loop and make it unit-stride:
  * If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly:
C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)<<image_row_maj>>
  * If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA):
for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)



      6.1.4.1.2  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Performance is limited by reading data from caches/RAM (load units are a bottleneck).


Workaround
 - Read less array elements
 - Provide more information to your compiler:
  * hardcode the bounds of the corresponding 'for' loop





      6.1.4.1.3  -  FMA
  ----------------------------------------------------------------------------------------------------------

Presence of both ADD/SUB and MUL operations.

Workaround
 - Pass to your compiler a micro-architecture specialization option:
  * use march=native
 - Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible.
For instance a + b*c is a valid FMA (MUL then ADD).
However (a+b)* c cannot be translated into an FMA (ADD then MUL).





      6.1.4.1.4  -  Slow data structures access
  ----------------------------------------------------------------------------------------------------------

Detected data structures (typically arrays) that cannot be efficiently read/written

Details
 - Constant unknown stride: 9 occurrence(s)
 - Irregular (variable stride) or indirect: 4 occurrence(s)
Non-unit stride (uncontiguous) accesses are not efficiently using data caches


Workaround
 - Try to reorganize arrays of structures to structures of arrays
 - Consider to permute loops (see vectorization gain report)
 - Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.



      6.1.4.1.5  -  Vector unaligned load/store instructions
  ----------------------------------------------------------------------------------------------------------

Detected 3 suboptimal vector unaligned load/store instructions.


Details
 - MOVHPD: 3 occurrences<<list_path_1_vec_align_1>>


Workaround
 - Pass to your compiler a micro-architecture specialization option:
  * use march=native
 - Use vector aligned instructions:
  1) align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
  2) inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.
<<image_vec_align>>


      6.1.4.1.6  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

10 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).
5 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).



      6.1.4.1.7  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 20 FP arithmetical operations:
 - 13: addition or subtraction
 - 3: multiply
 - 4: divide
The binary loop is loading 288 bytes (36 double precision FP elements).
The binary loop is storing 32 bytes (4 double precision FP elements).


      6.1.4.1.8  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.06 FP operations per loaded or stored byte.


      6.1.4.1.9  -  Unroll opportunity
  ----------------------------------------------------------------------------------------------------------

Loop is data access bound.

Workaround
Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: #pragma unroll_and_jam N, unroll_and_jam(N), unroll N or unroll(N)







      6.1.5  -  Loop 1105 from exec
  ==========================================================================================================

The loop is defined in:
 - /beegfs/hackathon/users/eoseret/qaas_runs_test/178-668-9279/intel/Kripke/build/Kripke/src/Kripke/Kernel/Population.cpp:58
 - /beegfs/hackathon/users/eoseret/qaas_runs_test/178-668-9279/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/pattern/kernel/For.hpp:142
 - /beegfs/hackathon/users/eoseret/qaas_runs_test/178-668-9279/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/Operators.hpp:369


It is main loop of related source loop which is unrolled by 2 (including vectorization).

      6.1.5.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

6% of peak computational performance is used (2.00 out of 32.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.5.1.1  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is vectorized, but using only 128 out of 512 bits (SSE/AVX-128 instructions on AVX-512 processors).
<<image_2x64_512>>By fully vectorizing your loop, you can lower the cost of an iteration from 3.00 to 0.75 cycles (4.00x speedup).

Details
All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).
Since your execution units are vector units, only a fully vectorized loop can use their full power.


Workaround
 - Pass to your compiler a micro-architecture specialization option:
  * use march=native
 - Use vector aligned instructions:
  1) align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
  2) inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.



      6.1.5.1.2  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Found no such bottlenecks but see expert reports for more complex bottlenecks.




      6.1.5.1.3  -  FMA
  ----------------------------------------------------------------------------------------------------------

Presence of both ADD/SUB and MUL operations.

Workaround
 - Pass to your compiler a micro-architecture specialization option:
  * use march=native
 - Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible.
For instance a + b*c is a valid FMA (MUL then ADD).
However (a+b)* c cannot be translated into an FMA (ADD then MUL).





      6.1.5.1.4  -  Vector unaligned load/store instructions
  ----------------------------------------------------------------------------------------------------------

Detected 2 suboptimal vector unaligned load/store instructions.


Details
 - MOVUPD: 2 occurrences<<list_path_1_vec_align_1>>


Workaround
 - Pass to your compiler a micro-architecture specialization option:
  * use march=native
 - Use vector aligned instructions:
  1) align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
  2) inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.
<<image_vec_align>>


      6.1.5.1.5  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

3 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).



      6.1.5.1.6  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 6 FP arithmetical operations:
 - 2: addition or subtraction
 - 4: multiply
The binary loop is loading 32 bytes (4 double precision FP elements).


      6.1.5.1.7  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.19 FP operations per loaded or stored byte.







      6.1.6  -  Loop 1392 from exec
  ==========================================================================================================

The loop is defined in:
 - /beegfs/hackathon/users/eoseret/qaas_runs_test/178-668-9279/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/internal/Iterators.hpp:449
 - /beegfs/hackathon/users/eoseret/qaas_runs_test/178-668-9279/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/Layout.hpp:191
 - /beegfs/hackathon/users/eoseret/qaas_runs_test/178-668-9279/intel/Kripke/build/Kripke/src/Kripke/Kernel/SweepSubdomain.cpp:88-89,96-106
 - /beegfs/hackathon/users/eoseret/qaas_runs_test/178-668-9279/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/pattern/kernel/For.hpp:142
 - /beegfs/hackathon/users/eoseret/qaas_runs_test/178-668-9279/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/Operators.hpp:369


Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).
The structure of this loop is probably <if then [else] end>.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):
 - hoisting them (moving them outside the loop)
 - turning them into conditional moves, MIN or MAX


Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)


      6.1.6.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

0% of peak computational performance is used (0.00 out of 64.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.6.1.1  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is not vectorized.
Only 12% of vector register length is used (average across all SSE/AVX instructions).
By vectorizing your loop, you can lower the cost of an iteration from 5.33 to 0.45 cycles (11.91x speedup).

Details
All SSE/AVX instructions are used in scalar version (process only one data element in vector registers).
Since your execution units are vector units, only a vectorized loop can use their full power.


Workaround
 - Try another compiler or update/tune your current one:
  * recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
 - Remove inter-iterations dependences from your loop and make it unit-stride:
  * If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly:
C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)<<image_row_maj>>
  * If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA):
for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)



      6.1.6.1.2  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Performance is limited by reading data from caches/RAM (load units are a bottleneck).


Workaround
 - Read less array elements
 - Provide more information to your compiler:
  * hardcode the bounds of the corresponding 'for' loop




No data for this section



      6.1.6.1.3  -  Slow data structures access
  ----------------------------------------------------------------------------------------------------------

Detected data structures (typically arrays) that cannot be efficiently read/written

Details
 - Constant unknown stride: 5 occurrence(s)
 - Irregular (variable stride) or indirect: 8 occurrence(s)
Non-unit stride (uncontiguous) accesses are not efficiently using data caches


Workaround
 - Try to reorganize arrays of structures to structures of arrays
 - Consider to permute loops (see vectorization gain report)
 - Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.



      6.1.6.1.4  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.


      6.1.6.1.5  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop does not contain any FP arithmetical operations.
The binary loop is loading 128 bytes.
The binary loop is storing 40 bytes.




      6.1.6.2  -  Path 2
  ----------------------------------------------------------------------------------------------------------

0% of peak computational performance is used (0.00 out of 64.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.6.2.1  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is not vectorized.
8 data elements could be processed at once in vector registers.
By vectorizing your loop, you can lower the cost of an iteration from 2.00 to 0.25 cycles (8.00x speedup).

Details
All SSE/AVX instructions are used in scalar version (process only one data element in vector registers).
Since your execution units are vector units, only a vectorized loop can use their full power.


Workaround
 - Try another compiler or update/tune your current one:
  * recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
 - Remove inter-iterations dependences from your loop and make it unit-stride:
  * If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly:
C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)<<image_row_maj>>
  * If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA):
for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)



      6.1.6.2.2  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Found no such bottlenecks but see expert reports for more complex bottlenecks.



No data for this section



      6.1.6.2.3  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.


      6.1.6.2.4  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop does not contain any FP arithmetical operations.
The binary loop is loading 48 bytes.
The binary loop is storing 8 bytes.





[MAQAO] Info: STOP THE REPORT GENERATION
[MAQAO] Info: 
[MAQAO] Info: If your application produces files, they can be found in directory "/beegfs/hackathon/users/eoseret/qaas_runs_test/178-668-9279/intel/Kripke/run/oneview_runs/defaults/orig/oneview_run_1786689771"
[MAQAO] Info: 
