OV - exec - Loop 811

	Loop Id: 811	Module: exec	Source: forall.hpp:59-59 [...]	Coverage: 1.43%

0x46aab0 LEA	(%RSI,%R8,1),%R10

0x46aab4 ADD	%RDX,%R10

0x46aab7 MOV	0x30(%RSP),%R12    [4]

0x46aabc VMOVUPD	(%R12,%R8,8),%YMM2    [1]

0x46aac2 VFMADD213PD	(%R15,%R8,8),%YMM26,%YMM2    [3]

0x46aac9 MOV	0x10(%RSP),%R12    [4]

0x46aace ADD	%R10,%R12

0x46aad1 VFMADD231PD	(%R14,%R12,8),%YMM27,%YMM2    [2]

0x46aad8 LEA	(%R10,%RAX,1),%R12

0x46aadc VFMADD231PD	(%R14,%R12,8),%YMM28,%YMM2    [2]

0x46aae3 LEA	(%R10,%R11,1),%R12

0x46aae7 VFMADD231PD	(%R14,%R12,8),%YMM29,%YMM2    [2]

0x46aaee LEA	(%R10,%R13,1),%R12

0x46aaf2 VFMADD231PD	(%R14,%R12,8),%YMM30,%YMM2    [2]

0x46aaf9 LEA	(%R10,%RDI,1),%R12

0x46aafd VFMADD231PD	(%R14,%R12,8),%YMM31,%YMM2    [2]

0x46ab04 LEA	(%R10,%RCX,1),%R12

0x46ab08 VFMADD231PD	(%R14,%R12,8),%YMM1,%YMM2    [2]

0x46ab0e ADD	%R9,%R10

0x46ab11 VFMADD231PD	(%R14,%R10,8),%YMM0,%YMM2    [2]

0x46ab17 VMOVUPD	%YMM2,(%R15,%R8,8)    [3]

0x46ab1d ADD	$0x4,%R8

0x46ab21 CMP	%RBX,%R8

0x46ab24 JLE	46aab0

/home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/loop/forall.hpp: 59 - 59

--------------------------------------------------------------------------------

59:   for (decltype(distance_it) i = 0; i < distance_it; ++i) {

/home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/src/Kripke/Kernel/LPlusTimes.cpp: 57 - 57

--------------------------------------------------------------------------------

57:             rhs(d,g,z) += ell_plus(d, nm) * phi_out(nm, g, z);

Coverage (%)	Name	Source Location	Module
►100.00+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Path /

Metric	Value
CQA speedup if no scalar integer	1.29
CQA speedup if FP arith vectorized	1.55
CQA speedup if fully vectorized	2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.29
Bottlenecks	micro-operation queue,
Function	void LPlusTimesSdom::operator() >(Kripke::ArchLayoutT, Kripke::SdomId, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&) const [clone .extracted]
Source	forall.hpp:59-59,LPlusTimes.cpp:57-57
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	high
Unroll/vectorization loop type	main
Unroll factor	4
CQA cycles	5.17
CQA cycles if no scalar integer	4.00
CQA cycles if FP arith vectorized	3.33
CQA cycles if fully vectorized	2.58
Front-end cycles	5.17
P0 cycles	4.00
P1 cycles	4.00
P2 cycles	3.67
P3 cycles	3.67
P4 cycles	0.50
P5 cycles	1.40
P6 cycles	1.40
P7 cycles	0.50
P8 cycles	0.50
P9 cycles	0.50
P10 cycles	1.20
P11 cycles	3.67
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	24.00
Nb uops	23.00
Nb loads	11.00
Nb stores	1.00
Nb stack references	2.00
FLOP/cycle	12.39
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	32.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	65.03
Bytes prefetched	0.00
Bytes loaded	304.00
Bytes stored	32.00
Stride 0	1.00
Stride 1	2.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	1.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	50.00
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	50.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.29
CQA speedup if FP arith vectorized	1.55
CQA speedup if fully vectorized	2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.29
Bottlenecks	micro-operation queue,
Function	void LPlusTimesSdom::operator() >(Kripke::ArchLayoutT, Kripke::SdomId, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&) const [clone .extracted]
Source	forall.hpp:59-59,LPlusTimes.cpp:57-57
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	high
Unroll/vectorization loop type	main
Unroll factor	4
CQA cycles	5.17
CQA cycles if no scalar integer	4.00
CQA cycles if FP arith vectorized	3.33
CQA cycles if fully vectorized	2.58
Front-end cycles	5.17
P0 cycles	4.00
P1 cycles	4.00
P2 cycles	3.67
P3 cycles	3.67
P4 cycles	0.50
P5 cycles	1.40
P6 cycles	1.40
P7 cycles	0.50
P8 cycles	0.50
P9 cycles	0.50
P10 cycles	1.20
P11 cycles	3.67
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	24.00
Nb uops	23.00
Nb loads	11.00
Nb stores	1.00
Nb stack references	2.00
FLOP/cycle	12.39
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	32.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	65.03
Bytes prefetched	0.00
Bytes loaded	304.00
Bytes stored	32.00
Stride 0	1.00
Stride 1	2.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	1.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	50.00
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	50.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	void LPlusTimesSdom::operator() >(Kripke::ArchLayoutT, Kripke::SdomId, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&) const [clone .extracted]
Source file and lines	forall.hpp:59-59
Module	exec

The loop is defined in:

/home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/loop/forall.hpp:59
/home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/src/Kripke/Kernel/LPlusTimes.cpp:57

It is main loop of related source loop which is unrolled by 4 (including vectorization).

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 5.17 to 4.00 cycles (1.29x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is vectorized, but using only 256 out of 512 bits (AVX/AVX2 instructions on AVX-512 processors).

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

FMA

Detected 32 FMA (fused multiply-add) operations.

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Irregular (variable stride) or indirect: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Vector unaligned load/store instructions

Detected 2 optimal vector unaligned load/store instructions.

Details

VMOVUPD: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/src/Kripke/Kernel/LPlusTimes.cpp:57
- /home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/src/Kripke/Kernel/LPlusTimes.cpp:57

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

8 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 64 FP arithmetical operations:

32: addition or subtraction (all inside FMA instructions)
32: multiply (all inside FMA instructions)

The binary loop is loading 304 bytes (38 double precision FP elements). The binary loop is storing 32 bytes (4 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.19 FP operations per loaded or stored byte.

General properties

nb instructions	24
nb uops	23
loop length	118
used x86 registers	15
used mmx registers	0
used xmm registers	0
used ymm registers	9
used zmm registers	0
nb stack references	2

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	5.17 cycles
front end	5.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	4.00	4.00	3.67	3.67	0.50	1.40	1.40	0.50	0.50	0.50	1.20	3.67
cycles	4.00	4.00	3.67	3.67	0.50	1.40	1.40	0.50	0.50	0.50	1.20	3.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	5.17
Dispatch	4.00
Data deps.	1.00
Overall L1	5.17

Vectorization ratios

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	50%
load	50%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	50%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 5.17 cycles. At this rate:

30% of peak load performance is reached (58.84 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (6.19 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 5.17 to 4.00 cycles (1.29x speedup).

ASM code

In the binary file, the address of the loop is: 46aab0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
LEA (%RSI,%R8,1),%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD %RDX,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0x30(%RSP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVUPD (%R12,%R8,8),%YMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VFMADD213PD (%R15,%R8,8),%YMM26,%YMM2	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
MOV 0x10(%RSP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %R10,%R12	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VFMADD231PD (%R14,%R12,8),%YMM27,%YMM2	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
LEA (%R10,%RAX,1),%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VFMADD231PD (%R14,%R12,8),%YMM28,%YMM2	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
LEA (%R10,%R11,1),%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VFMADD231PD (%R14,%R12,8),%YMM29,%YMM2	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
LEA (%R10,%R13,1),%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VFMADD231PD (%R14,%R12,8),%YMM30,%YMM2	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
LEA (%R10,%RDI,1),%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VFMADD231PD (%R14,%R12,8),%YMM31,%YMM2	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
LEA (%R10,%RCX,1),%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VFMADD231PD (%R14,%R12,8),%YMM1,%YMM2	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
ADD %R9,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VFMADD231PD (%R14,%R10,8),%YMM0,%YMM2	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VMOVUPD %YMM2,(%R15,%R8,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
ADD $0x4,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RBX,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JLE 46aab0 <_ZNK14LPlusTimesSdomclIN6Kripke11ArchLayoutTINS1_12ArchT_OpenMPENS1_11LayoutT_DGZEEEEEvT_NS1_6SdomIdERKNS1_4Core3SetESB_SB_SB_RNS8_5FieldIdJNS1_6MomentENS1_5GroupENS1_4ZoneEEEERNSC_IdJNS1_9DirectionESE_SF_EEERNSC_IdJSI_SD_EEE.extracted+0x850>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Function	void LPlusTimesSdom::operator() >(Kripke::ArchLayoutT, Kripke::SdomId, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&) const [clone .extracted]
Source file and lines	forall.hpp:59-59
Module	exec

The loop is defined in:

/home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/loop/forall.hpp:59
/home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/src/Kripke/Kernel/LPlusTimes.cpp:57

It is main loop of related source loop which is unrolled by 4 (including vectorization).

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 5.17 to 4.00 cycles (1.29x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is vectorized, but using only 256 out of 512 bits (AVX/AVX2 instructions on AVX-512 processors).

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

Workaround

Recompile with -mprefer-vector-width=512

FMA

Detected 32 FMA (fused multiply-add) operations.

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Irregular (variable stride) or indirect: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Vector unaligned load/store instructions

Detected 2 optimal vector unaligned load/store instructions.

Details

VMOVUPD: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/src/Kripke/Kernel/LPlusTimes.cpp:57
- /home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/src/Kripke/Kernel/LPlusTimes.cpp:57

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

8 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 64 FP arithmetical operations:

32: addition or subtraction (all inside FMA instructions)
32: multiply (all inside FMA instructions)

The binary loop is loading 304 bytes (38 double precision FP elements). The binary loop is storing 32 bytes (4 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.19 FP operations per loaded or stored byte.

General properties

nb instructions	24
nb uops	23
loop length	118
used x86 registers	15
used mmx registers	0
used xmm registers	0
used ymm registers	9
used zmm registers	0
nb stack references	2

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	5.17 cycles
front end	5.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	4.00	4.00	3.67	3.67	0.50	1.40	1.40	0.50	0.50	0.50	1.20	3.67
cycles	4.00	4.00	3.67	3.67	0.50	1.40	1.40	0.50	0.50	0.50	1.20	3.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	5.17
Dispatch	4.00
Data deps.	1.00
Overall L1	5.17

Vectorization ratios

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	50%
load	50%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	50%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 5.17 cycles. At this rate:

30% of peak load performance is reached (58.84 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (6.19 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 46aab0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
LEA (%RSI,%R8,1),%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD %RDX,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0x30(%RSP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVUPD (%R12,%R8,8),%YMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VFMADD213PD (%R15,%R8,8),%YMM26,%YMM2	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
MOV 0x10(%RSP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %R10,%R12	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VFMADD231PD (%R14,%R12,8),%YMM27,%YMM2	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
LEA (%R10,%RAX,1),%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VFMADD231PD (%R14,%R12,8),%YMM28,%YMM2	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
LEA (%R10,%R11,1),%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VFMADD231PD (%R14,%R12,8),%YMM29,%YMM2	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
LEA (%R10,%R13,1),%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VFMADD231PD (%R14,%R12,8),%YMM30,%YMM2	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
LEA (%R10,%RDI,1),%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VFMADD231PD (%R14,%R12,8),%YMM31,%YMM2	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
LEA (%R10,%RCX,1),%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VFMADD231PD (%R14,%R12,8),%YMM1,%YMM2	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
ADD %R9,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VFMADD231PD (%R14,%R10,8),%YMM0,%YMM2	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VMOVUPD %YMM2,(%R15,%R8,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
ADD $0x4,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RBX,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JLE 46aab0 <_ZNK14LPlusTimesSdomclIN6Kripke11ArchLayoutTINS1_12ArchT_OpenMPENS1_11LayoutT_DGZEEEEEvT_NS1_6SdomIdERKNS1_4Core3SetESB_SB_SB_RNS8_5FieldIdJNS1_6MomentENS1_5GroupENS1_4ZoneEEEERNSC_IdJNS1_9DirectionESE_SF_EEERNSC_IdJSI_SD_EEE.extracted+0x850>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

FMA

Slow data structures access

Details

Workaround

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

FMA

Slow data structures access

Details

Workaround

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code