OV - exec - Loop 1428

	Loop Id: 1428	Module: exec	Source: forall.hpp:59-59 [...]	Coverage: 0.03%

0x4ab7c0 MOV	-0xb8(%RBP),%R15

0x4ab7c7 ADD	-0x2e8(%RBP),%R15

0x4ab7ce MOV	-0x2e0(%RBP),%RAX

0x4ab7d5 MOV	-0x3a8(%RBP),%R14

0x4ab7dc ADD	%RAX,%R14

0x4ab7df MOV	-0x3a0(%RBP),%R12

0x4ab7e6 ADD	%RAX,%R12

0x4ab7e9 MOV	-0x3b0(%RBP),%RBX

0x4ab7f0 ADD	%RAX,%RBX

0x4ab7f3 MOV	-0x340(%RBP),%RAX

0x4ab7fa MOV	-0x398(%RBP),%R13

0x4ab801 CMP	%RAX,%R13

0x4ab804 LEA	0x1(%R13),%R13

0x4ab808 MOV	-0xb0(%RBP),%R9

0x4ab80f MOV	-0x40(%RBP),%R11

0x4ab813 JE	4ab4c0

0x4ab819 MOV	%R15,-0xb8(%RBP)

0x4ab820 MOV	%R9,-0x478(%RBP)

0x4ab827 MOV	%R9,-0x470(%RBP)

0x4ab82e MOV	-0x308(%RBP),%RAX

0x4ab835 MOV	%RAX,-0x468(%RBP)

0x4ab83c MOV	-0x300(%RBP),%RAX

0x4ab843 MOV	%RAX,-0x460(%RBP)

0x4ab84a MOV	%R11,-0x458(%RBP)

0x4ab851 MOV	%R11,-0x450(%RBP)

0x4ab858 MOV	-0x2f8(%RBP),%RAX

0x4ab85f MOV	%RAX,-0x448(%RBP)

0x4ab866 MOV	-0x2f0(%RBP),%RAX

0x4ab86d MOV	%RAX,-0x440(%RBP)

0x4ab874 MOV	-0xa8(%RBP),%RAX

0x4ab87b MOV	%RAX,-0x438(%RBP)

0x4ab882 MOV	%RAX,-0x430(%RBP)

0x4ab889 MOV	-0x198(%RBP),%RCX

0x4ab890 IMUL	%R13,%RCX

0x4ab894 MOV	-0x90(%RBP),%RAX

0x4ab89b ADD	%RCX,%RAX

0x4ab89e MOV	-0x348(%RBP),%RDX

0x4ab8a5 LEA	(%RDX,%RAX,8),%RAX

0x4ab8a9 MOV	%RAX,-0x1b0(%RBP)

0x4ab8b0 MOV	%RAX,-0x428(%RBP)

0x4ab8b7 MOV	%RAX,-0x420(%RBP)

0x4ab8be MOV	%RCX,%RSI

0x4ab8c1 IMUL	-0x180(%RBP),%RSI

0x4ab8c9 MOV	-0x370(%RBP),%RAX

0x4ab8d0 ADD	%RSI,%RAX

0x4ab8d3 MOV	-0xa0(%RBP),%RDX

0x4ab8da LEA	(%RDX,%RAX,8),%RAX

0x4ab8de MOV	%RAX,-0x418(%RBP)

0x4ab8e5 MOV	-0x368(%RBP),%RAX

0x4ab8ec MOV	%RSI,-0x1a8(%RBP)

0x4ab8f3 ADD	%RSI,%RAX

0x4ab8f6 LEA	(%RDX,%RAX,8),%RAX

0x4ab8fa MOV	%RAX,-0x410(%RBP)

0x4ab901 MOV	%RCX,%RAX

0x4ab904 IMUL	-0x190(%RBP),%RAX

0x4ab90c MOV	-0x320(%RBP),%RDX

0x4ab913 ADD	%RAX,%RDX

0x4ab916 ADD	-0x318(%RBP),%RDX

0x4ab91d ADD	-0x338(%RBP),%RDX

0x4ab924 MOV	-0x390(%RBP),%R8

0x4ab92b LEA	(%RDX,%R8,1),%RSI

0x4ab92f MOV	-0x188(%RBP),%RDI

0x4ab936 LEA	(%RDI,%RSI,8),%RSI

0x4ab93a MOV	%RSI,-0x408(%RBP)

0x4ab941 ADD	-0x328(%RBP),%RAX

0x4ab948 ADD	-0x310(%RBP),%RAX

0x4ab94f ADD	-0x330(%RBP),%RAX

0x4ab956 LEA	(%RAX,%R8,1),%RSI

0x4ab95a LEA	(%RDI,%RSI,8),%RSI

0x4ab95e MOV	%RSI,-0x400(%RBP)

0x4ab965 IMUL	-0x178(%RBP),%RCX

0x4ab96d MOV	-0x360(%RBP),%RSI

0x4ab974 ADD	%RCX,%RSI

0x4ab977 MOV	-0x170(%RBP),%RDI

0x4ab97e LEA	(%RDI,%RSI,8),%RSI

0x4ab982 MOV	%RSI,-0x3f8(%RBP)

0x4ab989 ADD	-0x388(%RBP),%RCX

0x4ab990 LEA	(%RDI,%RCX,8),%RCX

0x4ab994 MOV	%RCX,-0x3f0(%RBP)

0x4ab99b MOV	-0x358(%RBP),%RCX

0x4ab9a2 MOV	%RCX,-0x3e8(%RBP)

0x4ab9a9 MOV	-0x350(%RBP),%RCX

0x4ab9b0 MOV	%RCX,-0x3e0(%RBP)

0x4ab9b7 MOV	-0x380(%RBP),%RDI

0x4ab9be LEA	(%RDX,%RDI,1),%RCX

0x4ab9c2 MOV	-0x168(%RBP),%RSI

0x4ab9c9 LEA	(%RSI,%RCX,8),%RCX

0x4ab9cd MOV	%RCX,-0x3d8(%RBP)

0x4ab9d4 LEA	(%RAX,%RDI,1),%RCX

0x4ab9d8 LEA	(%RSI,%RCX,8),%RCX

0x4ab9dc MOV	%RCX,-0x3d0(%RBP)

0x4ab9e3 MOV	-0x378(%RBP),%RDI

0x4ab9ea ADD	%RDI,%RDX

0x4ab9ed MOV	-0x160(%RBP),%RSI

0x4ab9f4 LEA	(%RSI,%RDX,8),%RCX

0x4ab9f8 MOV	%RCX,-0x3c8(%RBP)

0x4ab9ff ADD	%RDI,%RAX

0x4aba02 LEA	(%RSI,%RAX,8),%RAX

0x4aba06 MOV	%RAX,-0x3c0(%RBP)

0x4aba0d MOV	$0xc,%ESI

0x4aba12 LEA	-0x478(%RBP),%RDI

0x4aba19 CALL	50d710 <__intel_rtdd_indep>

0x4aba1e TEST	%RAX,%RAX

0x4aba21 MOV	%RBX,-0x3b0(%RBP)

0x4aba28 MOV	%R14,-0x3a8(%RBP)

0x4aba2f MOV	%R12,-0x3a0(%RBP)

0x4aba36 MOV	%R13,-0x398(%RBP)

0x4aba3d JE	4abc00

0x4aba43 MOV	-0x2d8(%RBP),%RSI

0x4aba4a MOVQ	$0,-0x38(%RBP)

0x4aba52 JMP	4abab7

  (1431) 0x4aba80 ADD	-0xc8(%RBP),%RSI

  (1431) 0x4aba87 MOV	-0xc0(%RBP),%RDI

  (1431) 0x4aba8e ADD	%RDI,%RAX

  (1431) 0x4aba91 ADD	%RDI,%R12

  (1431) 0x4aba94 MOV	-0x60(%RBP),%RBX

  (1431) 0x4aba98 ADD	%RDI,%RBX

  (1431) 0x4aba9b MOV	%RAX,%R14

  (1431) 0x4aba9e MOV	-0x38(%RBP),%RAX

  (1431) 0x4abaa2 CMP	-0xd0(%RBP),%RAX

  (1431) 0x4abaa9 LEA	0x1(%RAX),%RAX

  (1431) 0x4abaad MOV	%RAX,-0x38(%RBP)

  (1431) 0x4abab1 JE	4ab7c0

  (1431) 0x4abab7 MOV	%RBX,-0x60(%RBP)

  (1431) 0x4ababb CMPQ	$0,-0x30(%RBP)

  (1431) 0x4abac0 MOV	-0xa0(%RBP),%RBX

  (1431) 0x4abac7 MOV	-0xb0(%RBP),%RDX

  (1431) 0x4abace MOV	%R14,%RAX

  (1431) 0x4abad1 MOV	-0xa8(%RBP),%R15

  (1431) 0x4abad8 MOV	-0xb8(%RBP),%R13

  (1431) 0x4abadf MOV	-0x1b0(%RBP),%RDI

  (1431) 0x4abae6 JLE	4aba80

  (1431) 0x4abae8 MOV	-0x98(%RBP),%R8

  (1431) 0x4abaef IMUL	-0x38(%RBP),%R8

  (1431) 0x4abaf4 MOV	-0x48(%RBP),%R9

  (1431) 0x4abaf8 ADD	%R8,%R9

  (1431) 0x4abafb ADD	-0x1a8(%RBP),%R8

  (1431) 0x4abb02 ADD	-0x1a0(%RBP),%R8

  (1431) 0x4abb09 XOR	%R10D,%R10D

  (1431) 0x4abb0c XOR	%R11D,%R11D

  (1431) 0x4abb0f MOV	-0x30(%RBP),%R14

  (1431) 0x4abb13 NOPW	%CS:(%RAX,%RAX,1)

    (1432) 0x4abb20 VMOVSD	(%RDX),%XMM0

    (1432) 0x4abb24 VADDSD	%XMM0,%XMM0,%XMM0

    (1432) 0x4abb28 MOV	-0x70(%RBP),%RCX

    (1432) 0x4abb2c VDIVSD	(%RCX,%R11,1),%XMM0,%XMM0

    (1432) 0x4abb32 MOV	-0x40(%RBP),%RCX

    (1432) 0x4abb36 VMOVSD	(%RCX),%XMM1

    (1432) 0x4abb3a VMOVHPD	(%R15),%XMM1,%XMM1

    (1432) 0x4abb3f VADDPD	%XMM1,%XMM1,%XMM1

    (1432) 0x4abb43 MOV	-0xd8(%RBP),%RCX

    (1432) 0x4abb4a VMOVSD	(%RCX,%R9,8),%XMM2

    (1432) 0x4abb50 VMOVHPD	(%RDI),%XMM2,%XMM2

    (1432) 0x4abb54 VDIVPD	%XMM2,%XMM1,%XMM1

    (1432) 0x4abb58 VMOVSD	(%RBX,%R8,8),%XMM2

    (1432) 0x4abb5e MOV	%RAX,%RCX

    (1432) 0x4abb61 MOV	%R12,%RAX

    (1432) 0x4abb64 MOV	-0x60(%RBP),%R12

    (1432) 0x4abb68 VFMADD213SD	(%R12,%R10,1),%XMM0,%XMM2

    (1432) 0x4abb6e MOV	%RAX,%R12

    (1432) 0x4abb71 MOV	%RCX,%RAX

    (1432) 0x4abb74 VFMADD231SD	(%R13,%R11,1),%XMM1,%XMM2

    (1432) 0x4abb7b VSHUFPD	$0x1,%XMM1,%XMM1,%XMM3

    (1432) 0x4abb80 VFMADD231SD	(%RSI,%R11,1),%XMM3,%XMM2

    (1432) 0x4abb86 VADDSD	%XMM0,%XMM1,%XMM0

    (1432) 0x4abb8a VADDSD	(%R12,%R10,1),%XMM3,%XMM1

    (1432) 0x4abb90 VADDSD	%XMM0,%XMM1,%XMM0

    (1432) 0x4abb94 VDIVSD	%XMM0,%XMM2,%XMM0

    (1432) 0x4abb98 VMOVSD	%XMM0,(%RCX,%R10,1)

    (1432) 0x4abb9e VADDSD	%XMM0,%XMM0,%XMM0

    (1432) 0x4abba2 VSUBSD	(%RBX,%R8,8),%XMM0,%XMM1

    (1432) 0x4abba8 VMOVSD	%XMM1,(%RBX,%R8,8)

    (1432) 0x4abbae VSUBSD	(%R13,%R11,1),%XMM0,%XMM1

    (1432) 0x4abbb5 VMOVSD	%XMM1,(%R13,%R11,1)

    (1432) 0x4abbbc VSUBSD	(%RSI,%R11,1),%XMM0,%XMM0

    (1432) 0x4abbc2 VMOVSD	%XMM0,(%RSI,%R11,1)

    (1432) 0x4abbc8 ADD	-0x58(%RBP),%R11

    (1432) 0x4abbcc ADD	-0x50(%RBP),%R10

    (1432) 0x4abbd0 DEC	%R14

    (1432) 0x4abbd3 JNE	4abb20

  (1431) 0x4abbd9 JMP	4aba80

0x4abc00 MOV	%RBX,%RAX

0x4abc03 MOV	%R12,%RCX

0x4abc06 MOV	%R14,%RDX

0x4abc09 MOV	-0x2d0(%RBP),%RSI

0x4abc10 XOR	%EDI,%EDI

0x4abc12 JMP	4abc68

  (1429) 0x4abc40 ADD	-0xc8(%RBP),%RSI

  (1429) 0x4abc47 MOV	-0xc0(%RBP),%R8

  (1429) 0x4abc4e ADD	%R8,%RDX

  (1429) 0x4abc51 ADD	%R8,%RCX

  (1429) 0x4abc54 ADD	%R8,%RAX

  (1429) 0x4abc57 CMP	-0xd0(%RBP),%RDI

  (1429) 0x4abc5e LEA	0x1(%RDI),%RDI

  (1429) 0x4abc62 JE	4ab7c0

  (1429) 0x4abc68 CMPQ	$0,-0x30(%RBP)

  (1429) 0x4abc6d JLE	4abc40

  (1429) 0x4abc6f MOV	-0xb0(%RBP),%R8

  (1429) 0x4abc76 VMOVSD	(%R8),%XMM1

  (1429) 0x4abc7b MOV	-0x98(%RBP),%R8

  (1429) 0x4abc82 IMUL	%RDI,%R8

  (1429) 0x4abc86 MOV	-0x48(%RBP),%R9

  (1429) 0x4abc8a ADD	%R8,%R9

  (1429) 0x4abc8d ADD	-0x1a8(%RBP),%R8

  (1429) 0x4abc94 ADD	-0x1a0(%RBP),%R8

  (1429) 0x4abc9b MOV	-0xa0(%RBP),%RBX

  (1429) 0x4abca2 VMOVSD	(%RBX,%R8,8),%XMM0

  (1429) 0x4abca8 MOV	-0x40(%RBP),%R10

  (1429) 0x4abcac VMOVSD	(%R10),%XMM2

  (1429) 0x4abcb1 MOV	-0xa8(%RBP),%R10

  (1429) 0x4abcb8 VMOVHPD	(%R10),%XMM2,%XMM2

  (1429) 0x4abcbd MOV	-0xd8(%RBP),%R10

  (1429) 0x4abcc4 VMOVSD	(%R10,%R9,8),%XMM3

  (1429) 0x4abcca MOV	-0x1b0(%RBP),%R9

  (1429) 0x4abcd1 VMOVHPD	(%R9),%XMM3,%XMM3

  (1429) 0x4abcd6 VADDSD	%XMM1,%XMM1,%XMM1

  (1429) 0x4abcda VADDPD	%XMM2,%XMM2,%XMM2

  (1429) 0x4abcde VDIVPD	%XMM3,%XMM2,%XMM2

  (1429) 0x4abce2 VSHUFPD	$0x1,%XMM2,%XMM2,%XMM3

  (1429) 0x4abce7 VADDSD	%XMM3,%XMM2,%XMM4

  (1429) 0x4abceb XOR	%R9D,%R9D

  (1429) 0x4abcee XOR	%R10D,%R10D

  (1429) 0x4abcf1 MOV	-0x30(%RBP),%R11

  (1429) 0x4abcf5 MOV	-0x58(%RBP),%R14

  (1429) 0x4abcf9 MOV	-0x50(%RBP),%R12

  (1429) 0x4abcfd MOV	-0x70(%RBP),%R13

  (1429) 0x4abd01 MOV	-0xb8(%RBP),%R15

  (1429) 0x4abd08 NOPL	(%RAX,%RAX,1)

    (1430) 0x4abd10 VDIVSD	(%R13,%R10,1),%XMM1,%XMM5

    (1430) 0x4abd17 VMOVSD	(%RAX,%R9,1),%XMM6

    (1430) 0x4abd1d VMOVSD	(%R15,%R10,1),%XMM7

    (1430) 0x4abd23 VFMADD231SD	%XMM5,%XMM0,%XMM6

    (1430) 0x4abd28 VMOVSD	(%RSI,%R10,1),%XMM8

    (1430) 0x4abd2e VADDSD	%XMM5,%XMM4,%XMM5

    (1430) 0x4abd32 VADDSD	(%RCX,%R9,1),%XMM5,%XMM5

    (1430) 0x4abd38 VFMADD231SD	%XMM2,%XMM7,%XMM6

    (1430) 0x4abd3d VFMADD231SD	%XMM3,%XMM8,%XMM6

    (1430) 0x4abd42 VDIVSD	%XMM5,%XMM6,%XMM5

    (1430) 0x4abd46 VADDSD	%XMM5,%XMM5,%XMM6

    (1430) 0x4abd4a VSUBSD	%XMM7,%XMM6,%XMM7

    (1430) 0x4abd4e VMOVSD	%XMM5,(%RDX,%R9,1)

    (1430) 0x4abd54 VMOVSD	%XMM7,(%R15,%R10,1)

    (1430) 0x4abd5a VSUBSD	%XMM0,%XMM6,%XMM0

    (1430) 0x4abd5e VSUBSD	%XMM8,%XMM6,%XMM5

    (1430) 0x4abd63 VMOVSD	%XMM5,(%RSI,%R10,1)

    (1430) 0x4abd69 ADD	%R14,%R10

    (1430) 0x4abd6c ADD	%R12,%R9

    (1430) 0x4abd6f DEC	%R11

    (1430) 0x4abd72 JNE	4abd10

  (1429) 0x4abd74 VMOVSD	%XMM0,(%RBX,%R8,8)

  (1429) 0x4abd7a JMP	4abc40

/home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/loop/forall.hpp: 59 - 59

--------------------------------------------------------------------------------

59:   for (decltype(distance_it) i = 0; i < distance_it; ++i) {

/home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/View.hpp: 110 - 110

--------------------------------------------------------------------------------

110:     return data[idx];

/home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/src/Kripke/Kernel/SweepSubdomain.cpp: 87 - 105

--------------------------------------------------------------------------------

87:             double xcos_dxi = 2.0 * xcos(d) / dx(i);

88:             double ycos_dyj = 2.0 * ycos(d) / dy(j);

89:             double zcos_dzk = 2.0 * zcos(d) / dz(k);

[...]

95:                 + psi_lf(d, g, j, k) * xcos_dxi

96:                 + psi_fr(d, g, i, k) * ycos_dyj

97:                 + psi_bo(d, g, i, j) * zcos_dzk)

98:                 / (xcos_dxi + ycos_dyj + zcos_dzk + sigt(g, z));

99:

100:             psi(d, g, z) = psi_d_g_z;

101:

102:             /* Apply diamond-difference relationships */

103:             psi_lf(d, g, j, k) = 2.0 * psi_d_g_z - psi_lf(d, g, j, k);

104:             psi_fr(d, g, i, k) = 2.0 * psi_d_g_z - psi_fr(d, g, i, k);

105:             psi_bo(d, g, i, j) = 2.0 * psi_d_g_z - psi_bo(d, g, i, j);

Coverage (%)	Name	Source Location	Module
►100.00+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	8.61
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.16
Bottlenecks
Function	void Kripke::DispatchHelper::operator()(Kripke::LayoutT_DGZ, SweepSdom const&, Kripke::Core::DataStore&, Kripke::SdomId&) const [clone .extracted]
Source	forall.hpp:59-59,View.hpp:110-110,SweepSubdomain.cpp:89-89,SweepSubdomain.cpp:95-95,SweepSubdomain.cpp:103-103
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	18.92
CQA cycles if no scalar integer	18.92
CQA cycles if FP arith vectorized	18.92
CQA cycles if fully vectorized	2.20
Front-end cycles	18.92
P0 cycles	5.20
P1 cycles	8.00
P2 cycles	14.00
P3 cycles	14.00
P4 cycles	16.25
P5 cycles	5.20
P6 cycles	5.20
P7 cycles	16.25
P8 cycles	16.25
P9 cycles	16.25
P10 cycles	5.20
P11 cycles	14.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	112.50
Nb uops	113.50
Nb loads	42.00
Nb stores	31.50
Nb stack references	68.50
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	31.09
Bytes prefetched	0.00
Bytes loaded	336.00
Bytes stored	252.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	6.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.43
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.40
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.20
Bottlenecks	micro-operation queue,
Function	void Kripke::DispatchHelper::operator()(Kripke::LayoutT_DGZ, SweepSdom const&, Kripke::Core::DataStore&, Kripke::SdomId&) const [clone .extracted]
Source	forall.hpp:59-59,View.hpp:110-110,SweepSubdomain.cpp:89-89,SweepSubdomain.cpp:95-95,SweepSubdomain.cpp:103-103
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	19.17
CQA cycles if no scalar integer	19.17
CQA cycles if FP arith vectorized	19.17
CQA cycles if fully vectorized	2.40
Front-end cycles	19.17
P0 cycles	5.20
P1 cycles	8.00
P2 cycles	14.00
P3 cycles	14.00
P4 cycles	16.00
P5 cycles	5.20
P6 cycles	5.20
P7 cycles	16.00
P8 cycles	16.00
P9 cycles	16.00
P10 cycles	5.20
P11 cycles	14.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	114.00
Nb uops	115.00
Nb loads	42.00
Nb stores	31.00
Nb stack references	68.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	30.47
Bytes prefetched	0.00
Bytes loaded	336.00
Bytes stored	248.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	6.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	9.33
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.13
Bottlenecks	micro-operation queue,
Function	void Kripke::DispatchHelper::operator()(Kripke::LayoutT_DGZ, SweepSdom const&, Kripke::Core::DataStore&, Kripke::SdomId&) const [clone .extracted]
Source	forall.hpp:59-59,View.hpp:110-110,SweepSubdomain.cpp:89-89,SweepSubdomain.cpp:95-95,SweepSubdomain.cpp:103-103
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	18.67
CQA cycles if no scalar integer	18.67
CQA cycles if FP arith vectorized	18.67
CQA cycles if fully vectorized	2.00
Front-end cycles	18.67
P0 cycles	5.20
P1 cycles	8.00
P2 cycles	14.00
P3 cycles	14.00
P4 cycles	16.50
P5 cycles	5.20
P6 cycles	5.20
P7 cycles	16.50
P8 cycles	16.50
P9 cycles	16.50
P10 cycles	5.20
P11 cycles	14.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	111.00
Nb uops	112.00
Nb loads	42.00
Nb stores	32.00
Nb stack references	69.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	31.71
Bytes prefetched	0.00
Bytes loaded	336.00
Bytes stored	256.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.35
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.30
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	void Kripke::DispatchHelper::operator()(Kripke::LayoutT_DGZ, SweepSdom const&, Kripke::Core::DataStore&, Kripke::SdomId&) const [clone .extracted]
Source file and lines	forall.hpp:59-59
Module	exec

The loop is defined in:

/home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/loop/forall.hpp:59
/home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/View.hpp:110
/home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/src/Kripke/Kernel/SweepSubdomain.cpp:87-89,95-105

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).
This loop has 4 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 12% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 18.92 to 2.20 cycles (8.61x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

__intel_rtdd_indep: 0 occurrences

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 6 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 336 bytes. The binary loop is storing 252 bytes.

General properties

nb instructions	112.50
nb uops	113.50
loop length	661.50
used x86 registers	14
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	68.50

Front-end

MACRO FUSION NOT POSSIBLE

micro-operation queue	18.92 cycles
front end	18.92 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	5.20	5.20	14.00	14.00	16.25	5.20	5.20	16.25	16.25	16.25	5.20	14.00
cycles	5.20	8.00	14.00	14.00	16.25	5.20	5.20	16.25	16.25	16.25	5.20	14.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	18.92
Dispatch	16.25
Data deps.	0.00
Overall L1	18.92

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 18.92 cycles. At this rate:

9% of peak load performance is reached (17.77 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
10% of peak store performance is reached (13.33 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Function	void Kripke::DispatchHelper::operator()(Kripke::LayoutT_DGZ, SweepSdom const&, Kripke::Core::DataStore&, Kripke::SdomId&) const [clone .extracted]
Source file and lines	forall.hpp:59-59
Module	exec

The loop is defined in:

/home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/loop/forall.hpp:59
/home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/View.hpp:110
/home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/src/Kripke/Kernel/SweepSubdomain.cpp:87-89,95-105

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 19.17 to 2.40 cycles (8.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

__intel_rtdd_indep: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/loop/forall.hpp:59

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 6 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 336 bytes. The binary loop is storing 248 bytes.

General properties

nb instructions	114
nb uops	115
loop length	663
used x86 registers	14
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	68

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	19.17 cycles
front end	19.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	5.20	5.20	14.00	14.00	16.00	5.20	5.20	16.00	16.00	16.00	5.20	14.00
cycles	5.20	8.00	14.00	14.00	16.00	5.20	5.20	16.00	16.00	16.00	5.20	14.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	19.17
Dispatch	16.00
Data deps.	0.00
Overall L1	19.17

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 19.17 cycles. At this rate:

9% of peak load performance is reached (17.53 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
10% of peak store performance is reached (12.94 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 19.17 to 16.00 cycles (1.20x speedup).

ASM code

In the binary file, the address of the loop is: 4ab819

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
MOV -0xb8(%RBP),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD -0x2e8(%RBP),%R15	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
MOV -0x2e0(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x3a8(%RBP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD %RAX,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV -0x3a0(%RBP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD %RAX,%R12	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV -0x3b0(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD %RAX,%RBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV -0x340(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x398(%RBP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %RAX,%R13	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
LEA 0x1(%R13),%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0xb0(%RBP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x40(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
JE 4ab4c0 <_ZNK6Kripke14DispatchHelperINS_12ArchT_OpenMPEEclINS_11LayoutT_DGZE9SweepSdomJRNS_4Core9DataStoreERNS_6SdomIdEEEEvT_RKT0_DpOT1_.extracted+0x830>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R15,-0xb8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R9,-0x478(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R9,-0x470(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0x308(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x468(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0x300(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x460(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R11,-0x458(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R11,-0x450(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0x2f8(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x448(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0x2f0(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x440(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0xa8(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x438(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RAX,-0x430(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0x198(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
IMUL %R13,%RCX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV -0x90(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %RCX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0x348(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%RDX,%RAX,8),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,-0x1b0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RAX,-0x428(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RAX,-0x420(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RCX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL -0x180(%RBP),%RSI	1	0	1	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1	N/A
MOV -0x370(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %RSI,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0xa0(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%RDX,%RAX,8),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,-0x418(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0x368(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RSI,-0x1a8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %RSI,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA (%RDX,%RAX,8),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,-0x410(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL -0x190(%RBP),%RAX	1	0	1	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1	N/A
MOV -0x320(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %RAX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD -0x318(%RBP),%RDX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
ADD -0x338(%RBP),%RDX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
MOV -0x390(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%RDX,%R8,1),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0x188(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%RDI,%RSI,8),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RSI,-0x408(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD -0x328(%RBP),%RAX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
ADD -0x310(%RBP),%RAX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
ADD -0x330(%RBP),%RAX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
LEA (%RAX,%R8,1),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%RDI,%RSI,8),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RSI,-0x400(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
IMUL -0x178(%RBP),%RCX	1	0	1	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1	N/A
MOV -0x360(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %RCX,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0x170(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%RDI,%RSI,8),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RSI,-0x3f8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD -0x388(%RBP),%RCX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
LEA (%RDI,%RCX,8),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RCX,-0x3f0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0x358(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RCX,-0x3e8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0x350(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RCX,-0x3e0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0x380(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%RDX,%RDI,1),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0x168(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%RSI,%RCX,8),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RCX,-0x3d8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (%RAX,%RDI,1),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%RSI,%RCX,8),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RCX,-0x3d0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0x378(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %RDI,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0x160(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%RSI,%RDX,8),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RCX,-0x3c8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %RDI,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA (%RSI,%RAX,8),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,-0x3c0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV $0xc,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA -0x478(%RBP),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 50d710 <__intel_rtdd_indep>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
TEST %RAX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
MOV %RBX,-0x3b0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R14,-0x3a8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R12,-0x3a0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R13,-0x398(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JE 4abc00 <_ZNK6Kripke14DispatchHelperINS_12ArchT_OpenMPEEclINS_11LayoutT_DGZE9SweepSdomJRNS_4Core9DataStoreERNS_6SdomIdEEEEvT_RKT0_DpOT1_.extracted+0xf70>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RBX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R12,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R14,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x2d0(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 4abc68 <_ZNK6Kripke14DispatchHelperINS_12ArchT_OpenMPEEclINS_11LayoutT_DGZE9SweepSdomJRNS_4Core9DataStoreERNS_6SdomIdEEEEvT_RKT0_DpOT1_.extracted+0xfd8>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A

Function	void Kripke::DispatchHelper::operator()(Kripke::LayoutT_DGZ, SweepSdom const&, Kripke::Core::DataStore&, Kripke::SdomId&) const [clone .extracted]
Source file and lines	forall.hpp:59-59
Module	exec

The loop is defined in:

/home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/loop/forall.hpp:59
/home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/View.hpp:110
/home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/src/Kripke/Kernel/SweepSubdomain.cpp:87-89,95-105

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

__intel_rtdd_indep: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/loop/forall.hpp:59

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 336 bytes. The binary loop is storing 256 bytes.

General properties

nb instructions	111
nb uops	112
loop length	660
used x86 registers	14
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	69

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	18.67 cycles
front end	18.67 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	5.20	5.20	14.00	14.00	16.50	5.20	5.20	16.50	16.50	16.50	5.20	14.00
cycles	5.20	8.00	14.00	14.00	16.50	5.20	5.20	16.50	16.50	16.50	5.20	14.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	18.67
Dispatch	16.50
Data deps.	0.00
Overall L1	18.67

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 18.67 cycles. At this rate:

9% of peak load performance is reached (18.00 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
10% of peak store performance is reached (13.71 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 4ab819

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
MOV -0xb8(%RBP),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD -0x2e8(%RBP),%R15	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
MOV -0x2e0(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x3a8(%RBP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD %RAX,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV -0x3a0(%RBP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD %RAX,%R12	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV -0x3b0(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD %RAX,%RBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV -0x340(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x398(%RBP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %RAX,%R13	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
LEA 0x1(%R13),%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0xb0(%RBP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x40(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
JE 4ab4c0 <_ZNK6Kripke14DispatchHelperINS_12ArchT_OpenMPEEclINS_11LayoutT_DGZE9SweepSdomJRNS_4Core9DataStoreERNS_6SdomIdEEEEvT_RKT0_DpOT1_.extracted+0x830>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R15,-0xb8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R9,-0x478(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R9,-0x470(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0x308(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x468(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0x300(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x460(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R11,-0x458(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R11,-0x450(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0x2f8(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x448(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0x2f0(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x440(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0xa8(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x438(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RAX,-0x430(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0x198(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
IMUL %R13,%RCX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV -0x90(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %RCX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0x348(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%RDX,%RAX,8),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,-0x1b0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RAX,-0x428(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RAX,-0x420(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RCX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL -0x180(%RBP),%RSI	1	0	1	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1	N/A
MOV -0x370(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %RSI,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0xa0(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%RDX,%RAX,8),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,-0x418(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0x368(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RSI,-0x1a8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %RSI,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA (%RDX,%RAX,8),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,-0x410(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL -0x190(%RBP),%RAX	1	0	1	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1	N/A
MOV -0x320(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %RAX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD -0x318(%RBP),%RDX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
ADD -0x338(%RBP),%RDX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
MOV -0x390(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%RDX,%R8,1),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0x188(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%RDI,%RSI,8),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RSI,-0x408(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD -0x328(%RBP),%RAX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
ADD -0x310(%RBP),%RAX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
ADD -0x330(%RBP),%RAX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
LEA (%RAX,%R8,1),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%RDI,%RSI,8),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RSI,-0x400(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
IMUL -0x178(%RBP),%RCX	1	0	1	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1	N/A
MOV -0x360(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %RCX,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0x170(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%RDI,%RSI,8),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RSI,-0x3f8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD -0x388(%RBP),%RCX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
LEA (%RDI,%RCX,8),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RCX,-0x3f0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0x358(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RCX,-0x3e8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0x350(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RCX,-0x3e0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0x380(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%RDX,%RDI,1),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0x168(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%RSI,%RCX,8),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RCX,-0x3d8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (%RAX,%RDI,1),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%RSI,%RCX,8),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RCX,-0x3d0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0x378(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %RDI,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0x160(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%RSI,%RDX,8),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RCX,-0x3c8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %RDI,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA (%RSI,%RAX,8),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,-0x3c0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV $0xc,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA -0x478(%RBP),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 50d710 <__intel_rtdd_indep>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
TEST %RAX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
MOV %RBX,-0x3b0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R14,-0x3a8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R12,-0x3a0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R13,-0x398(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JE 4abc00 <_ZNK6Kripke14DispatchHelperINS_12ArchT_OpenMPEEclINS_11LayoutT_DGZE9SweepSdomJRNS_4Core9DataStoreERNS_6SdomIdEEEEvT_RKT0_DpOT1_.extracted+0xf70>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x2d8(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOVQ $0,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
JMP 4abab7 <_ZNK6Kripke14DispatchHelperINS_12ArchT_OpenMPEEclINS_11LayoutT_DGZE9SweepSdomJRNS_4Core9DataStoreERNS_6SdomIdEEEEvT_RKT0_DpOT1_.extracted+0xe27>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A

Report Configuration

Vectorization

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Workaround

CALL instructions

Details

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code