OV - exec - Loop 1273

	Loop Id: 1273	Module: exec	Source: forall.hpp:59-59 [...]	Coverage: 0.29%

0x498b80 MOV	-0x48(%RBP),%RAX

0x498b84 CMP	-0x40(%RBP),%RAX

0x498b88 LEA	0x1(%RAX),%RAX

0x498b8c MOV	%RAX,-0x48(%RBP)

0x498b90 JE	498a40

0x498b96 CMPQ	$0,-0x38(%RBP)

0x498b9b JLE	498b80

0x498b9d MOV	-0xf0(%RBP),%RAX

0x498ba4 MOV	-0x108(%RBP),%RCX

0x498bab MOV	(%RAX,%RCX,8),%R11

0x498baf IMUL	-0xe8(%RBP),%R11

0x498bb7 ADD	-0x30(%RBP),%R11

0x498bbb MOV	-0xf8(%RBP),%RAX

0x498bc2 MOV	-0x48(%RBP),%RCX

0x498bc6 ADD	%RCX,%RAX

0x498bc9 ADD	%R11,%RAX

0x498bcc VPBROADCASTQ	%RAX,%YMM1

0x498bd2 MOV	-0x70(%RBP),%RAX

0x498bd6 IMUL	%RCX,%RAX

0x498bda MOV	%RAX,-0x50(%RBP)

0x498bde ADD	-0x100(%RBP),%R11

0x498be5 ADD	-0x78(%RBP),%R11

0x498be9 ADD	%RCX,%R11

0x498bec XOR	%EDX,%EDX

0x498bee JMP	498c4b

  (1274) 0x498c00 VXORPD	%XMM2,%XMM2,%XMM2

  (1274) 0x498c04 MOV	-0x50(%RBP),%RAX

  (1274) 0x498c08 ADD	%RDX,%RAX

  (1274) 0x498c0b ADD	-0x140(%RBP),%RAX

  (1274) 0x498c12 MOV	-0x128(%RBP),%RCX

  (1274) 0x498c19 VMOVSD	(%RCX,%RAX,8),%XMM3

  (1274) 0x498c1e MOV	-0x138(%RBP),%RAX

  (1274) 0x498c25 ADD	%RDX,%RAX

  (1274) 0x498c28 MOV	-0x130(%RBP),%RCX

  (1274) 0x498c2f VFMADD213SD	(%RCX,%RAX,8),%XMM2,%XMM3

  (1274) 0x498c35 VMOVSD	%XMM3,(%RCX,%RAX,8)

  (1274) 0x498c3a CMP	-0x120(%RBP),%RDX

  (1274) 0x498c41 LEA	0x1(%RDX),%RDX

  (1274) 0x498c45 JE	498b80

  (1274) 0x498c4b LEA	(%R13,%RDX,1),%RCX

  (1274) 0x498c50 MOVSXD	(%RDI,%RCX,4),%RAX

  (1274) 0x498c54 TEST	%RAX,%RAX

  (1274) 0x498c57 JLE	498c00

  (1274) 0x498c59 MOV	-0x118(%RBP),%RSI

  (1274) 0x498c60 MOV	(%RSI,%RCX,8),%R10

  (1274) 0x498c64 ADD	%R10,%RAX

  (1274) 0x498c67 LEA	0x1(%R10),%RCX

  (1274) 0x498c6b CMP	%RCX,%RAX

  (1274) 0x498c6e CMOVLE	%RCX,%RAX

  (1274) 0x498c72 MOV	%RAX,%R8

  (1274) 0x498c75 SUB	%R10,%R8

  (1274) 0x498c78 MOV	%R8,%R9

  (1274) 0x498c7b AND	$-0x4,%R9

  (1274) 0x498c7f JE	498d00

  (1274) 0x498c85 LEA	-0x1(%R9),%RDI

  (1274) 0x498c89 LEA	(%R12,%R10,8),%RCX

  (1274) 0x498c8d LEA	(%R14,%R10,8),%R13

  (1274) 0x498c91 VXORPD	%XMM2,%XMM2,%XMM2

  (1274) 0x498c95 XOR	%ESI,%ESI

  (1274) 0x498c97 NOPW	(%RAX,%RAX,1)

    (1276) 0x498ca0 VXORPS	%XMM3,%XMM3,%XMM3

    (1276) 0x498ca4 VPMULLQ	(%R13,%RSI,8),%YMM0,%YMM3

    (1276) 0x498cac VPADDQ	%YMM3,%YMM1,%YMM3

    (1276) 0x498cb0 KXNORW	%K0,%K0,%K1

    (1276) 0x498cb4 VXORPD	%XMM4,%XMM4,%XMM4

    (1276) 0x498cb8 VGATHERQPD	(%R15,%YMM3,8),%YMM4{%K1}

    (1276) 0x498cbf VFMADD231PD	(%RCX,%RSI,8),%YMM4,%YMM2

    (1276) 0x498cc5 ADD	$0x4,%RSI

    (1276) 0x498cc9 CMP	%RDI,%RSI

    (1276) 0x498ccc JBE	498ca0

  (1274) 0x498cce VEXTRACTF128	$0x1,%YMM2,%XMM3

  (1274) 0x498cd4 VADDPD	%XMM3,%XMM2,%XMM2

  (1274) 0x498cd8 VSHUFPD	$0x1,%XMM2,%XMM2,%XMM3

  (1274) 0x498cdd VADDSD	%XMM3,%XMM2,%XMM2

  (1274) 0x498ce1 CMP	%R9,%R8

  (1274) 0x498ce4 MOV	-0x110(%RBP),%R13

  (1274) 0x498ceb MOV	-0x80(%RBP),%RDI

  (1274) 0x498cef JE	498c04

  (1274) 0x498cf5 JMP	498d07

  (1274) 0x498d00 VXORPD	%XMM2,%XMM2,%XMM2

  (1274) 0x498d04 XOR	%R9D,%R9D

  (1274) 0x498d07 ADD	%R10,%R9

  (1274) 0x498d0a NOPW	(%RAX,%RAX,1)

    (1275) 0x498d10 MOV	(%R14,%R9,8),%RCX

    (1275) 0x498d14 IMUL	%RBX,%RCX

    (1275) 0x498d18 ADD	%R11,%RCX

    (1275) 0x498d1b VMOVSD	(%R15,%RCX,8),%XMM3

    (1275) 0x498d21 VFMADD231SD	(%R12,%R9,8),%XMM3,%XMM2

    (1275) 0x498d27 INC	%R9

    (1275) 0x498d2a CMP	%R9,%RAX

    (1275) 0x498d2d JNE	498d10

  (1274) 0x498d2f JMP	498c04

/home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/src/Kripke/Kernel/Scattering.cpp: 87 - 97

--------------------------------------------------------------------------------

87:             MixElem mix_start = zone_to_mixelem(z);

88:             MixElem mix_stop = mix_start + zone_to_num_mixelem(z);

89:

90:             double sigs_z = 0.0;

91:             for(MixElem mix = mix_start;mix < mix_stop;++ mix){

92:               Material mat = mixelem_to_material(mix);

93:               double fraction = mixelem_to_fraction(mix);

94:

95:               sigs_z += sigs(mat, n, global_g, global_gp) * fraction;

96:             }

97:             phi_out(nm, g, z) += sigs_z * phi(nm, gp, z);

/home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/index/IndexValue.hpp: 105 - 217

--------------------------------------------------------------------------------

105:     return TYPE(value + a);

[...]

217:     return (value < x.value);

/home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/loop/forall.hpp: 59 - 59

--------------------------------------------------------------------------------

59:   for (decltype(distance_it) i = 0; i < distance_it; ++i) {

/home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/Layout.hpp: 55 - 55

--------------------------------------------------------------------------------

55:     return a * b;

Coverage (%)	Name	Source Location	Module
►99.88+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Path /

Metric	Value
CQA speedup if no scalar integer	1.86
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	13.87
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.04
Bottlenecks	P2, P3, P11,
Function	void Kripke::DispatchHelper::operator()&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&>(Kripke::LayoutT_DGZ, ScatteringSdom const&, Kripke::SdomId&, Kripke::SdomId&, Kripke::Core::Set&, Kripke::Core::Set&, Kripke::Core::Set&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&) const [clone .extracted]
Source	Scattering.cpp:95-97,forall.hpp:59-59,Layout.hpp:55-55
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	4.33
CQA cycles if no scalar integer	2.33
CQA cycles if FP arith vectorized	4.33
CQA cycles if fully vectorized	0.31
Front-end cycles	4.17
P0 cycles	2.60
P1 cycles	3.60
P2 cycles	4.33
P3 cycles	4.33
P4 cycles	1.00
P5 cycles	2.60
P6 cycles	2.60
P7 cycles	1.00
P8 cycles	1.00
P9 cycles	1.00
P10 cycles	2.60
P11 cycles	4.33
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	25.00
Nb uops	25.00
Nb loads	13.00
Nb stores	2.00
Nb stack references	12.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	27.69
Bytes prefetched	0.00
Bytes loaded	104.00
Bytes stored	16.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	11.46
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	10.94

Metric	Value
CQA speedup if no scalar integer	1.86
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	13.87
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.04
Bottlenecks	P2, P3, P11,
Function	void Kripke::DispatchHelper::operator()&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&>(Kripke::LayoutT_DGZ, ScatteringSdom const&, Kripke::SdomId&, Kripke::SdomId&, Kripke::Core::Set&, Kripke::Core::Set&, Kripke::Core::Set&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&) const [clone .extracted]
Source	Scattering.cpp:95-97,forall.hpp:59-59,Layout.hpp:55-55
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	4.33
CQA cycles if no scalar integer	2.33
CQA cycles if FP arith vectorized	4.33
CQA cycles if fully vectorized	0.31
Front-end cycles	4.17
P0 cycles	2.60
P1 cycles	3.60
P2 cycles	4.33
P3 cycles	4.33
P4 cycles	1.00
P5 cycles	2.60
P6 cycles	2.60
P7 cycles	1.00
P8 cycles	1.00
P9 cycles	1.00
P10 cycles	2.60
P11 cycles	4.33
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	25.00
Nb uops	25.00
Nb loads	13.00
Nb stores	2.00
Nb stack references	12.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	27.69
Bytes prefetched	0.00
Bytes loaded	104.00
Bytes stored	16.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	11.46
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	10.94

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	void Kripke::DispatchHelper::operator()&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&>(Kripke::LayoutT_DGZ, ScatteringSdom const&, Kripke::SdomId&, Kripke::SdomId&, Kripke::Core::Set&, Kripke::Core::Set&, Kripke::Core::Set&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&) const [clone .extracted]
Source file and lines	forall.hpp:59-59
Module	exec

The loop is defined in:

/home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/src/Kripke/Kernel/Scattering.cpp:87-97
/home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/index/IndexValue.hpp:105,217
/home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/loop/forall.hpp:59
/home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/Layout.hpp:55

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=5
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 5 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 4.33 to 2.33 cycles (1.86x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 11% of vector register length is used (average across all SSE/AVX instructions).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Performance is limited by reading data from caches/RAM (load units are a bottleneck).

Workaround

Read less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 104 bytes. The binary loop is storing 16 bytes.

General properties

nb instructions	25
nb uops	25
loop length	112
used x86 registers	5
used mmx registers	0
used xmm registers	0
used ymm registers	1
used zmm registers	0
nb stack references	12

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	4.17 cycles
front end	4.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	2.60	2.60	4.33	4.33	1.00	2.60	2.60	1.00	1.00	1.00	2.60	4.33
cycles	2.60	3.60	4.33	4.33	1.00	2.60	2.60	1.00	1.00	1.00	2.60	4.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	4.17
Dispatch	4.33
Overall L1	4.33

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	11%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 4.33 cycles. At this rate:

12% of peak load performance is reached (24.00 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (3.69 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 498b96

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
MOV -0x48(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP -0x40(%RBP),%RAX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
LEA 0x1(%RAX),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,-0x48(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JE 498a40 <_ZNK6Kripke14DispatchHelperINS_12ArchT_OpenMPEEclINS_11LayoutT_DGZE14ScatteringSdomJRNS_6SdomIdES7_RNS_4Core3SetESA_SA_RNS8_5FieldIdJNS_6MomentENS_5GroupENS_4ZoneEEEESG_RNSB_IdJNS_8MaterialENS_8LegendreENS_11GlobalGroupESJ_EEERNSB_INS_7MixElemEJSE_EEERNSB_IiJSE_EEERNSB_ISH_JSM_EEERNSB_IdJSM_EEERNSB_ISI_JSC_EEEEEEvT_RKT0_DpOT1_.extracted+0x220>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMPQ $0,-0x38(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JLE 498b80 <_ZNK6Kripke14DispatchHelperINS_12ArchT_OpenMPEEclINS_11LayoutT_DGZE14ScatteringSdomJRNS_6SdomIdES7_RNS_4Core3SetESA_SA_RNS8_5FieldIdJNS_6MomentENS_5GroupENS_4ZoneEEEESG_RNSB_IdJNS_8MaterialENS_8LegendreENS_11GlobalGroupESJ_EEERNSB_INS_7MixElemEJSE_EEERNSB_IiJSE_EEERNSB_ISH_JSM_EEERNSB_IdJSM_EEERNSB_ISI_JSC_EEEEEEvT_RKT0_DpOT1_.extracted+0x360>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0xf0(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x108(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RAX,%RCX,8),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
IMUL -0xe8(%RBP),%R11	1	0	1	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1	N/A
ADD -0x30(%RBP),%R11	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
MOV -0xf8(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x48(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %RCX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %R11,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VPBROADCASTQ %RAX,%YMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
MOV -0x70(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
IMUL %RCX,%RAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV %RAX,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD -0x100(%RBP),%R11	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
ADD -0x78(%RBP),%R11	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
ADD %RCX,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
JMP 498c4b <_ZNK6Kripke14DispatchHelperINS_12ArchT_OpenMPEEclINS_11LayoutT_DGZE14ScatteringSdomJRNS_6SdomIdES7_RNS_4Core3SetESA_SA_RNS8_5FieldIdJNS_6MomentENS_5GroupENS_4ZoneEEEESG_RNSB_IdJNS_8MaterialENS_8LegendreENS_11GlobalGroupESJ_EEERNSB_INS_7MixElemEJSE_EEERNSB_IiJSE_EEERNSB_ISH_JSM_EEERNSB_IdJSM_EEERNSB_ISI_JSC_EEEEEEvT_RKT0_DpOT1_.extracted+0x42b>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A

Function	void Kripke::DispatchHelper::operator()&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&>(Kripke::LayoutT_DGZ, ScatteringSdom const&, Kripke::SdomId&, Kripke::SdomId&, Kripke::Core::Set&, Kripke::Core::Set&, Kripke::Core::Set&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&) const [clone .extracted]
Source file and lines	forall.hpp:59-59
Module	exec

The loop is defined in:

/home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/src/Kripke/Kernel/Scattering.cpp:87-97
/home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/index/IndexValue.hpp:105,217
/home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/loop/forall.hpp:59
/home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/Layout.hpp:55

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=5
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 4.33 to 2.33 cycles (1.86x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 11% of vector register length is used (average across all SSE/AVX instructions).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Performance is limited by reading data from caches/RAM (load units are a bottleneck).

Workaround

Read less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop

512-bits vectorization

Workaround

Recompile with -mprefer-vector-width=512

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 104 bytes. The binary loop is storing 16 bytes.

General properties

nb instructions	25
nb uops	25
loop length	112
used x86 registers	5
used mmx registers	0
used xmm registers	0
used ymm registers	1
used zmm registers	0
nb stack references	12

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	4.17 cycles
front end	4.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	2.60	2.60	4.33	4.33	1.00	2.60	2.60	1.00	1.00	1.00	2.60	4.33
cycles	2.60	3.60	4.33	4.33	1.00	2.60	2.60	1.00	1.00	1.00	2.60	4.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	4.17
Dispatch	4.33
Overall L1	4.33

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	11%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 4.33 cycles. At this rate:

12% of peak load performance is reached (24.00 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (3.69 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 498b96

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
MOV -0x48(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP -0x40(%RBP),%RAX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
LEA 0x1(%RAX),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,-0x48(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JE 498a40 <_ZNK6Kripke14DispatchHelperINS_12ArchT_OpenMPEEclINS_11LayoutT_DGZE14ScatteringSdomJRNS_6SdomIdES7_RNS_4Core3SetESA_SA_RNS8_5FieldIdJNS_6MomentENS_5GroupENS_4ZoneEEEESG_RNSB_IdJNS_8MaterialENS_8LegendreENS_11GlobalGroupESJ_EEERNSB_INS_7MixElemEJSE_EEERNSB_IiJSE_EEERNSB_ISH_JSM_EEERNSB_IdJSM_EEERNSB_ISI_JSC_EEEEEEvT_RKT0_DpOT1_.extracted+0x220>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMPQ $0,-0x38(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JLE 498b80 <_ZNK6Kripke14DispatchHelperINS_12ArchT_OpenMPEEclINS_11LayoutT_DGZE14ScatteringSdomJRNS_6SdomIdES7_RNS_4Core3SetESA_SA_RNS8_5FieldIdJNS_6MomentENS_5GroupENS_4ZoneEEEESG_RNSB_IdJNS_8MaterialENS_8LegendreENS_11GlobalGroupESJ_EEERNSB_INS_7MixElemEJSE_EEERNSB_IiJSE_EEERNSB_ISH_JSM_EEERNSB_IdJSM_EEERNSB_ISI_JSC_EEEEEEvT_RKT0_DpOT1_.extracted+0x360>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0xf0(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x108(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RAX,%RCX,8),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
IMUL -0xe8(%RBP),%R11	1	0	1	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1	N/A
ADD -0x30(%RBP),%R11	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
MOV -0xf8(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x48(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %RCX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %R11,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VPBROADCASTQ %RAX,%YMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
MOV -0x70(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
IMUL %RCX,%RAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV %RAX,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD -0x100(%RBP),%R11	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
ADD -0x78(%RBP),%R11	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
ADD %RCX,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
JMP 498c4b <_ZNK6Kripke14DispatchHelperINS_12ArchT_OpenMPEEclINS_11LayoutT_DGZE14ScatteringSdomJRNS_6SdomIdES7_RNS_4Core3SetESA_SA_RNS8_5FieldIdJNS_6MomentENS_5GroupENS_4ZoneEEEESG_RNSB_IdJNS_8MaterialENS_8LegendreENS_11GlobalGroupESJ_EEERNSB_INS_7MixElemEJSE_EEERNSB_IiJSE_EEERNSB_ISH_JSM_EEERNSB_IdJSM_EEERNSB_ISI_JSC_EEEEEEvT_RKT0_DpOT1_.extracted+0x42b>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

512-bits vectorization

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

512-bits vectorization

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code