OV - exec - Function void PopulationSdom::operator()<Kripke::ArchLayoutT<Kripke::ArchT_OpenMP, Kripke::LayoutT_DGZ> >(Kripke::ArchLayoutT<Kripke::ArchT_OpenMP, Kripke::LayoutT_DGZ>, Kripke::SdomId, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Field<double, Kripke::Direction, Kripke::Group, Kripke::Zone>&, Kripke::Core::Field<double, Kripke::Direction>&, Kripke::Core::Field<double, Kripke::Zone>&, double*) const [clone .extracted]

	Function: void PopulationSdom::operator()<Kripke::ArchLayoutT<Kripke::ArchT_OpenMP, Kripke::LayoutT_ ...	Module: exec	Source: Collapse.hpp:81-83 [...]	Coverage (incl. loops): 0.23% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/Operators.hpp: 307 - 307

--------------------------------------------------------------------------------

307:     return Ret{lhs} + rhs;

/home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/loop/forall.hpp: 59 - 59

--------------------------------------------------------------------------------

59:   for (decltype(distance_it) i = 0; i < distance_it; ++i) {

/home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/pattern/detail/reduce.hpp: 74 - 262

--------------------------------------------------------------------------------

74:     val = operator_type::operator()(val, v);

[...]

261:       : parent{other.parent ? other.parent : &other},

262:         identity{other.identity},

/home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/internal/Iterators.hpp: 55 - 177

--------------------------------------------------------------------------------

55:       : val(rhs.val)

[...]

177:     return value_type(val + rhs);

/home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/src/Kripke/Kernel/Population.cpp: 58 - 58

--------------------------------------------------------------------------------

58:           part_red += w(d) * psi(d,g,z) * volume(z);

/home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/Layout.hpp: 55 - 55

--------------------------------------------------------------------------------

55:     return a * b;

/home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/tpl/raja/tpl/camp/include/camp/tuple.hpp: 253 - 253

--------------------------------------------------------------------------------

253:   CAMP_HOST_DEVICE constexpr tuple(tuple const& o) : base(o.base) {}

/home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/View.hpp: 79 - 79

--------------------------------------------------------------------------------

79:       : layout(V.layout), data(V.data)

/home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/openmp/kernel/Collapse.hpp: 81 - 83

--------------------------------------------------------------------------------

81: #pragma omp parallel for private(i0, i1) firstprivate(privatizer) \

82:     RAJA_COLLAPSE(2)

83:     for (i0 = 0; i0 < l0; ++i0) {

0x486260 PUSH	%RBP

0x486261 MOV	%RSP,%RBP

0x486264 PUSH	%R15

0x486266 PUSH	%R14

0x486268 PUSH	%R13

0x48626a PUSH	%R12

0x48626c PUSH	%RBX

0x48626d AND	$-0x20,%RSP

0x486271 SUB	$0x200,%RSP

0x486278 MOVL	$0,0x94(%RSP)

0x486283 LEA	0x38(%R8),%RCX

0x486287 MOV	0x38(%R8),%RAX

0x48628b TEST	%RAX,%RAX

0x48628e CMOVNE	%RAX,%RCX

0x486292 TEST	%R9,%R9

0x486295 JS	486580

0x48629b MOV	%RCX,0xc8(%RSP)

0x4862a3 MOV	%RDX,%RBX

0x4862a6 MOV	(%R8),%RAX

0x4862a9 MOV	%RAX,0x18(%RSP)

0x4862ae MOV	0x10(%R8),%R13

0x4862b2 MOV	0x20(%R8),%R15

0x4862b6 MOV	0x28(%R8),%R12

0x4862ba MOV	0x70(%R8),%RAX

0x4862be MOV	%RAX,0x10(%RSP)

0x4862c3 MOV	0x90(%R8),%RAX

0x4862ca MOV	%RAX,0x28(%RSP)

0x4862cf MOV	0x98(%R8),%RAX

0x4862d6 MOV	%RAX,0x38(%RSP)

0x4862db MOV	0xd8(%R8),%RAX

0x4862e2 MOV	%RAX,0x40(%RSP)

0x4862e7 MOV	0x100(%R8),%RAX

0x4862ee MOV	%RAX,0x20(%RSP)

0x4862f3 VMOVSD	0x40(%R8),%XMM0

0x4862f9 VMOVSD	%XMM0,0x8(%RSP)

0x4862ff MOV	(%RDI),%ESI

0x486301 MOVQ	$0,0xb8(%RSP)

0x48630d MOV	%R9,0xb0(%RSP)

0x486315 MOVQ	$0x1,0x138(%RSP)

0x486321 SUB	$0x8,%RSP

0x486325 LEA	0x140(%RSP),%RAX

0x48632d LEA	0xd847c(%RIP),%RDI

0x486334 LEA	0x9c(%RSP),%RCX

0x48633c LEA	0xc0(%RSP),%R8

0x486344 LEA	0xb8(%RSP),%R9

0x48634c MOV	%ESI,0x98(%RSP)

0x486353 MOV	$0x22,%EDX

0x486358 PUSH	$0x1

0x48635a PUSH	$0x1

0x48635c PUSH	%RAX

0x48635d CALL	403140 <__kmpc_for_static_init_8@plt>

0x486362 ADD	$0x20,%RSP

0x486366 MOV	0xb8(%RSP),%RAX

0x48636e MOV	0xb0(%RSP),%RCX

0x486376 MOV	%RAX,0x88(%RSP)

0x48637e CMP	%RCX,%RAX

0x486381 JA	4865c0

0x486387 MOV	%R12,%RAX

0x48638a SUB	%R15,%RAX

0x48638d MOV	%RAX,0x30(%RSP)

0x486392 JLE	4865c0

0x486398 MOV	0x88(%RSP),%RAX

0x4863a0 LEA	0x1(%RAX),%RDX

0x4863a4 INC	%RCX

0x4863a7 CMP	%RCX,%RDX

0x4863aa MOV	%RDX,0xf8(%RSP)

0x4863b2 CMOVG	%RDX,%RCX

0x4863b6 SUB	%RAX,%RCX

0x4863b9 CMP	$0x8,%RCX

0x4863bd VMOVSD	0x8(%RSP),%XMM5

0x4863c3 MOV	0x20(%RSP),%RDX

0x4863c8 MOV	%RBX,0xa0(%RSP)

0x4863d0 MOV	%RCX,0xc0(%RSP)

0x4863d8 JAE	486640

0x4863de MOV	0xc0(%RSP),%R10

0x4863e6 MOV	%R10,%RCX

0x4863e9 AND	$-0x8,%RCX

0x4863ed DEC	%R10

0x4863f0 CMP	%RCX,%R10

0x4863f3 JB	4865c6

0x4863f9 MOV	0x30(%RSP),%RSI

0x4863fe AND	$-0x4,%RSI

0x486402 LEA	-0x1(%RSI),%RDI

0x486406 MOV	0x20(%RSP),%RAX

0x48640b LEA	(%RAX,%R15,8),%R8

0x48640f MOV	0x28(%RSP),%RAX

0x486414 LEA	(,%RAX,8),%R14

0x48641c MOV	0x38(%RSP),%RAX

0x486421 LEA	(,%RAX,8),%RAX

0x486429 MOV	%RAX,0x8(%RSP)

0x48642e JMP	486458

0x486430 NOPW	%CS:(%RAX,%RAX,1)

0x48643f NOP

(1121) 0x486440 MOV	%R10,%RAX

(1121) 0x486443 CMP	%R10,%RCX

(1121) 0x486446 LEA	0x1(%RCX),%RCX

(1121) 0x48644a MOV	0xa0(%RSP),%RBX

(1121) 0x486452 JE	4865c6

(1121) 0x486458 MOV	0x88(%RSP),%RAX

(1121) 0x486460 ADD	%RCX,%RAX

(1121) 0x486463 MOV	%RAX,%RDX

(1121) 0x486466 OR	%RBX,%RDX

(1121) 0x486469 SHR	$0x20,%RDX

(1121) 0x48646d JE	486480

(1121) 0x48646f CQTO

(1121) 0x486471 IDIV	%RBX

(1121) 0x486474 JMP	486484

0x486476 NOPW	%CS:(%RAX,%RAX,1)

(1121) 0x486480 XOR	%EDX,%EDX

(1121) 0x486482 DIV	%EBX

(1121) 0x486484 ADD	0x18(%RSP),%RAX

(1121) 0x486489 MOV	0x10(%RSP),%R9

(1121) 0x48648e VMOVSD	(%R9,%RAX,8),%XMM0

(1121) 0x486494 TEST	%RSI,%RSI

(1121) 0x486497 JE	486540

(1121) 0x48649d LEA	(%R13,%RDX,1),%R11

(1121) 0x4864a2 IMUL	0x38(%RSP),%R11

(1121) 0x4864a8 ADD	%R15,%R11

(1121) 0x4864ab MOV	0x28(%RSP),%RBX

(1121) 0x4864b0 IMUL	%RAX,%RBX

(1121) 0x4864b4 ADD	%R11,%RBX

(1121) 0x4864b7 VBROADCASTSD	%XMM0,%YMM2

(1121) 0x4864bc MOV	0x40(%RSP),%R11

(1121) 0x4864c1 LEA	(%R11,%RBX,8),%R11

(1121) 0x4864c5 VXORPD	%XMM1,%XMM1,%XMM1

(1121) 0x4864c9 XOR	%EBX,%EBX

(1121) 0x4864cb NOPL	(%RAX,%RAX,1)

  (1122) 0x4864d0 VMULPD	(%R11,%RBX,8),%YMM2,%YMM3

  (1122) 0x4864d6 VFMADD231PD	(%R8,%RBX,8),%YMM3,%YMM1

  (1122) 0x4864dc ADD	$0x4,%RBX

  (1122) 0x4864e0 CMP	%RDI,%RBX

  (1122) 0x4864e3 JLE	4864d0

(1121) 0x4864e5 VEXTRACTF128	$0x1,%YMM1,%XMM2

(1121) 0x4864eb VADDPD	%XMM2,%XMM1,%XMM1

(1121) 0x4864ef VSHUFPD	$0x1,%XMM1,%XMM1,%XMM2

(1121) 0x4864f4 VADDSD	%XMM2,%XMM1,%XMM1

(1121) 0x4864f8 VADDSD	%XMM1,%XMM5,%XMM5

(1121) 0x4864fc MOV	%RSI,%RBX

(1121) 0x4864ff CMP	%RSI,0x30(%RSP)

(1121) 0x486504 MOV	0x20(%RSP),%R9

(1121) 0x486509 JE	486440

(1121) 0x48650f JMP	486547

0x486511 NOPW	%CS:(%RAX,%RAX,1)

0x486520 NOPW	%CS:(%RAX,%RAX,1)

0x48652f NOPW	%CS:(%RAX,%RAX,1)

0x48653e XCHG	%AX,%AX

(1121) 0x486540 XOR	%EBX,%EBX

(1121) 0x486542 MOV	0x20(%RSP),%R9

(1121) 0x486547 ADD	%R13,%RDX

(1121) 0x48654a IMUL	0x8(%RSP),%RDX

(1121) 0x486550 ADD	%R15,%RBX

(1121) 0x486553 IMUL	%R14,%RAX

(1121) 0x486557 ADD	%RDX,%RAX

(1121) 0x48655a ADD	0x40(%RSP),%RAX

(1121) 0x48655f NOP

  (1120) 0x486560 VMULSD	(%RAX,%RBX,8),%XMM0,%XMM1

  (1120) 0x486565 VFMADD231SD	(%R9,%RBX,8),%XMM1,%XMM5

  (1120) 0x48656b INC	%RBX

  (1120) 0x48656e CMP	%RBX,%R12

  (1120) 0x486571 JNE	486560

(1121) 0x486573 JMP	486440

0x486578 NOPL	(%RAX,%RAX,1)

0x486580 LEA	-0x28(%RBP),%RSP

0x486584 POP	%RBX

0x486585 POP	%R12

0x486587 POP	%R13

0x486589 POP	%R14

0x48658b POP	%R15

0x48658d POP	%RBP

0x48658e RET

0x48658f NOPW	%CS:(%RAX,%RAX,1)

0x48659e NOPW	%CS:(%RAX,%RAX,1)

0x4865ad NOPW	%CS:(%RAX,%RAX,1)

0x4865bc NOPL	(%RAX)

0x4865c0 VMOVSD	0x8(%RSP),%XMM5

0x4865c6 VMOVSD	%XMM5,0x8(%RSP)

0x4865cc LEA	0xd81fd(%RIP),%RDI

0x4865d3 MOV	0x90(%RSP),%ESI

0x4865da VZEROUPPER

0x4865dd CALL	403050 <__kmpc_for_static_fini@plt>

0x4865e2 LEA	0xd8407(%RIP),%RDI

0x4865e9 CALL	403110 <__kmpc_global_thread_num@plt>

0x4865ee MOV	%EAX,%EBX

0x4865f0 LEA	0xd8179(%RIP),%RDI

0x4865f7 MOV	$0x5600e0,%R14

0x4865fe MOV	%EAX,%ESI

0x486600 MOV	%R14,%RDX

0x486603 CALL	403390 <__kmpc_critical@plt>

0x486608 MOV	0xc8(%RSP),%RAX

0x486610 VMOVSD	0x8(%RSP),%XMM0

0x486616 VADDSD	0x10(%RAX),%XMM0,%XMM0

0x48661b VMOVSD	%XMM0,0x10(%RAX)

0x486620 LEA	0xd8169(%RIP),%RDI

0x486627 MOV	%EBX,%ESI

0x486629 MOV	%R14,%RDX

0x48662c LEA	-0x28(%RBP),%RSP

0x486630 POP	%RBX

0x486631 POP	%R12

0x486633 POP	%R13

0x486635 POP	%R14

0x486637 POP	%R15

0x486639 POP	%RBP

0x48663a JMP	403170

0x48663f NOP

0x486640 SHR	$0x3,%RCX

0x486644 DEC	%RCX

0x486647 MOV	%RCX,0xf0(%RSP)

0x48664f MOV	0x30(%RSP),%RAX

0x486654 MOV	%RAX,%R8

0x486657 AND	$-0x4,%R8

0x48665b LEA	-0x1(%R8),%RCX

0x48665f MOV	%RCX,0xd8(%RSP)

0x486667 VPBROADCASTQ	%RAX,%YMM0

0x48666d VMOVDQU	%YMM0,0x140(%RSP)

0x486676 LEA	(%RDX,%R15,8),%RAX

0x48667a MOV	%RAX,0xd0(%RSP)

0x486682 XOR	%ESI,%ESI

0x486684 MOV	%R13,0xe8(%RSP)

0x48668c MOV	%R12,0xe0(%RSP)

0x486694 MOV	%R8,0x98(%RSP)

0x48669c JMP	48696b

0x4866a1 NOPW	%CS:(%RAX,%RAX,1)

0x4866b0 NOPW	%CS:(%RAX,%RAX,1)

0x4866bf NOP

(1123) 0x4866c0 MOV	0x28(%RSP),%RDX

(1123) 0x4866c5 IMUL	%RDX,%RDI

(1123) 0x4866c9 ADD	%R15,%RDI

(1123) 0x4866cc MOV	0x80(%RSP),%RAX

(1123) 0x4866d4 ADD	%R13,%RAX

(1123) 0x4866d7 MOV	%RCX,%R8

(1123) 0x4866da MOV	%RSI,%RCX

(1123) 0x4866dd MOV	0x38(%RSP),%RSI

(1123) 0x4866e2 IMUL	%RSI,%RAX

(1123) 0x4866e6 ADD	%RDI,%RAX

(1123) 0x4866e9 ADD	%R9,%RAX

(1123) 0x4866ec MOV	0x40(%RSP),%RDI

(1123) 0x4866f1 VMOVUPD	(%RDI,%RAX,8),%YMM27{%K1}{z}

(1123) 0x4866f8 MOV	%RCX,%RAX

(1123) 0x4866fb LEA	(%R15,%R9,1),%RCX

(1123) 0x4866ff MOV	%R10,%RDX

(1123) 0x486702 MOV	0x20(%RSP),%R10

(1123) 0x486707 VMOVUPD	(%R10,%RCX,8),%YMM26{%K1}{z}

(1123) 0x48670e MOV	%RAX,%RCX

(1123) 0x486711 MOV	0x28(%RSP),%R10

(1123) 0x486716 IMUL	%R10,%R8

(1123) 0x48671a ADD	%R15,%R8

(1123) 0x48671d MOV	0x78(%RSP),%RAX

(1123) 0x486722 ADD	%R13,%RAX

(1123) 0x486725 IMUL	%RSI,%RAX

(1123) 0x486729 ADD	%R8,%RAX

(1123) 0x48672c MOV	0x98(%RSP),%R8

(1123) 0x486734 ADD	%R9,%RAX

(1123) 0x486737 VMOVUPD	(%RDI,%RAX,8),%YMM28{%K1}{z}

(1123) 0x48673e IMUL	%R10,%RDX

(1123) 0x486742 ADD	%R15,%RDX

(1123) 0x486745 MOV	0x70(%RSP),%RAX

(1123) 0x48674a ADD	%R13,%RAX

(1123) 0x48674d IMUL	%RSI,%RAX

(1123) 0x486751 ADD	%RDX,%RAX

(1123) 0x486754 ADD	%R9,%RAX

(1123) 0x486757 VMOVUPD	(%RDI,%RAX,8),%YMM29{%K1}{z}

(1123) 0x48675e IMUL	%R10,%R11

(1123) 0x486762 ADD	%R15,%R11

(1123) 0x486765 MOV	0x68(%RSP),%RAX

(1123) 0x48676a ADD	%R13,%RAX

(1123) 0x48676d IMUL	%RSI,%RAX

(1123) 0x486771 ADD	%R11,%RAX

(1123) 0x486774 ADD	%R9,%RAX

(1123) 0x486777 VMOVUPD	(%RDI,%RAX,8),%YMM30{%K1}{z}

(1123) 0x48677e IMUL	%R10,%R14

(1123) 0x486782 ADD	%R15,%R14

(1123) 0x486785 MOV	0x60(%RSP),%RAX

(1123) 0x48678a ADD	%R13,%RAX

(1123) 0x48678d IMUL	%RSI,%RAX

(1123) 0x486791 ADD	%R14,%RAX

(1123) 0x486794 ADD	%R9,%RAX

(1123) 0x486797 VMOVUPD	(%RDI,%RAX,8),%YMM31{%K1}{z}

(1123) 0x48679e MOV	0x8(%RSP),%RDX

(1123) 0x4867a3 IMUL	%R10,%RDX

(1123) 0x4867a7 ADD	%R15,%RDX

(1123) 0x4867aa MOV	0x58(%RSP),%RAX

(1123) 0x4867af ADD	%R13,%RAX

(1123) 0x4867b2 IMUL	%RSI,%RAX

(1123) 0x4867b6 ADD	%RDX,%RAX

(1123) 0x4867b9 ADD	%R9,%RAX

(1123) 0x4867bc VMOVUPD	(%RDI,%RAX,8),%YMM0{%K1}{z}

(1123) 0x4867c3 MOV	0xa8(%RSP),%RDX

(1123) 0x4867cb IMUL	%R10,%RDX

(1123) 0x4867cf ADD	%R15,%RDX

(1123) 0x4867d2 MOV	0x50(%RSP),%RAX

(1123) 0x4867d7 ADD	%R13,%RAX

(1123) 0x4867da IMUL	%RSI,%RAX

(1123) 0x4867de ADD	%RDX,%RAX

(1123) 0x4867e1 ADD	%R9,%RAX

(1123) 0x4867e4 VMOVUPD	(%RDI,%RAX,8),%YMM1{%K1}{z}

(1123) 0x4867eb MOV	0x130(%RSP),%RAX

(1123) 0x4867f3 IMUL	%R10,%RAX

(1123) 0x4867f7 ADD	%R9,%RAX

(1123) 0x4867fa MOV	0x48(%RSP),%RDX

(1123) 0x4867ff ADD	%R13,%RDX

(1123) 0x486802 IMUL	%RSI,%RDX

(1123) 0x486806 MOV	%RCX,%RSI

(1123) 0x486809 ADD	%R15,%RDX

(1123) 0x48680c ADD	%RDX,%RAX

(1123) 0x48680f VMOVUPD	(%RDI,%RAX,8),%YMM2{%K1}{z}

(1123) 0x486816 VMOVAPD	%YMM27,%YMM17{%K1}

(1123) 0x48681c VMOVAPD	%YMM28,%YMM15{%K1}

(1123) 0x486822 VBROADCASTSD	%XMM18,%YMM3

(1123) 0x486828 VMULPD	%YMM3,%YMM17,%YMM3

(1123) 0x48682e VMOVAPD	%YMM26,%YMM16{%K1}

(1123) 0x486834 VMULPD	%YMM16,%YMM3,%YMM3

(1123) 0x48683a VBROADCASTSD	%XMM19,%YMM4

(1123) 0x486840 VMULPD	%YMM4,%YMM15,%YMM4

(1123) 0x486844 VMOVAPD	%YMM26,%YMM14{%K1}

(1123) 0x48684a VFMADD213PD	%YMM3,%YMM14,%YMM4

(1123) 0x48684f VMOVAPD	%YMM29,%YMM13{%K1}

(1123) 0x486855 VBROADCASTSD	%XMM20,%YMM3

(1123) 0x48685b VMULPD	%YMM3,%YMM13,%YMM3

(1123) 0x48685f VMOVAPD	%YMM26,%YMM12{%K1}

(1123) 0x486865 VFMADD213PD	%YMM4,%YMM12,%YMM3

(1123) 0x48686a VMOVAPD	%YMM30,%YMM11{%K1}

(1123) 0x486870 VBROADCASTSD	%XMM21,%YMM4

(1123) 0x486876 VMULPD	%YMM4,%YMM11,%YMM4

(1123) 0x48687a VMOVAPD	%YMM26,%YMM10{%K1}

(1123) 0x486880 VFMADD213PD	%YMM3,%YMM10,%YMM4

(1123) 0x486885 VMOVAPD	%YMM31,%YMM9{%K1}

(1123) 0x48688b VBROADCASTSD	%XMM22,%YMM3

(1123) 0x486891 VMULPD	%YMM3,%YMM9,%YMM3

(1123) 0x486895 VMOVAPD	%YMM26,%YMM8{%K1}

(1123) 0x48689b VFMADD213PD	%YMM4,%YMM8,%YMM3

(1123) 0x4868a0 VMOVAPD	%YMM0,%YMM7{%K1}

(1123) 0x4868a6 VBROADCASTSD	%XMM23,%YMM0

(1123) 0x4868ac VMULPD	%YMM0,%YMM7,%YMM0

(1123) 0x4868b0 VMOVAPD	%YMM26,%YMM6{%K1}

(1123) 0x4868b6 VFMADD213PD	%YMM3,%YMM6,%YMM0

(1123) 0x4868bb VMOVUPD	0x160(%RSP),%YMM3

(1123) 0x4868c4 VMOVAPD	%YMM1,%YMM3{%K1}

(1123) 0x4868ca VBROADCASTSD	%XMM24,%YMM1

(1123) 0x4868d0 VMOVUPD	%YMM3,0x160(%RSP)

(1123) 0x4868d9 VMULPD	%YMM1,%YMM3,%YMM1

(1123) 0x4868dd VMOVUPD	0x180(%RSP),%YMM3

(1123) 0x4868e6 VMOVAPD	%YMM26,%YMM3{%K1}

(1123) 0x4868ec VMOVUPD	%YMM3,0x180(%RSP)

(1123) 0x4868f5 VFMADD213PD	%YMM0,%YMM3,%YMM1

(1123) 0x4868fa VMOVUPD	0x1a0(%RSP),%YMM3

(1123) 0x486903 VMOVAPD	%YMM2,%YMM3{%K1}

(1123) 0x486909 VBROADCASTSD	%XMM25,%YMM0

(1123) 0x48690f VMOVUPD	%YMM3,0x1a0(%RSP)

(1123) 0x486918 VMULPD	%YMM0,%YMM3,%YMM18

(1123) 0x48691e VMOVUPD	0x1c0(%RSP),%YMM0

(1123) 0x486927 VMOVAPD	%YMM26,%YMM0{%K1}

(1123) 0x48692d VMOVUPD	%YMM0,0x1c0(%RSP)

(1123) 0x486936 VFMADD213PD	%YMM1,%YMM0,%YMM18

(1123) 0x48693c VMOVAPD	%YMM18,%YMM0{%K1}{z}

(1123) 0x486942 VEXTRACTF128	$0x1,%YMM0,%XMM1

(1123) 0x486948 VADDPD	%XMM1,%XMM0,%XMM0

(1123) 0x48694c VSHUFPD	$0x1,%XMM0,%XMM0,%XMM1

(1123) 0x486951 VADDSD	%XMM1,%XMM0,%XMM0

(1123) 0x486955 VADDSD	%XMM0,%XMM5,%XMM5

(1123) 0x486959 CMP	0xf0(%RSP),%RSI

(1123) 0x486961 LEA	0x1(%RSI),%RSI

(1123) 0x486965 JE	4863de

(1123) 0x48696b MOV	0x88(%RSP),%RAX

(1123) 0x486973 LEA	(%RAX,%RSI,8),%R9

(1123) 0x486977 MOV	%R9,%RAX

(1123) 0x48697a OR	%RBX,%RAX

(1123) 0x48697d SHR	$0x20,%RAX

(1123) 0x486981 JE	4869c0

(1123) 0x486983 MOV	%R9,%RAX

(1123) 0x486986 CQTO

(1123) 0x486988 IDIV	%RBX

(1123) 0x48698b MOV	%RDX,0x80(%RSP)

(1123) 0x486993 MOV	%RAX,%RDI

(1123) 0x486996 JMP	4869d1

0x486998 NOPW	%CS:(%RAX,%RAX,1)

0x4869a7 NOPW	%CS:(%RAX,%RAX,1)

0x4869b6 NOPW	%CS:(%RAX,%RAX,1)

(1123) 0x4869c0 MOV	%R9D,%EAX

(1123) 0x4869c3 XOR	%EDX,%EDX

(1123) 0x4869c5 DIV	%EBX

(1123) 0x4869c7 MOV	%RDX,0x80(%RSP)

(1123) 0x4869cf MOV	%EAX,%EDI

(1123) 0x4869d1 LEA	(,%RSI,8),%RAX

(1123) 0x4869d9 ADD	0x18(%RSP),%RDI

(1123) 0x4869de MOV	0x10(%RSP),%RDX

(1123) 0x4869e3 VMOVSD	(%RDX,%RDI,8),%XMM18

(1123) 0x4869ea ADD	0xf8(%RSP),%RAX

(1123) 0x4869f2 MOV	%RAX,%RDX

(1123) 0x4869f5 OR	%RBX,%RDX

(1123) 0x4869f8 SHR	$0x20,%RDX

(1123) 0x4869fc JE	486a40

(1123) 0x4869fe CQTO

(1123) 0x486a00 IDIV	%RBX

(1123) 0x486a03 MOV	%RDX,0x78(%RSP)

(1123) 0x486a08 MOV	%RAX,%RCX

(1123) 0x486a0b JMP	486a4b

0x486a0d NOPW	%CS:(%RAX,%RAX,1)

0x486a1c NOPW	%CS:(%RAX,%RAX,1)

0x486a2b NOPW	%CS:(%RAX,%RAX,1)

0x486a3a NOPW	(%RAX,%RAX,1)

(1123) 0x486a40 XOR	%EDX,%EDX

(1123) 0x486a42 DIV	%EBX

(1123) 0x486a44 MOV	%RDX,0x78(%RSP)

(1123) 0x486a49 MOV	%EAX,%ECX

(1123) 0x486a4b ADD	0x18(%RSP),%RCX

(1123) 0x486a50 MOV	0x10(%RSP),%RAX

(1123) 0x486a55 VMOVSD	(%RAX,%RCX,8),%XMM19

(1123) 0x486a5c LEA	0x2(%R9),%RAX

(1123) 0x486a60 MOV	%RAX,%RDX

(1123) 0x486a63 OR	%RBX,%RDX

(1123) 0x486a66 SHR	$0x20,%RDX

(1123) 0x486a6a JE	486a80

(1123) 0x486a6c CQTO

(1123) 0x486a6e IDIV	%RBX

(1123) 0x486a71 MOV	%RDX,0x70(%RSP)

(1123) 0x486a76 MOV	%RAX,%R10

(1123) 0x486a79 JMP	486a8c

0x486a7b NOPL	(%RAX,%RAX,1)

(1123) 0x486a80 XOR	%EDX,%EDX

(1123) 0x486a82 DIV	%EBX

(1123) 0x486a84 MOV	%RDX,0x70(%RSP)

(1123) 0x486a89 MOV	%EAX,%R10D

(1123) 0x486a8c ADD	0x18(%RSP),%R10

(1123) 0x486a91 MOV	0x10(%RSP),%RAX

(1123) 0x486a96 VMOVSD	(%RAX,%R10,8),%XMM20

(1123) 0x486a9d LEA	0x3(%R9),%RAX

(1123) 0x486aa1 MOV	%RAX,%RDX

(1123) 0x486aa4 OR	%RBX,%RDX

(1123) 0x486aa7 SHR	$0x20,%RDX

(1123) 0x486aab JE	486ac0

(1123) 0x486aad CQTO

(1123) 0x486aaf IDIV	%RBX

(1123) 0x486ab2 MOV	%RDX,0x68(%RSP)

(1123) 0x486ab7 MOV	%RAX,%R11

(1123) 0x486aba JMP	486acc

0x486abc NOPL	(%RAX)

(1123) 0x486ac0 XOR	%EDX,%EDX

(1123) 0x486ac2 DIV	%EBX

(1123) 0x486ac4 MOV	%RDX,0x68(%RSP)

(1123) 0x486ac9 MOV	%EAX,%R11D

(1123) 0x486acc ADD	0x18(%RSP),%R11

(1123) 0x486ad1 MOV	0x10(%RSP),%RAX

(1123) 0x486ad6 VMOVSD	(%RAX,%R11,8),%XMM21

(1123) 0x486add LEA	0x4(%R9),%RAX

(1123) 0x486ae1 MOV	%RAX,%RDX

(1123) 0x486ae4 OR	%RBX,%RDX

(1123) 0x486ae7 SHR	$0x20,%RDX

(1123) 0x486aeb JE	486b00

(1123) 0x486aed CQTO

(1123) 0x486aef IDIV	%RBX

(1123) 0x486af2 MOV	%RDX,0x60(%RSP)

(1123) 0x486af7 MOV	%RAX,%R14

(1123) 0x486afa JMP	486b0c

0x486afc NOPL	(%RAX)

(1123) 0x486b00 XOR	%EDX,%EDX

(1123) 0x486b02 DIV	%EBX

(1123) 0x486b04 MOV	%RDX,0x60(%RSP)

(1123) 0x486b09 MOV	%EAX,%R14D

(1123) 0x486b0c ADD	0x18(%RSP),%R14

(1123) 0x486b11 MOV	0x10(%RSP),%RAX

(1123) 0x486b16 VMOVSD	(%RAX,%R14,8),%XMM22

(1123) 0x486b1d LEA	0x5(%R9),%RAX

(1123) 0x486b21 MOV	%RAX,%RDX

(1123) 0x486b24 OR	%RBX,%RDX

(1123) 0x486b27 SHR	$0x20,%RDX

(1123) 0x486b2b JE	486b40

(1123) 0x486b2d CQTO

(1123) 0x486b2f IDIV	%RBX

(1123) 0x486b32 MOV	%RDX,0x58(%RSP)

(1123) 0x486b37 JMP	486b49

0x486b39 NOPL	(%RAX)

(1123) 0x486b40 XOR	%EDX,%EDX

(1123) 0x486b42 DIV	%EBX

(1123) 0x486b44 MOV	%RDX,0x58(%RSP)

(1123) 0x486b49 ADD	0x18(%RSP),%RAX

(1123) 0x486b4e MOV	%RAX,%RDX

(1123) 0x486b51 MOV	0x10(%RSP),%RAX

(1123) 0x486b56 MOV	%RDX,0x8(%RSP)

(1123) 0x486b5b VMOVSD	(%RAX,%RDX,8),%XMM23

(1123) 0x486b62 LEA	0x6(%R9),%RAX

(1123) 0x486b66 MOV	%RAX,%RDX

(1123) 0x486b69 OR	%RBX,%RDX

(1123) 0x486b6c SHR	$0x20,%RDX

(1123) 0x486b70 JE	486bc0

(1123) 0x486b72 CQTO

(1123) 0x486b74 IDIV	%RBX

(1123) 0x486b77 MOV	%RDX,0x50(%RSP)

(1123) 0x486b7c MOV	%RAX,%RDX

(1123) 0x486b7f JMP	486bcb

0x486b81 NOPW	%CS:(%RAX,%RAX,1)

0x486b90 NOPW	%CS:(%RAX,%RAX,1)

0x486b9f NOPW	%CS:(%RAX,%RAX,1)

0x486bae NOPW	%CS:(%RAX,%RAX,1)

0x486bbd NOPL	(%RAX)

(1123) 0x486bc0 XOR	%EDX,%EDX

(1123) 0x486bc2 DIV	%EBX

(1123) 0x486bc4 MOV	%RDX,0x50(%RSP)

(1123) 0x486bc9 MOV	%EAX,%EDX

(1123) 0x486bcb ADD	0x18(%RSP),%RDX

(1123) 0x486bd0 MOV	0x10(%RSP),%RAX

(1123) 0x486bd5 VMOVSD	(%RAX,%RDX,8),%XMM24

(1123) 0x486bdc ADD	$0x7,%R9

(1123) 0x486be0 MOV	%R9,%RAX

(1123) 0x486be3 OR	%RBX,%RAX

(1123) 0x486be6 SHR	$0x20,%RAX

(1123) 0x486bea MOV	%RDX,0xa8(%RSP)

(1123) 0x486bf2 JE	486c40

(1123) 0x486bf4 MOV	%R9,%RAX

(1123) 0x486bf7 CQTO

(1123) 0x486bf9 IDIV	%RBX

(1123) 0x486bfc MOV	%RDX,0x48(%RSP)

(1123) 0x486c01 MOV	%RAX,%RDX

(1123) 0x486c04 JMP	486c4e

0x486c06 NOPW	%CS:(%RAX,%RAX,1)

0x486c15 NOPW	%CS:(%RAX,%RAX,1)

0x486c24 NOPW	%CS:(%RAX,%RAX,1)

0x486c33 NOPW	%CS:(%RAX,%RAX,1)

(1123) 0x486c40 MOV	%R9D,%EAX

(1123) 0x486c43 XOR	%EDX,%EDX

(1123) 0x486c45 DIV	%EBX

(1123) 0x486c47 MOV	%RDX,0x48(%RSP)

(1123) 0x486c4c MOV	%EAX,%EDX

(1123) 0x486c4e ADD	0x18(%RSP),%RDX

(1123) 0x486c53 MOV	0x10(%RSP),%RAX

(1123) 0x486c58 VMOVSD	(%RAX,%RDX,8),%XMM25

(1123) 0x486c5f TEST	%R8,%R8

(1123) 0x486c62 MOV	%RDX,0x130(%RSP)

(1123) 0x486c6a JE	486f00

(1123) 0x486c70 MOV	%RSI,0x128(%RSP)

(1123) 0x486c78 MOV	0x28(%RSP),%RBX

(1123) 0x486c7d MOV	%RDX,%RSI

(1123) 0x486c80 MOV	%RBX,%R9

(1123) 0x486c83 MOV	%RDI,0x120(%RSP)

(1123) 0x486c8b IMUL	%RDI,%R9

(1123) 0x486c8f MOV	%RBX,%R8

(1123) 0x486c92 MOV	%RCX,0x118(%RSP)

(1123) 0x486c9a IMUL	%RCX,%R8

(1123) 0x486c9e MOV	%RBX,%RCX

(1123) 0x486ca1 MOV	%R10,0x110(%RSP)

(1123) 0x486ca9 IMUL	%R10,%RCX

(1123) 0x486cad MOV	%R14,%RAX

(1123) 0x486cb0 MOV	%RBX,%R14

(1123) 0x486cb3 MOV	%R11,0x108(%RSP)

(1123) 0x486cbb IMUL	%R11,%R14

(1123) 0x486cbf MOV	%RBX,%R12

(1123) 0x486cc2 MOV	%RAX,0x100(%RSP)

(1123) 0x486cca IMUL	%RAX,%R12

(1123) 0x486cce MOV	%RBX,%R11

(1123) 0x486cd1 IMUL	0x8(%RSP),%R11

(1123) 0x486cd7 MOV	%R15,%RDX

(1123) 0x486cda MOV	%RBX,%R15

(1123) 0x486cdd IMUL	0xa8(%RSP),%R15

(1123) 0x486ce6 MOV	0x48(%RSP),%RAX

(1123) 0x486ceb LEA	(%R13,%RAX,1),%RDI

(1123) 0x486cf0 MOV	0x38(%RSP),%R10

(1123) 0x486cf5 IMUL	%R10,%RDI

(1123) 0x486cf9 ADD	%RDX,%RDI

(1123) 0x486cfc IMUL	%RSI,%RBX

(1123) 0x486d00 ADD	%RDI,%RBX

(1123) 0x486d03 MOV	0x50(%RSP),%RAX

(1123) 0x486d08 LEA	(%RAX,%R13,1),%RDI

(1123) 0x486d0c IMUL	%R10,%RDI

(1123) 0x486d10 ADD	%RDX,%RDI

(1123) 0x486d13 ADD	%R15,%RDI

(1123) 0x486d16 MOV	0x58(%RSP),%RAX

(1123) 0x486d1b LEA	(%RAX,%R13,1),%R15

(1123) 0x486d1f IMUL	%R10,%R15

(1123) 0x486d23 ADD	%RDX,%R15

(1123) 0x486d26 ADD	%R11,%R15

(1123) 0x486d29 MOV	0x60(%RSP),%RAX

(1123) 0x486d2e LEA	(%RAX,%R13,1),%R11

(1123) 0x486d32 IMUL	%R10,%R11

(1123) 0x486d36 ADD	%RDX,%R11

(1123) 0x486d39 ADD	%R12,%R11

(1123) 0x486d3c MOV	0x68(%RSP),%RAX

(1123) 0x486d41 LEA	(%RAX,%R13,1),%R12

(1123) 0x486d45 IMUL	%R10,%R12

(1123) 0x486d49 ADD	%RDX,%R12

(1123) 0x486d4c ADD	%R14,%R12

(1123) 0x486d4f MOV	%R13,%RSI

(1123) 0x486d52 MOV	0x70(%RSP),%RAX

(1123) 0x486d57 ADD	%RAX,%R13

(1123) 0x486d5a IMUL	%R10,%R13

(1123) 0x486d5e ADD	%RDX,%R13

(1123) 0x486d61 ADD	%RCX,%R13

(1123) 0x486d64 MOV	0x78(%RSP),%RAX

(1123) 0x486d69 LEA	(%RAX,%RSI,1),%RCX

(1123) 0x486d6d IMUL	%R10,%RCX

(1123) 0x486d71 ADD	%RDX,%RCX

(1123) 0x486d74 ADD	%R8,%RCX

(1123) 0x486d77 MOV	0x80(%RSP),%RAX

(1123) 0x486d7f ADD	%RAX,%RSI

(1123) 0x486d82 IMUL	%R10,%RSI

(1123) 0x486d86 VBROADCASTSD	%XMM18,%YMM26

(1123) 0x486d8c VBROADCASTSD	%XMM19,%YMM27

(1123) 0x486d92 VBROADCASTSD	%XMM20,%YMM28

(1123) 0x486d98 VBROADCASTSD	%XMM21,%YMM29

(1123) 0x486d9e VBROADCASTSD	%XMM22,%YMM30

(1123) 0x486da4 VBROADCASTSD	%XMM23,%YMM31

(1123) 0x486daa VBROADCASTSD	%XMM24,%YMM1

(1123) 0x486db0 VBROADCASTSD	%XMM25,%YMM0

(1123) 0x486db6 MOV	0x40(%RSP),%RAX

(1123) 0x486dbb LEA	(%RAX,%RBX,8),%R8

(1123) 0x486dbf LEA	(%RAX,%RDI,8),%RDI

(1123) 0x486dc3 LEA	(%RAX,%R15,8),%R10

(1123) 0x486dc7 LEA	(%RAX,%R11,8),%RBX

(1123) 0x486dcb LEA	(%RAX,%R12,8),%R14

(1123) 0x486dcf LEA	(%RAX,%R13,8),%R12

(1123) 0x486dd3 LEA	(%RAX,%RCX,8),%R11

(1123) 0x486dd7 MOV	%RDX,%RCX

(1123) 0x486dda ADD	%RDX,%RSI

(1123) 0x486ddd ADD	%R9,%RSI

(1123) 0x486de0 LEA	(%RAX,%RSI,8),%R9

(1123) 0x486de4 VXORPD	%XMM2,%XMM2,%XMM2

(1123) 0x486de8 XOR	%R15D,%R15D

(1123) 0x486deb MOV	0xd8(%RSP),%RAX

(1123) 0x486df3 MOV	0xd0(%RSP),%RDX

(1123) 0x486dfb NOPL	(%RAX,%RAX,1)

  (1124) 0x486e00 VMULPD	(%R9,%R15,8),%YMM26,%YMM3

  (1124) 0x486e07 VFMADD231PD	(%R11,%R15,8),%YMM27,%YMM3

  (1124) 0x486e0e VMOVUPD	(%RDX,%R15,8),%YMM4

  (1124) 0x486e14 VFMADD231PD	(%R12,%R15,8),%YMM28,%YMM3

  (1124) 0x486e1b VFMADD231PD	(%R14,%R15,8),%YMM29,%YMM3

  (1124) 0x486e22 VFMADD213PD	%YMM2,%YMM4,%YMM3

  (1124) 0x486e27 VMULPD	(%RBX,%R15,8),%YMM30,%YMM2

  (1124) 0x486e2e VFMADD231PD	(%R10,%R15,8),%YMM31,%YMM2

  (1124) 0x486e35 VFMADD231PD	(%RDI,%R15,8),%YMM1,%YMM2

  (1124) 0x486e3b VFMADD231PD	(%R8,%R15,8),%YMM0,%YMM2

  (1124) 0x486e41 VFMADD213PD	%YMM3,%YMM4,%YMM2

  (1124) 0x486e46 ADD	$0x4,%R15

  (1124) 0x486e4a CMP	%RAX,%R15

  (1124) 0x486e4d JLE	486e00

(1123) 0x486e4f VEXTRACTF128	$0x1,%YMM2,%XMM0

(1123) 0x486e55 VADDPD	%XMM0,%XMM2,%XMM0

(1123) 0x486e59 VSHUFPD	$0x1,%XMM0,%XMM0,%XMM1

(1123) 0x486e5e VADDSD	%XMM1,%XMM0,%XMM0

(1123) 0x486e62 VADDSD	%XMM0,%XMM5,%XMM5

(1123) 0x486e66 MOV	0x98(%RSP),%R8

(1123) 0x486e6e MOV	%R8,%R9

(1123) 0x486e71 CMP	%R8,0x30(%RSP)

(1123) 0x486e76 MOV	0xe8(%RSP),%R13

(1123) 0x486e7e MOV	%RCX,%R15

(1123) 0x486e81 MOV	0xe0(%RSP),%R12

(1123) 0x486e89 MOV	0xa0(%RSP),%RBX

(1123) 0x486e91 MOV	0x128(%RSP),%RSI

(1123) 0x486e99 MOV	0x120(%RSP),%RDI

(1123) 0x486ea1 MOV	0x118(%RSP),%RCX

(1123) 0x486ea9 MOV	0x110(%RSP),%R10

(1123) 0x486eb1 MOV	0x108(%RSP),%R11

(1123) 0x486eb9 MOV	0x100(%RSP),%R14

(1123) 0x486ec1 JE	486959

(1123) 0x486ec7 JMP	486f03

0x486ec9 NOPW	%CS:(%RAX,%RAX,1)

0x486ed8 NOPW	%CS:(%RAX,%RAX,1)

0x486ee7 NOPW	%CS:(%RAX,%RAX,1)

0x486ef6 NOPW	%CS:(%RAX,%RAX,1)

(1123) 0x486f00 XOR	%R9D,%R9D

(1123) 0x486f03 VPBROADCASTQ	%R9,%YMM0

(1123) 0x486f09 VMOVDQU	0x140(%RSP),%YMM1

(1123) 0x486f12 VPSUBQ	%YMM0,%YMM1,%YMM0

(1123) 0x486f16 VPCMPNLEUQ	0x8bfff(%RIP),%YMM0,%K1

(1123) 0x486f21 KORTESTB	%K1,%K1

(1123) 0x486f25 JNE	4866c0

(1123) 0x486f2b VXORPD	%XMM18,%XMM18,%XMM18

(1123) 0x486f31 JMP	48693c

0x486f36 NOPW	%CS:(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
►100.00+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run icx_1

Source file and lines	Collapse.hpp:81-83
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/Operators.hpp:307
/home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/loop/forall.hpp:59
/home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/pattern/detail/reduce.hpp:74,261-262
/home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/internal/Iterators.hpp:55,177
/home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/src/Kripke/Kernel/Population.cpp:58
/home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/Layout.hpp:55
/home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/tpl/raja/tpl/camp/include/camp/tuple.hpp:253
/home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/View.hpp:79
/home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/openmp/kernel/Collapse.hpp:81-83

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 31.83 to 4.83 cycles (6.59x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 12% of vector register length is used (average across all SSE/AVX instructions).

Details

4% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX loads are used in vector version.
3% of SSE/AVX stores are used in vector version.
0% of SSE/AVX addition or subtraction instructions are used in vector version.
9% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

__kmpc_critical@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/openmp/kernel/Collapse.hpp:81
__kmpc_for_static_fini@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/openmp/kernel/Collapse.hpp:81
__kmpc_for_static_init_8@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/openmp/kernel/Collapse.hpp:81
__kmpc_global_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/openmp/kernel/Collapse.hpp:81

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VZEROUPPER: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/openmp/kernel/Collapse.hpp:81

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 1 FP arithmetical operations:

1: addition or subtraction

The binary function is loading 216 bytes (27 double precision FP elements). The binary function is storing 240 bytes (30 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.00 FP operations per loaded or stored byte.

General properties

nb instructions	186
nb uops	191
loop length	1162
used x86 registers	15
used mmx registers	0
used xmm registers	2
used ymm registers	1
used zmm registers	0
nb stack references	27

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	31.83 cycles
front end	31.83 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	5.30	5.20	13.67	13.67	20.50	5.20	5.10	20.50	20.50	20.50	5.20	13.67
cycles	5.30	5.20	13.67	13.67	20.50	5.20	5.10	20.50	20.50	20.50	5.20	13.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	31.83
Dispatch	20.50
Overall L1	31.83

Vectorization ratios

INT

all	5%
load	0%
store	4%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	9%

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	4%
load	0%
store	3%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	9%

Vector efficiency ratios

INT

all	12%
load	12%
store	13%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 31.83 cycles. At this rate:

3% of peak load performance is reached (6.79 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (7.54 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 31.83 to 20.50 cycles (1.55x speedup).

ASM code

In the binary file, the address of the function is: 486260

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
AND $-0x20,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SUB $0x200,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOVL $0,0x94(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
LEA 0x38(%R8),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x38(%R8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
TEST %RAX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
CMOVNE %RAX,%RCX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	N/A
TEST %R9,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JS 486580 <_ZNK14PopulationSdomclIN6Kripke11ArchLayoutTINS1_12ArchT_OpenMPENS1_11LayoutT_DGZEEEEEvT_NS1_6SdomIdERKNS1_4Core3SetESB_SB_RNS8_5FieldIdJNS1_9DirectionENS1_5GroupENS1_4ZoneEEEERNSC_IdJSD_EEERNSC_IdJSF_EEEPd.extracted+0x320>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RCX,0xc8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV (%R8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,0x18(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x10(%R8),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x20(%R8),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x28(%R8),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x70(%R8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,0x10(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x90(%R8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,0x28(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x98(%R8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,0x38(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xd8(%R8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,0x40(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x100(%R8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,0x20(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD 0x40(%R8),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD %XMM0,0x8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV (%RDI),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOVQ $0,0xb8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %R9,0xb0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVQ $0x1,0x138(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA 0x140(%RSP),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA 0xd847c(%RIP),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA 0x9c(%RSP),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA 0xc0(%RSP),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA 0xb8(%RSP),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %ESI,0x98(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RAX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
CALL 403140 <__kmpc_for_static_init_8@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
ADD $0x20,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0xb8(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0xb0(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,0x88(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CMP %RCX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JA 4865c0 <_ZNK14PopulationSdomclIN6Kripke11ArchLayoutTINS1_12ArchT_OpenMPENS1_11LayoutT_DGZEEEEEvT_NS1_6SdomIdERKNS1_4Core3SetESB_SB_RNS8_5FieldIdJNS1_9DirectionENS1_5GroupENS1_4ZoneEEEERNSC_IdJSD_EEERNSC_IdJSF_EEEPd.extracted+0x360>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R12,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %R15,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RAX,0x30(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JLE 4865c0 <_ZNK14PopulationSdomclIN6Kripke11ArchLayoutTINS1_12ArchT_OpenMPENS1_11LayoutT_DGZEEEEEvT_NS1_6SdomIdERKNS1_4Core3SetESB_SB_RNS8_5FieldIdJNS1_9DirectionENS1_5GroupENS1_4ZoneEEEERNSC_IdJSD_EEERNSC_IdJSF_EEEPd.extracted+0x360>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x88(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA 0x1(%RAX),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
INC %RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RCX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV %RDX,0xf8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CMOVG %RDX,%RCX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	N/A
SUB %RAX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP $0x8,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
VMOVSD 0x8(%RSP),%XMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x20(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RBX,0xa0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RCX,0xc0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JAE 486640 <_ZNK14PopulationSdomclIN6Kripke11ArchLayoutTINS1_12ArchT_OpenMPENS1_11LayoutT_DGZEEEEEvT_NS1_6SdomIdERKNS1_4Core3SetESB_SB_RNS8_5FieldIdJNS1_9DirectionENS1_5GroupENS1_4ZoneEEEERNSC_IdJSD_EEERNSC_IdJSF_EEEPd.extracted+0x3e0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0xc0(%RSP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %R10,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x8,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
DEC %R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMP %RCX,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JB 4865c6 <_ZNK14PopulationSdomclIN6Kripke11ArchLayoutTINS1_12ArchT_OpenMPENS1_11LayoutT_DGZEEEEEvT_NS1_6SdomIdERKNS1_4Core3SetESB_SB_RNS8_5FieldIdJNS1_9DirectionENS1_5GroupENS1_4ZoneEEEERNSC_IdJSD_EEERNSC_IdJSF_EEEPd.extracted+0x366>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x30(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
AND $-0x4,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
LEA -0x1(%RSI),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x20(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%RAX,%R15,8),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x28(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (,%RAX,8),%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x38(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (,%RAX,8),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,0x8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JMP 486458 <_ZNK14PopulationSdomclIN6Kripke11ArchLayoutTINS1_12ArchT_OpenMPENS1_11LayoutT_DGZEEEEEvT_NS1_6SdomIdERKNS1_4Core3SetESB_SB_RNS8_5FieldIdJNS1_9DirectionENS1_5GroupENS1_4ZoneEEEERNSC_IdJSD_EEERNSC_IdJSF_EEEPd.extracted+0x1f8>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XCHG %AX,%AX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x28(%RBP),%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVSD 0x8(%RSP),%XMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD %XMM5,0x8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA 0xd81fd(%RIP),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x90(%RSP),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 403050 <__kmpc_for_static_fini@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
LEA 0xd8407(%RIP),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 403110 <__kmpc_global_thread_num@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
LEA 0xd8179(%RIP),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x5600e0,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV %EAX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R14,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 403390 <__kmpc_critical@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV 0xc8(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD 0x8(%RSP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VADDSD 0x10(%RAX),%XMM0,%XMM0	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VMOVSD %XMM0,0x10(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA 0xd8169(%RIP),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %EBX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R14,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA -0x28(%RBP),%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
JMP 403170 <__kmpc_end_critical@plt>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SHR $0x3,%RCX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
DEC %RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RCX,0xf0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x30(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x4,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
LEA -0x1(%R8),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RCX,0xd8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VPBROADCASTQ %RAX,%YMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVDQU %YMM0,0x140(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
LEA (%RDX,%R15,8),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,0xd0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R13,0xe8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R12,0xe0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R8,0x98(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JMP 48696b <_ZNK14PopulationSdomclIN6Kripke11ArchLayoutTINS1_12ArchT_OpenMPENS1_11LayoutT_DGZEEEEEvT_NS1_6SdomIdERKNS1_4Core3SetESB_SB_RNS8_5FieldIdJNS1_9DirectionENS1_5GroupENS1_4ZoneEEEERNSC_IdJSD_EEERNSC_IdJSF_EEEPd.extracted+0x70b>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run icx_1

Source file and lines	Collapse.hpp:81-83
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/Operators.hpp:307
/home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/loop/forall.hpp:59
/home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/pattern/detail/reduce.hpp:74,261-262
/home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/internal/Iterators.hpp:55,177
/home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/src/Kripke/Kernel/Population.cpp:58
/home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/Layout.hpp:55
/home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/tpl/raja/tpl/camp/include/camp/tuple.hpp:253
/home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/View.hpp:79
/home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/openmp/kernel/Collapse.hpp:81-83

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 31.83 to 4.83 cycles (6.59x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 12% of vector register length is used (average across all SSE/AVX instructions).

Details

4% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX loads are used in vector version.
3% of SSE/AVX stores are used in vector version.
0% of SSE/AVX addition or subtraction instructions are used in vector version.
9% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

Workaround

Recompile with -mprefer-vector-width=512

CALL instructions

Detected function call instructions.

Details

__kmpc_critical@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/openmp/kernel/Collapse.hpp:81
__kmpc_for_static_fini@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/openmp/kernel/Collapse.hpp:81
__kmpc_for_static_init_8@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/openmp/kernel/Collapse.hpp:81
__kmpc_global_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/openmp/kernel/Collapse.hpp:81

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VZEROUPPER: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/openmp/kernel/Collapse.hpp:81

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 1 FP arithmetical operations:

1: addition or subtraction

The binary function is loading 216 bytes (27 double precision FP elements). The binary function is storing 240 bytes (30 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.00 FP operations per loaded or stored byte.

General properties

nb instructions	186
nb uops	191
loop length	1162
used x86 registers	15
used mmx registers	0
used xmm registers	2
used ymm registers	1
used zmm registers	0
nb stack references	27

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	31.83 cycles
front end	31.83 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	5.30	5.20	13.67	13.67	20.50	5.20	5.10	20.50	20.50	20.50	5.20	13.67
cycles	5.30	5.20	13.67	13.67	20.50	5.20	5.10	20.50	20.50	20.50	5.20	13.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	31.83
Dispatch	20.50
Overall L1	31.83

Vectorization ratios

INT

all	5%
load	0%
store	4%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	9%

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	4%
load	0%
store	3%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	9%

Vector efficiency ratios

INT

all	12%
load	12%
store	13%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 31.83 cycles. At this rate:

3% of peak load performance is reached (6.79 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (7.54 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 486260

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
AND $-0x20,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SUB $0x200,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOVL $0,0x94(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
LEA 0x38(%R8),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x38(%R8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
TEST %RAX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
CMOVNE %RAX,%RCX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	N/A
TEST %R9,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JS 486580 <_ZNK14PopulationSdomclIN6Kripke11ArchLayoutTINS1_12ArchT_OpenMPENS1_11LayoutT_DGZEEEEEvT_NS1_6SdomIdERKNS1_4Core3SetESB_SB_RNS8_5FieldIdJNS1_9DirectionENS1_5GroupENS1_4ZoneEEEERNSC_IdJSD_EEERNSC_IdJSF_EEEPd.extracted+0x320>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RCX,0xc8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV (%R8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,0x18(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x10(%R8),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x20(%R8),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x28(%R8),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x70(%R8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,0x10(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x90(%R8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,0x28(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x98(%R8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,0x38(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xd8(%R8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,0x40(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x100(%R8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,0x20(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD 0x40(%R8),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD %XMM0,0x8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV (%RDI),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOVQ $0,0xb8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %R9,0xb0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVQ $0x1,0x138(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA 0x140(%RSP),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA 0xd847c(%RIP),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA 0x9c(%RSP),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA 0xc0(%RSP),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA 0xb8(%RSP),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %ESI,0x98(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RAX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
CALL 403140 <__kmpc_for_static_init_8@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
ADD $0x20,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0xb8(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0xb0(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,0x88(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CMP %RCX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JA 4865c0 <_ZNK14PopulationSdomclIN6Kripke11ArchLayoutTINS1_12ArchT_OpenMPENS1_11LayoutT_DGZEEEEEvT_NS1_6SdomIdERKNS1_4Core3SetESB_SB_RNS8_5FieldIdJNS1_9DirectionENS1_5GroupENS1_4ZoneEEEERNSC_IdJSD_EEERNSC_IdJSF_EEEPd.extracted+0x360>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R12,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %R15,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RAX,0x30(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JLE 4865c0 <_ZNK14PopulationSdomclIN6Kripke11ArchLayoutTINS1_12ArchT_OpenMPENS1_11LayoutT_DGZEEEEEvT_NS1_6SdomIdERKNS1_4Core3SetESB_SB_RNS8_5FieldIdJNS1_9DirectionENS1_5GroupENS1_4ZoneEEEERNSC_IdJSD_EEERNSC_IdJSF_EEEPd.extracted+0x360>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x88(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA 0x1(%RAX),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
INC %RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RCX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV %RDX,0xf8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CMOVG %RDX,%RCX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	N/A
SUB %RAX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP $0x8,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
VMOVSD 0x8(%RSP),%XMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x20(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RBX,0xa0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RCX,0xc0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JAE 486640 <_ZNK14PopulationSdomclIN6Kripke11ArchLayoutTINS1_12ArchT_OpenMPENS1_11LayoutT_DGZEEEEEvT_NS1_6SdomIdERKNS1_4Core3SetESB_SB_RNS8_5FieldIdJNS1_9DirectionENS1_5GroupENS1_4ZoneEEEERNSC_IdJSD_EEERNSC_IdJSF_EEEPd.extracted+0x3e0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0xc0(%RSP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %R10,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x8,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
DEC %R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMP %RCX,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JB 4865c6 <_ZNK14PopulationSdomclIN6Kripke11ArchLayoutTINS1_12ArchT_OpenMPENS1_11LayoutT_DGZEEEEEvT_NS1_6SdomIdERKNS1_4Core3SetESB_SB_RNS8_5FieldIdJNS1_9DirectionENS1_5GroupENS1_4ZoneEEEERNSC_IdJSD_EEERNSC_IdJSF_EEEPd.extracted+0x366>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x30(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
AND $-0x4,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
LEA -0x1(%RSI),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x20(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%RAX,%R15,8),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x28(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (,%RAX,8),%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x38(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (,%RAX,8),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,0x8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JMP 486458 <_ZNK14PopulationSdomclIN6Kripke11ArchLayoutTINS1_12ArchT_OpenMPENS1_11LayoutT_DGZEEEEEvT_NS1_6SdomIdERKNS1_4Core3SetESB_SB_RNS8_5FieldIdJNS1_9DirectionENS1_5GroupENS1_4ZoneEEEERNSC_IdJSD_EEERNSC_IdJSF_EEEPd.extracted+0x1f8>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XCHG %AX,%AX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x28(%RBP),%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVSD 0x8(%RSP),%XMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD %XMM5,0x8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA 0xd81fd(%RIP),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x90(%RSP),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 403050 <__kmpc_for_static_fini@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
LEA 0xd8407(%RIP),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 403110 <__kmpc_global_thread_num@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
LEA 0xd8179(%RIP),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x5600e0,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV %EAX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R14,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 403390 <__kmpc_critical@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV 0xc8(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD 0x8(%RSP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VADDSD 0x10(%RAX),%XMM0,%XMM0	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VMOVSD %XMM0,0x10(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA 0xd8169(%RIP),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %EBX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R14,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA -0x28(%RBP),%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
JMP 403170 <__kmpc_end_critical@plt>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SHR $0x3,%RCX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
DEC %RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RCX,0xf0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x30(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x4,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
LEA -0x1(%R8),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RCX,0xd8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VPBROADCASTQ %RAX,%YMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVDQU %YMM0,0x140(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
LEA (%RDX,%R15,8),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,0xd0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R13,0xe8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R12,0xe0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R8,0x98(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JMP 48696b <_ZNK14PopulationSdomclIN6Kripke11ArchLayoutTINS1_12ArchT_OpenMPENS1_11LayoutT_DGZEEEEEvT_NS1_6SdomIdERKNS1_4Core3SetESB_SB_RNS8_5FieldIdJNS1_9DirectionENS1_5GroupENS1_4ZoneEEEERNSC_IdJSD_EEERNSC_IdJSF_EEEPd.extracted+0x70b>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

Name	Coverage (%)	Time (s)
▼void PopulationSdom::operator() >(Kripke::ArchLayoutT, Kripke::SdomId, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Set const&, K...–	0.23	0.03
▼Loop 1123 - Collapse.hpp:81-83 - exec–	0.00	0.00
○Loop 1124 - forall.hpp:59-59 - exec	0.22	0.02
▼Loop 1121 - Collapse.hpp:81-83 - exec–	0.00	0.00
○Loop 1122 - forall.hpp:59-59 - exec	0.00	0.01
○Loop 1120 - forall.hpp:59-59 - exec	0.00	0.00

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512-bits vectorization

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Type of elements and instruction set

Matching between your function (in the source code) and the binary function

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ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code