OV - exec - Function void Kripke::DispatchHelper<Kripke::ArchT_OpenMP>::operator()<Kripke::LayoutT_DGZ, LTimesSdom, Kripke::SdomId&, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Field<double, Kripke::Direction, Kripke::Group, Kripke::Zone>&, Kripke::Core::Field<double, Kripke::Moment, Kripke::Group, Kripke::Zone>&, Kripke::Core::Field<double, Kripke::Moment, Kripke::Direction>&>(Kripke::LayoutT_DGZ, LTimesSdom const&, Kripke::SdomId&, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Field<double, Kripke::Direction, Kripke::Group, Kripke::Zone>&, Kripke::Core::Field<double, Kripke::Moment, Kripke::Group, Kripke::Zone>&, Kripke::Core::Field<double, Kripke::Moment, Kripke::Direction>&) const [clone .extracted]

	Function: void Kripke::DispatchHelper<Kripke::ArchT_OpenMP>::operator()<Kripke::LayoutT_DGZ, LTimesS ...	Module: exec	Source: Collapse.hpp:81-83 [...]	Coverage (incl. loops): 4.18% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/loop/forall.hpp: 59 - 59

--------------------------------------------------------------------------------

59:   for (decltype(distance_it) i = 0; i < distance_it; ++i) {

/home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/src/Kripke/Kernel/LTimes.cpp: 62 - 62

--------------------------------------------------------------------------------

62:            phi(nm,g,z) += ell(nm, d) * psi(d, g, z);

/home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/internal/Iterators.hpp: 55 - 177

--------------------------------------------------------------------------------

55:       : val(rhs.val)

[...]

177:     return value_type(val + rhs);

/home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/Layout.hpp: 55 - 55

--------------------------------------------------------------------------------

55:     return a * b;

/home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/View.hpp: 79 - 110

--------------------------------------------------------------------------------

79:       : layout(V.layout), data(V.data)

[...]

110:     return data[idx];

/home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/openmp/kernel/Collapse.hpp: 81 - 83

--------------------------------------------------------------------------------

81: #pragma omp parallel for private(i0, i1) firstprivate(privatizer) \

82:     RAJA_COLLAPSE(2)

83:     for (i0 = 0; i0 < l0; ++i0) {

0x4779e0 PUSH	%RBP

0x4779e1 MOV	%RSP,%RBP

0x4779e4 PUSH	%R15

0x4779e6 PUSH	%R14

0x4779e8 PUSH	%R13

0x4779ea PUSH	%R12

0x4779ec PUSH	%RBX

0x4779ed AND	$-0x20,%RSP

0x4779f1 SUB	$0x240,%RSP

0x4779f8 MOV	%RDX,%R12

0x4779fb MOVL	$0,0x74(%RSP)

0x477a03 MOV	(%R8),%RAX

0x477a06 MOV	%RAX,0x178(%RSP)

0x477a0e MOV	0x10(%R8),%R13

0x477a12 MOV	0x18(%R8),%R15

0x477a16 MOV	0x20(%R8),%RAX

0x477a1a MOV	%RAX,0x170(%RSP)

0x477a22 MOV	0x30(%R8),%RAX

0x477a26 MOV	%RAX,0x98(%RSP)

0x477a2e MOV	0x38(%R8),%RAX

0x477a32 MOV	%RAX,0x90(%RSP)

0x477a3a MOV	0x60(%R8),%RAX

0x477a3e MOV	%RAX,0x168(%RSP)

0x477a46 MOV	0x68(%R8),%RAX

0x477a4a MOV	%RAX,0x160(%RSP)

0x477a52 MOV	0xa8(%R8),%RAX

0x477a59 MOV	%RAX,0x68(%RSP)

0x477a5e MOV	(%RDI),%ESI

0x477a60 MOV	%R9,0xf0(%RSP)

0x477a68 MOV	0xc8(%R8),%RAX

0x477a6f MOV	%RAX,0x10(%RSP)

0x477a74 MOV	0xf0(%R8),%RBX

0x477a7b MOV	0x110(%R8),%RAX

0x477a82 MOV	%RAX,(%RSP)

0x477a86 MOV	0x118(%R8),%RAX

0x477a8d MOV	%RAX,0x88(%RSP)

0x477a95 MOV	0x158(%R8),%R14

0x477a9c MOVQ	$0,0xf8(%RSP)

0x477aa8 MOVQ	$0x1,0x1d8(%RSP)

0x477ab4 SUB	$0x8,%RSP

0x477ab8 LEA	0x1e0(%RSP),%RAX

0x477ac0 LEA	0xe6a69(%RIP),%RDI

0x477ac7 LEA	0x7c(%RSP),%RCX

0x477acc LEA	0x100(%RSP),%R8

0x477ad4 LEA	0xf8(%RSP),%R9

0x477adc MOV	%ESI,0x78(%RSP)

0x477ae0 MOV	$0x22,%EDX

0x477ae5 PUSH	$0x1

0x477ae7 PUSH	$0x1

0x477ae9 PUSH	%RAX

0x477aea CALL	403140 <__kmpc_for_static_init_8@plt>

0x477aef ADD	$0x20,%RSP

0x477af3 MOV	0xf8(%RSP),%RCX

0x477afb MOV	0xf0(%RSP),%RAX

0x477b03 MOV	%RCX,0x80(%RSP)

0x477b0b CMP	%RAX,%RCX

0x477b0e JA	478640

0x477b14 MOV	%R15,%RCX

0x477b17 SUB	%R13,%RCX

0x477b1a MOV	%RCX,0x48(%RSP)

0x477b1f JLE	478640

0x477b25 MOV	0x80(%RSP),%RDX

0x477b2d LEA	0x1(%RDX),%RCX

0x477b31 INC	%RAX

0x477b34 CMP	%RAX,%RCX

0x477b37 CMOVG	%RCX,%RAX

0x477b3b NOT	%RDX

0x477b3e ADD	%RAX,%RDX

0x477b41 MOV	%RDX,0x158(%RSP)

0x477b49 MOV	%R13,%RDI

0x477b4c MOV	%R13,%RAX

0x477b4f MOV	(%RSP),%R9

0x477b53 IMUL	%R9,%RAX

0x477b57 MOV	%RAX,0x60(%RSP)

0x477b5c MOV	%R9,%RAX

0x477b5f SAR	$0x3f,%RAX

0x477b63 ANDN	%R9,%RAX,%RAX

0x477b68 MOV	%R13,%RSI

0x477b6b NOT	%RSI

0x477b6e MOV	%R15,%RCX

0x477b71 IMUL	%RAX,%RCX

0x477b75 MOV	%RCX,0x148(%RSP)

0x477b7d IMUL	%RSI,%RAX

0x477b81 MOV	%RAX,0x150(%RSP)

0x477b89 XOR	%R13D,%R13D

0x477b8c TEST	%R9,%R9

0x477b8f MOV	$0,%R10D

0x477b95 CMOVS	%R9,%R10

0x477b99 MOV	%R15,%RAX

0x477b9c IMUL	%R10,%RAX

0x477ba0 MOV	%RAX,0x8(%RSP)

0x477ba5 IMUL	%RSI,%R10

0x477ba9 MOV	%RDI,%RCX

0x477bac MOV	0x10(%RSP),%R8

0x477bb1 IMUL	%R8,%RCX

0x477bb5 MOV	%RCX,0x138(%RSP)

0x477bbd MOV	%R8,%RCX

0x477bc0 SAR	$0x3f,%RCX

0x477bc4 ANDN	%R8,%RCX,%RCX

0x477bc9 MOV	%R15,%R11

0x477bcc IMUL	%RCX,%R11

0x477bd0 IMUL	%RSI,%RCX

0x477bd4 TEST	%R8,%R8

0x477bd7 MOV	%R15,%RAX

0x477bda MOV	$0,%R15D

0x477be0 CMOVS	%R8,%R15

0x477be4 MOV	%RAX,%RDX

0x477be7 IMUL	%R15,%RDX

0x477beb IMUL	%RSI,%R15

0x477bef ADD	%RDX,%R15

0x477bf2 MOV	%R15,0x128(%RSP)

0x477bfa ADD	%RAX,%RSI

0x477bfd MOV	%RSI,0x120(%RSP)

0x477c05 MOV	0x90(%RSP),%RSI

0x477c0d MOV	0x98(%RSP),%RDX

0x477c15 SUB	%RDX,%RSI

0x477c18 ADD	0x8(%RSP),%R10

0x477c1d MOV	%R10,0x140(%RSP)

0x477c25 MOV	0x48(%RSP),%R10

0x477c2a MOV	%R10,%R15

0x477c2d SHR	$0x3,%R15

0x477c31 DEC	%R15

0x477c34 MOV	%R15,0x1d0(%RSP)

0x477c3c ADD	%R11,%RCX

0x477c3f MOV	%RCX,0x130(%RSP)

0x477c47 LEA	(,%R8,8),%RAX

0x477c4f MOV	%RAX,0x1b8(%RSP)

0x477c57 SUB	%R8,%RAX

0x477c5a MOV	%RAX,0x1b0(%RSP)

0x477c62 MOV	%RSI,%RCX

0x477c65 AND	$-0x4,%RCX

0x477c69 LEA	(,%R9,8),%RAX

0x477c71 MOV	%RAX,0x20(%RSP)

0x477c76 SUB	%R9,%RAX

0x477c79 MOV	%RAX,0xc8(%RSP)

0x477c81 VPBROADCASTQ	%RSI,%YMM0

0x477c87 VMOVDQU	%YMM0,0x1e0(%RSP)

0x477c90 MOV	%R10,%R15

0x477c93 AND	$-0x8,%R15

0x477c97 LEA	(,%RDX,8),%RAX

0x477c9f MOV	0x60(%RSP),%R11

0x477ca4 LEA	(%RAX,%R11,8),%R11

0x477ca8 ADD	%R14,%R11

0x477cab MOV	%R11,0x78(%RSP)

0x477cb0 MOV	%R9,%R11

0x477cb3 SAL	$0x6,%R11

0x477cb7 MOV	%R15,0x118(%RSP)

0x477cbf ADD	%R15,%RDI

0x477cc2 IMUL	%R9,%RDI

0x477cc6 LEA	(%RAX,%RDI,8),%RAX

0x477cca ADD	%R14,%RAX

0x477ccd MOV	%RAX,0x100(%RSP)

0x477cd5 ADD	%RDX,%RDI

0x477cd8 MOV	%RDI,0x108(%RSP)

0x477ce0 LEA	(%R8,%R8,1),%RAX

0x477ce4 LEA	(%R8,%R8,2),%RDX

0x477ce8 MOV	%RDX,0x1a0(%RSP)

0x477cf0 LEA	(,%R8,4),%RDX

0x477cf8 MOV	%RDX,0x198(%RSP)

0x477d00 LEA	(%R8,%R8,4),%RDX

0x477d04 MOV	%RDX,0x190(%RSP)

0x477d0c MOV	%R11,%R8

0x477d0f MOV	%RAX,0x1a8(%RSP)

0x477d17 LEA	(%RAX,%RAX,2),%RAX

0x477d1b MOV	%RAX,0x188(%RSP)

0x477d23 MOV	%RCX,0x28(%RSP)

0x477d28 LEA	-0x1(%RCX),%RAX

0x477d2c MOV	%RAX,0xe0(%RSP)

0x477d34 LEA	(%R9,%R9,1),%RAX

0x477d38 MOV	%RAX,0xc0(%RSP)

0x477d40 LEA	(%R9,%R9,2),%RCX

0x477d44 MOV	%RCX,0xb8(%RSP)

0x477d4c LEA	(,%R9,4),%RCX

0x477d54 MOV	%RCX,0xb0(%RSP)

0x477d5c LEA	(%R9,%R9,4),%RDX

0x477d60 LEA	(%RAX,%RAX,2),%RAX

0x477d64 MOV	%RAX,0xa8(%RSP)

0x477d6c LEA	-0x1(%R10),%RAX

0x477d70 MOV	%RAX,0x1c8(%RSP)

0x477d78 MOV	0x88(%RSP),%RAX

0x477d80 LEA	(,%RAX,8),%RAX

0x477d88 MOV	%RAX,0x38(%RSP)

0x477d8d MOV	%R12,0x40(%RSP)

0x477d92 MOV	%RSI,0xd8(%RSP)

0x477d9a MOV	%R11,0xa0(%RSP)

0x477da2 MOV	%RBX,0x180(%RSP)

0x477daa MOV	%RDX,0x110(%RSP)

0x477db2 JMP	477ddc

0x477db4 NOPW	%CS:(%RAX,%RAX,1)

(956) 0x477dc0 MOV	0x58(%RSP),%R13

(956) 0x477dc5 MOV	0x40(%RSP),%R12

(956) 0x477dca CMP	0x158(%RSP),%R13

(956) 0x477dd2 LEA	0x1(%R13),%R13

(956) 0x477dd6 JE	478640

(956) 0x477ddc MOV	0x80(%RSP),%RAX

(956) 0x477de4 ADD	%R13,%RAX

(956) 0x477de7 MOV	%RAX,%RCX

(956) 0x477dea OR	%R12,%RCX

(956) 0x477ded SHR	$0x20,%RCX

(956) 0x477df1 MOV	%R13,0x58(%RSP)

(956) 0x477df6 MOV	%R14,%RDI

(956) 0x477df9 JE	477e40

(956) 0x477dfb CQTO

(956) 0x477dfd IDIV	%R12

(956) 0x477e00 JMP	477e45

0x477e02 NOPW	%CS:(%RAX,%RAX,1)

0x477e11 NOPW	%CS:(%RAX,%RAX,1)

0x477e20 NOPW	%CS:(%RAX,%RAX,1)

0x477e2f NOPW	%CS:(%RAX,%RAX,1)

0x477e3e XCHG	%AX,%AX

(956) 0x477e40 XOR	%EDX,%EDX

(956) 0x477e42 DIV	%R12D

(956) 0x477e45 MOV	0x10(%RSP),%R13

(956) 0x477e4a ADD	0x178(%RSP),%RAX

(956) 0x477e52 ADD	0x170(%RSP),%RDX

(956) 0x477e5a MOV	0x88(%RSP),%R8

(956) 0x477e62 IMUL	%RDX,%R8

(956) 0x477e66 MOV	0x90(%RSP),%R15

(956) 0x477e6e MOV	0x60(%RSP),%RCX

(956) 0x477e73 ADD	%R15,%RCX

(956) 0x477e76 ADD	0x150(%RSP),%RCX

(956) 0x477e7e ADD	0x148(%RSP),%RCX

(956) 0x477e86 ADD	%R8,%RCX

(956) 0x477e89 LEA	-0x8(%RDI,%RCX,8),%R14

(956) 0x477e8e MOV	0x160(%RSP),%RCX

(956) 0x477e96 MOV	%RDX,0x50(%RSP)

(956) 0x477e9b IMUL	%RDX,%RCX

(956) 0x477e9f MOV	0x98(%RSP),%R11

(956) 0x477ea7 LEA	(%R11,%RCX,1),%R9

(956) 0x477eab MOV	0x168(%RSP),%R10

(956) 0x477eb3 IMUL	%RAX,%R10

(956) 0x477eb7 ADD	%R10,%R9

(956) 0x477eba MOV	0x68(%RSP),%R12

(956) 0x477ebf MOV	%R9,0xe8(%RSP)

(956) 0x477ec7 LEA	(%R12,%R9,8),%R9

(956) 0x477ecb CMP	%R9,%R14

(956) 0x477ece SETAEB	0x8(%RSP)

(956) 0x477ed3 ADD	%R15,%RCX

(956) 0x477ed6 ADD	%R10,%RCX

(956) 0x477ed9 LEA	-0x8(%R12,%RCX,8),%R10

(956) 0x477ede MOV	%RDI,%RDX

(956) 0x477ee1 MOV	0x60(%RSP),%RCX

(956) 0x477ee6 LEA	(%R11,%RCX,1),%R14

(956) 0x477eea MOV	%R8,0x18(%RSP)

(956) 0x477eef ADD	%R8,%R14

(956) 0x477ef2 MOV	0x140(%RSP),%RCX

(956) 0x477efa ADD	%R14,%RCX

(956) 0x477efd LEA	(%RDI,%RCX,8),%RCX

(956) 0x477f01 CMP	%RCX,%R10

(956) 0x477f04 SETAE	%R12B

(956) 0x477f08 ADD	0x138(%RSP),%RAX

(956) 0x477f10 MOV	0x130(%RSP),%RCX

(956) 0x477f18 ADD	%RAX,%RCX

(956) 0x477f1b LEA	(%RBX,%RCX,8),%RCX

(956) 0x477f1f CMP	%R9,%RCX

(956) 0x477f22 SETB	%CL

(956) 0x477f25 MOV	0x128(%RSP),%R11

(956) 0x477f2d MOV	%RAX,0x30(%RSP)

(956) 0x477f32 ADD	%RAX,%R11

(956) 0x477f35 LEA	(%RBX,%R11,8),%R11

(956) 0x477f39 CMP	%R11,%R10

(956) 0x477f3c SETB	%R10B

(956) 0x477f40 TEST	%R12B,0x8(%RSP)

(956) 0x477f45 JNE	478100

(956) 0x477f4b OR	%R10B,%CL

(956) 0x477f4e JE	478100

(956) 0x477f54 CMPQ	$0x8,0x48(%RSP)

(956) 0x477f5a MOV	0x110(%RSP),%RDX

(956) 0x477f62 MOV	0xa0(%RSP),%R8

(956) 0x477f6a JAE	478200

(956) 0x477f70 MOV	(%RSP),%R15

(956) 0x477f74 MOV	%RDI,%R14

(956) 0x477f77 MOV	0x118(%RSP),%RAX

(956) 0x477f7f CMP	0x48(%RSP),%RAX

(956) 0x477f84 JAE	4781c0

(956) 0x477f8a MOV	0x50(%RSP),%RDX

(956) 0x477f8f IMUL	0x38(%RSP),%RDX

(956) 0x477f95 ADD	0x100(%RSP),%RDX

(956) 0x477f9d MOV	0x18(%RSP),%RCX

(956) 0x477fa2 ADD	0x108(%RSP),%RCX

(956) 0x477faa MOV	%RCX,0x18(%RSP)

(956) 0x477faf JMP	477fdc

0x477fb1 NOPW	%CS:(%RAX,%RAX,1)

  (959) 0x477fc0 ADD	0x20(%RSP),%RDX

  (959) 0x477fc5 ADD	%R15,0x18(%RSP)

  (959) 0x477fca CMP	0x1c8(%RSP),%RAX

  (959) 0x477fd2 LEA	0x1(%RAX),%RAX

  (959) 0x477fd6 JE	4781c0

  (959) 0x477fdc TEST	%RSI,%RSI

  (959) 0x477fdf JLE	477fc0

  (959) 0x477fe1 MOV	%R13,%RCX

  (959) 0x477fe4 IMUL	%RAX,%RCX

  (959) 0x477fe8 ADD	0x30(%RSP),%RCX

  (959) 0x477fed VMOVSD	(%RBX,%RCX,8),%XMM18

  (959) 0x477ff4 CMPQ	$0,0x28(%RSP)

  (959) 0x477ffa JE	478080

  (959) 0x478000 VBROADCASTSD	%XMM18,%YMM0

  (959) 0x478006 XOR	%ECX,%ECX

  (959) 0x478008 MOV	0xe0(%RSP),%RSI

    (961) 0x478010 VMOVUPD	(%RDX,%RCX,8),%YMM1

    (961) 0x478015 VFMADD213PD	(%R9,%RCX,8),%YMM0,%YMM1

    (961) 0x47801b VMOVUPD	%YMM1,(%R9,%RCX,8)

    (961) 0x478021 ADD	$0x4,%RCX

    (961) 0x478025 CMP	%RSI,%RCX

    (961) 0x478028 JLE	478010

  (959) 0x47802a MOV	0x28(%RSP),%RCX

  (959) 0x47802f MOV	%RCX,%R11

  (959) 0x478032 MOV	0xd8(%RSP),%RSI

  (959) 0x47803a CMP	%RCX,%RSI

  (959) 0x47803d JE	477fc0

  (959) 0x47803f JMP	478083

0x478041 NOPW	%CS:(%RAX,%RAX,1)

0x478050 NOPW	%CS:(%RAX,%RAX,1)

0x47805f NOPW	%CS:(%RAX,%RAX,1)

0x47806e NOPW	%CS:(%RAX,%RAX,1)

0x47807d NOPL	(%RAX)

  (959) 0x478080 XOR	%R11D,%R11D

  (959) 0x478083 MOV	%RSI,%RCX

  (959) 0x478086 SUB	%R11,%RCX

  (959) 0x478089 MOV	0xe8(%RSP),%R10

  (959) 0x478091 ADD	%R11,%R10

  (959) 0x478094 MOV	0x68(%RSP),%R15

  (959) 0x478099 LEA	(%R15,%R10,8),%R10

  (959) 0x47809d MOV	(%RSP),%R15

  (959) 0x4780a1 ADD	0x18(%RSP),%R11

  (959) 0x4780a6 LEA	(%R14,%R11,8),%R11

  (959) 0x4780aa XOR	%R12D,%R12D

  (959) 0x4780ad NOPL	(%RAX)

    (960) 0x4780b0 VMOVSD	(%R11,%R12,8),%XMM0

    (960) 0x4780b6 VFMADD213SD	(%R10,%R12,8),%XMM18,%XMM0

    (960) 0x4780bd VMOVSD	%XMM0,(%R10,%R12,8)

    (960) 0x4780c3 INC	%R12

    (960) 0x4780c6 CMP	%R12,%RCX

    (960) 0x4780c9 JNE	4780b0

  (959) 0x4780cb JMP	477fc0

0x4780d0 NOPW	%CS:(%RAX,%RAX,1)

0x4780df NOPW	%CS:(%RAX,%RAX,1)

0x4780ee NOPW	%CS:(%RAX,%RAX,1)

0x4780fd NOPL	(%RAX)

(956) 0x478100 MOV	0x50(%RSP),%RDX

(956) 0x478105 IMUL	0x38(%RSP),%RDX

(956) 0x47810b ADD	0x78(%RSP),%RDX

(956) 0x478110 XOR	%EAX,%EAX

(956) 0x478112 MOV	0x120(%RSP),%R11

(956) 0x47811a MOV	0x20(%RSP),%R15

(956) 0x47811f MOV	%RDI,%R14

(956) 0x478122 JMP	478150

0x478124 NOPW	%CS:(%RAX,%RAX,1)

0x478133 NOPW	%CS:(%RAX,%RAX,1)

  (957) 0x478140 ADD	%R15,%RDX

  (957) 0x478143 CMP	%R11,%RAX

  (957) 0x478146 LEA	0x1(%RAX),%RAX

  (957) 0x47814a JE	477dc0

  (957) 0x478150 TEST	%RSI,%RSI

  (957) 0x478153 JLE	478140

  (957) 0x478155 MOV	%R13,%RCX

  (957) 0x478158 IMUL	%RAX,%RCX

  (957) 0x47815c ADD	0x30(%RSP),%RCX

  (957) 0x478161 XOR	%R10D,%R10D

  (957) 0x478164 NOPW	%CS:(%RAX,%RAX,1)

    (958) 0x478170 VMOVSD	(%RDX,%R10,8),%XMM0

    (958) 0x478176 VMOVSD	(%RBX,%RCX,8),%XMM1

    (958) 0x47817b VFMADD213SD	(%R9,%R10,8),%XMM0,%XMM1

    (958) 0x478181 VMOVSD	%XMM1,(%R9,%R10,8)

    (958) 0x478187 INC	%R10

    (958) 0x47818a CMP	%R10,%RSI

    (958) 0x47818d JNE	478170

  (957) 0x47818f JMP	478140

0x478191 NOPW	%CS:(%RAX,%RAX,1)

0x4781a0 NOPW	%CS:(%RAX,%RAX,1)

0x4781af NOPW	%CS:(%RAX,%RAX,1)

0x4781be XCHG	%AX,%AX

(956) 0x4781c0 MOV	0x40(%RSP),%R12

(956) 0x4781c5 MOV	0x58(%RSP),%R13

(956) 0x4781ca CMP	0x158(%RSP),%R13

(956) 0x4781d2 LEA	0x1(%R13),%R13

(956) 0x4781d6 JNE	477ddc

0x4781dc JMP	478640

0x4781e1 NOPW	%CS:(%RAX,%RAX,1)

0x4781f0 NOPW	%CS:(%RAX,%RAX,1)

0x4781ff NOP

(956) 0x478200 MOV	%R14,0xd0(%RSP)

(956) 0x478208 MOV	0x38(%RSP),%RAX

(956) 0x47820d IMUL	0x50(%RSP),%RAX

(956) 0x478213 ADD	0x78(%RSP),%RAX

(956) 0x478218 XOR	%ECX,%ECX

(956) 0x47821a MOV	(%RSP),%R15

(956) 0x47821e MOV	0x30(%RSP),%R12

(956) 0x478223 MOV	%RDI,%R14

(956) 0x478226 MOV	%RAX,%RDI

(956) 0x478229 JMP	478255

0x47822b NOPW	%CS:(%RAX,%RAX,1)

0x47823a NOPW	(%RAX,%RAX,1)

  (962) 0x478240 ADD	%R8,%RDI

  (962) 0x478243 CMP	0x1d0(%RSP),%RCX

  (962) 0x47824b LEA	0x1(%RCX),%RCX

  (962) 0x47824f JE	477f77

  (962) 0x478255 TEST	%RSI,%RSI

  (962) 0x478258 JLE	478240

  (962) 0x47825a MOV	0x1b8(%RSP),%R10

  (962) 0x478262 IMUL	%RCX,%R10

  (962) 0x478266 ADD	%R12,%R10

  (962) 0x478269 LEA	(%R10,%R13,1),%R11

  (962) 0x47826d VMOVSD	(%RBX,%R11,8),%XMM24

  (962) 0x478274 MOV	0x1a8(%RSP),%R11

  (962) 0x47827c ADD	%R10,%R11

  (962) 0x47827f VMOVSD	(%RBX,%R11,8),%XMM23

  (962) 0x478286 MOV	0x1a0(%RSP),%R11

  (962) 0x47828e LEA	(%R10,%R11,1),%R11

  (962) 0x478292 VMOVSD	(%RBX,%R11,8),%XMM22

  (962) 0x478299 MOV	0x198(%RSP),%R11

  (962) 0x4782a1 LEA	(%R10,%R11,1),%R11

  (962) 0x4782a5 VMOVSD	(%RBX,%R11,8),%XMM21

  (962) 0x4782ac MOV	0x190(%RSP),%R11

  (962) 0x4782b4 ADD	%R10,%R11

  (962) 0x4782b7 VMOVSD	(%RBX,%R11,8),%XMM20

  (962) 0x4782be MOV	0x188(%RSP),%R11

  (962) 0x4782c6 ADD	%R10,%R11

  (962) 0x4782c9 VMOVSD	(%RBX,%R11,8),%XMM19

  (962) 0x4782d0 VMOVSD	(%RBX,%R10,8),%XMM25

  (962) 0x4782d7 MOV	0x1b0(%RSP),%R11

  (962) 0x4782df ADD	%R11,%R10

  (962) 0x4782e2 VMOVSD	(%RBX,%R10,8),%XMM18

  (962) 0x4782e9 CMPQ	$0,0x28(%RSP)

  (962) 0x4782ef JE	478440

  (962) 0x4782f5 MOV	0x20(%RSP),%R10

  (962) 0x4782fa MOV	%RCX,0x1c0(%RSP)

  (962) 0x478302 IMUL	%RCX,%R10

  (962) 0x478306 VBROADCASTSD	%XMM25,%YMM26

  (962) 0x47830c VBROADCASTSD	%XMM24,%YMM27

  (962) 0x478312 VBROADCASTSD	%XMM23,%YMM28

  (962) 0x478318 VBROADCASTSD	%XMM22,%YMM29

  (962) 0x47831e VBROADCASTSD	%XMM21,%YMM30

  (962) 0x478324 VBROADCASTSD	%XMM20,%YMM31

  (962) 0x47832a VBROADCASTSD	%XMM19,%YMM1

  (962) 0x478330 VBROADCASTSD	%XMM18,%YMM0

  (962) 0x478336 XOR	%R11D,%R11D

  (962) 0x478339 MOV	0xc8(%RSP),%R8

  (962) 0x478341 MOV	0xc0(%RSP),%RCX

  (962) 0x478349 MOV	0xb8(%RSP),%RAX

  (962) 0x478351 MOV	%RDI,0x8(%RSP)

  (962) 0x478356 MOV	0xb0(%RSP),%RDI

  (962) 0x47835e MOV	0xa8(%RSP),%RBX

  (962) 0x478366 MOV	0xe0(%RSP),%RSI

  (962) 0x47836e MOV	0xd0(%RSP),%R12

  (962) 0x478376 NOPW	%CS:(%RAX,%RAX,1)

    (963) 0x478380 LEA	(%R10,%R11,1),%R13

    (963) 0x478384 ADD	%R12,%R13

    (963) 0x478387 MOV	0x8(%RSP),%R15

    (963) 0x47838c VMOVUPD	(%R15,%R11,8),%YMM2

    (963) 0x478392 VFMADD213PD	(%R9,%R11,8),%YMM26,%YMM2

    (963) 0x478399 MOV	(%RSP),%R15

    (963) 0x47839d ADD	%R13,%R15

    (963) 0x4783a0 VFMADD231PD	(%R14,%R15,8),%YMM27,%YMM2

    (963) 0x4783a7 LEA	(%R13,%RCX,1),%R15

    (963) 0x4783ac VFMADD231PD	(%R14,%R15,8),%YMM28,%YMM2

    (963) 0x4783b3 LEA	(%R13,%RAX,1),%R15

    (963) 0x4783b8 VFMADD231PD	(%R14,%R15,8),%YMM29,%YMM2

    (963) 0x4783bf LEA	(%R13,%RDI,1),%R15

    (963) 0x4783c4 VFMADD231PD	(%R14,%R15,8),%YMM30,%YMM2

    (963) 0x4783cb LEA	(%R13,%RDX,1),%R15

    (963) 0x4783d0 VFMADD231PD	(%R14,%R15,8),%YMM31,%YMM2

    (963) 0x4783d7 LEA	(%R13,%RBX,1),%R15

    (963) 0x4783dc VFMADD231PD	(%R14,%R15,8),%YMM1,%YMM2

    (963) 0x4783e2 MOV	(%RSP),%R15

    (963) 0x4783e6 ADD	%R8,%R13

    (963) 0x4783e9 VFMADD231PD	(%R14,%R13,8),%YMM0,%YMM2

    (963) 0x4783ef VMOVUPD	%YMM2,(%R9,%R11,8)

    (963) 0x4783f5 ADD	$0x4,%R11

    (963) 0x4783f9 CMP	%RSI,%R11

    (963) 0x4783fc JLE	478380

  (962) 0x4783fe MOV	0x28(%RSP),%R10

  (962) 0x478403 MOV	%R10,%R11

  (962) 0x478406 MOV	0xd8(%RSP),%RSI

  (962) 0x47840e CMP	%R10,%RSI

  (962) 0x478411 MOV	0x10(%RSP),%R13

  (962) 0x478416 MOV	0xa0(%RSP),%R8

  (962) 0x47841e MOV	0x180(%RSP),%RBX

  (962) 0x478426 MOV	0x30(%RSP),%R12

  (962) 0x47842b MOV	0x8(%RSP),%RDI

  (962) 0x478430 MOV	0x1c0(%RSP),%RCX

  (962) 0x478438 JE	478240

  (962) 0x47843e JMP	478443

  (962) 0x478440 XOR	%R11D,%R11D

  (962) 0x478443 VPBROADCASTQ	%R11,%YMM0

  (962) 0x478449 VMOVDQU	0x1e0(%RSP),%YMM1

  (962) 0x478452 VPSUBQ	%YMM0,%YMM1,%YMM0

  (962) 0x478456 VPCMPNLEUQ	0x9aabf(%RIP),%YMM0,%K1

  (962) 0x478461 KORTESTB	%K1,%K1

  (962) 0x478465 JE	478240

  (962) 0x47846b MOV	0xd0(%RSP),%RAX

  (962) 0x478473 MOV	0x20(%RSP),%R10

  (962) 0x478478 IMUL	%RCX,%R10

  (962) 0x47847c ADD	%RAX,%R10

  (962) 0x47847f ADD	%R11,%R10

  (962) 0x478482 VMOVUPD	(%R14,%R10,8),%YMM0{%K1}{z}

  (962) 0x478489 VMOVAPD	%YMM0,%YMM17{%K1}

  (962) 0x47848f VBROADCASTSD	%XMM25,%YMM0

  (962) 0x478495 ADD	0xe8(%RSP),%R11

  (962) 0x47849d MOV	0x68(%RSP),%R13

  (962) 0x4784a2 VMOVUPD	(%R13,%R11,8),%YMM1{%K1}{z}

  (962) 0x4784aa VMOVAPD	%YMM1,%YMM16{%K1}

  (962) 0x4784b0 VFMADD213PD	%YMM16,%YMM17,%YMM0

  (962) 0x4784b6 VMOVUPD	%YMM0,(%R13,%R11,8){%K1}

  (962) 0x4784be MOV	(%RSP),%R15

  (962) 0x4784c2 ADD	%R10,%R15

  (962) 0x4784c5 VMOVUPD	(%R14,%R15,8),%YMM1{%K1}{z}

  (962) 0x4784cc VMOVAPD	%YMM1,%YMM15{%K1}

  (962) 0x4784d2 VBROADCASTSD	%XMM24,%YMM1

  (962) 0x4784d8 VMOVAPD	%YMM0,%YMM14{%K1}

  (962) 0x4784de VFMADD213PD	%YMM14,%YMM15,%YMM1

  (962) 0x4784e3 VMOVUPD	%YMM1,(%R13,%R11,8){%K1}

  (962) 0x4784eb MOV	%RCX,%RAX

  (962) 0x4784ee MOV	0xc0(%RSP),%RCX

  (962) 0x4784f6 LEA	(%R10,%RCX,1),%R15

  (962) 0x4784fa MOV	%RAX,%RCX

  (962) 0x4784fd VMOVUPD	(%R14,%R15,8),%YMM0{%K1}{z}

  (962) 0x478504 VMOVAPD	%YMM0,%YMM13{%K1}

  (962) 0x47850a VBROADCASTSD	%XMM23,%YMM0

  (962) 0x478510 VMOVAPD	%YMM1,%YMM12{%K1}

  (962) 0x478516 VFMADD213PD	%YMM12,%YMM13,%YMM0

  (962) 0x47851b VMOVUPD	%YMM0,(%R13,%R11,8){%K1}

  (962) 0x478523 MOV	0xb8(%RSP),%RAX

  (962) 0x47852b LEA	(%R10,%RAX,1),%R15

  (962) 0x47852f VMOVUPD	(%R14,%R15,8),%YMM1{%K1}{z}

  (962) 0x478536 VMOVAPD	%YMM1,%YMM11{%K1}

  (962) 0x47853c VBROADCASTSD	%XMM22,%YMM1

  (962) 0x478542 VMOVAPD	%YMM0,%YMM10{%K1}

  (962) 0x478548 VFMADD213PD	%YMM10,%YMM11,%YMM1

  (962) 0x47854d VMOVUPD	%YMM1,(%R13,%R11,8){%K1}

  (962) 0x478555 MOV	0xb0(%RSP),%RAX

  (962) 0x47855d LEA	(%R10,%RAX,1),%R15

  (962) 0x478561 VMOVUPD	(%R14,%R15,8),%YMM0{%K1}{z}

  (962) 0x478568 VMOVAPD	%YMM0,%YMM9{%K1}

  (962) 0x47856e VBROADCASTSD	%XMM21,%YMM0

  (962) 0x478574 VMOVAPD	%YMM1,%YMM8{%K1}

  (962) 0x47857a VFMADD213PD	%YMM8,%YMM9,%YMM0

  (962) 0x47857f VMOVUPD	%YMM0,(%R13,%R11,8){%K1}

  (962) 0x478587 LEA	(%R10,%RDX,1),%R15

  (962) 0x47858b VMOVUPD	(%R14,%R15,8),%YMM1{%K1}{z}

  (962) 0x478592 VMOVAPD	%YMM1,%YMM7{%K1}

  (962) 0x478598 VBROADCASTSD	%XMM20,%YMM1

  (962) 0x47859e VMOVAPD	%YMM0,%YMM6{%K1}

  (962) 0x4785a4 VFMADD213PD	%YMM6,%YMM7,%YMM1

  (962) 0x4785a9 VMOVUPD	%YMM1,(%R13,%R11,8){%K1}

  (962) 0x4785b1 MOV	0xa8(%RSP),%RAX

  (962) 0x4785b9 LEA	(%R10,%RAX,1),%R15

  (962) 0x4785bd VMOVUPD	(%R14,%R15,8),%YMM0{%K1}{z}

  (962) 0x4785c4 MOV	(%RSP),%R15

  (962) 0x4785c8 VMOVAPD	%YMM0,%YMM5{%K1}

  (962) 0x4785ce VBROADCASTSD	%XMM19,%YMM0

  (962) 0x4785d4 VMOVAPD	%YMM1,%YMM4{%K1}

  (962) 0x4785da VFMADD213PD	%YMM4,%YMM5,%YMM0

  (962) 0x4785df VMOVUPD	%YMM0,(%R13,%R11,8){%K1}

  (962) 0x4785e7 ADD	0xc8(%RSP),%R10

  (962) 0x4785ef VMOVUPD	(%R14,%R10,8),%YMM1{%K1}{z}

  (962) 0x4785f6 VMOVAPD	%YMM1,%YMM3{%K1}

  (962) 0x4785fc VBROADCASTSD	%XMM18,%YMM1

  (962) 0x478602 VMOVUPD	0x200(%RSP),%YMM2

  (962) 0x47860b VMOVAPD	%YMM0,%YMM2{%K1}

  (962) 0x478611 VMOVUPD	%YMM2,0x200(%RSP)

  (962) 0x47861a VFMADD213PD	%YMM2,%YMM3,%YMM1

  (962) 0x47861f VMOVUPD	%YMM1,(%R13,%R11,8){%K1}

  (962) 0x478627 MOV	0x10(%RSP),%R13

  (962) 0x47862c JMP	478240

0x478631 NOPW	%CS:(%RAX,%RAX,1)

0x478640 LEA	0xe5f09(%RIP),%RDI

0x478647 MOV	0x70(%RSP),%ESI

0x47864b LEA	-0x28(%RBP),%RSP

0x47864f POP	%RBX

0x478650 POP	%R12

0x478652 POP	%R13

0x478654 POP	%R14

0x478656 POP	%R15

0x478658 POP	%RBP

0x478659 VZEROUPPER

0x47865c JMP	403050

0x478661 NOPW	%CS:(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
►100.00+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run icx_1

Source file and lines	Collapse.hpp:81-83
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/loop/forall.hpp:59
/home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/src/Kripke/Kernel/LTimes.cpp:62
/home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/internal/Iterators.hpp:55,177
/home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/Layout.hpp:55
/home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/View.hpp:79,110
/home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/openmp/kernel/Collapse.hpp:81-83

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 38.50 to 3.67 cycles (10.50x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 12% of vector register length is used (average across all SSE/AVX instructions).

Details

2% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX loads are used in vector version.
1% of SSE/AVX stores are used in vector version.
0% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX multiply instructions are used in vector version.
6% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

__kmpc_for_static_init_8@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/openmp/kernel/Collapse.hpp:81

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VZEROUPPER: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/openmp/kernel/Collapse.hpp:81

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 208 bytes. The binary function is storing 456 bytes.

General properties

nb instructions	229
nb uops	231
loop length	1375
used x86 registers	16
used mmx registers	0
used xmm registers	0
used ymm registers	1
used zmm registers	0
nb stack references	57

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	38.50 cycles
front end	38.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	9.50	11.00	11.00	11.00	32.50	9.47	9.50	32.50	32.50	32.50	9.53	11.00
cycles	9.50	16.87	11.00	11.00	32.50	9.47	9.50	32.50	32.50	32.50	9.53	11.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	38.50
Dispatch	32.50
Overall L1	38.50

Vectorization ratios

all	2%
load	0%
store	1%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

Vector efficiency ratios

all	12%
load	10%
store	12%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 38.50 cycles. At this rate:

2% of peak load performance is reached (5.40 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
9% of peak store performance is reached (11.84 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 38.50 to 32.50 cycles (1.18x speedup).

ASM code

In the binary file, the address of the function is: 4779e0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
AND $-0x20,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SUB $0x240,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RDX,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOVL $0,0x74(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV (%R8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,0x178(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x10(%R8),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x18(%R8),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x20(%R8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,0x170(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x30(%R8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,0x98(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x38(%R8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,0x90(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x60(%R8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,0x168(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x68(%R8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,0x160(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xa8(%R8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,0x68(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV (%RDI),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV %R9,0xf0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xc8(%R8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,0x10(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xf0(%R8),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x110(%R8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x118(%R8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,0x88(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x158(%R8),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOVQ $0,0xf8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOVQ $0x1,0x1d8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA 0x1e0(%RSP),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA 0xe6a69(%RIP),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA 0x7c(%RSP),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA 0x100(%RSP),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA 0xf8(%RSP),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %ESI,0x78(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RAX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
CALL 403140 <__kmpc_for_static_init_8@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
ADD $0x20,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0xf8(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0xf0(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RCX,0x80(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CMP %RAX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JA 478640 <_ZNK6Kripke14DispatchHelperINS_12ArchT_OpenMPEEclINS_11LayoutT_DGZE10LTimesSdomJRNS_6SdomIdERKNS_4Core3SetESB_SB_SB_RNS8_5FieldIdJNS_9DirectionENS_5GroupENS_4ZoneEEEERNSC_IdJNS_6MomentESE_SF_EEERNSC_IdJSI_SD_EEEEEEvT_RKT0_DpOT1_.extracted+0xc60>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R15,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %R13,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RCX,0x48(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JLE 478640 <_ZNK6Kripke14DispatchHelperINS_12ArchT_OpenMPEEclINS_11LayoutT_DGZE10LTimesSdomJRNS_6SdomIdERKNS_4Core3SetESB_SB_SB_RNS8_5FieldIdJNS_9DirectionENS_5GroupENS_4ZoneEEEERNSC_IdJNS_6MomentESE_SF_EEERNSC_IdJSI_SD_EEEEEEvT_RKT0_DpOT1_.extracted+0xc60>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x80(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA 0x1(%RDX),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
INC %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RAX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
CMOVG %RCX,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	N/A
NOT %RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %RAX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RDX,0x158(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R13,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R13,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV (%RSP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
IMUL %R9,%RAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV %RAX,0x60(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R9,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SAR $0x3f,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
ANDN %R9,%RAX,%RAX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1-2	0.33	N/A
MOV %R13,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
NOT %RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV %R15,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %RAX,%RCX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV %RCX,0x148(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
IMUL %RSI,%RAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV %RAX,0x150(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
XOR %R13D,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
TEST %R9,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
MOV $0,%R10D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMOVS %R9,%R10	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	N/A
MOV %R15,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %R10,%RAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV %RAX,0x8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
IMUL %RSI,%R10	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV %RDI,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x10(%RSP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
IMUL %R8,%RCX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV %RCX,0x138(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R8,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SAR $0x3f,%RCX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
ANDN %R8,%RCX,%RCX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1-2	0.33	N/A
MOV %R15,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %RCX,%R11	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
IMUL %RSI,%RCX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
TEST %R8,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
MOV %R15,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0,%R15D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
CMOVS %R8,%R15	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	scal (12.5%)
MOV %RAX,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %R15,%RDX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
IMUL %RSI,%R15	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
ADD %RDX,%R15	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV %R15,0x128(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %RAX,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV %RSI,0x120(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x90(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x98(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SUB %RDX,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
ADD 0x8(%RSP),%R10	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
MOV %R10,0x140(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x48(%RSP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R10,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SHR $0x3,%R15	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (12.5%)
DEC %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %R15,0x1d0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %R11,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RCX,0x130(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (,%R8,8),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,0x1b8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
SUB %R8,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RAX,0x1b0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RSI,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x4,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
LEA (,%R9,8),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,0x20(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
SUB %R9,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RAX,0xc8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VPBROADCASTQ %RSI,%YMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVDQU %YMM0,0x1e0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
MOV %R10,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
AND $-0x8,%R15	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (12.5%)
LEA (,%RDX,8),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x60(%RSP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%RAX,%R11,8),%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD %R14,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R11,0x78(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R9,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SAL $0x6,%R11	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
MOV %R15,0x118(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %R15,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
IMUL %R9,%RDI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
LEA (%RAX,%RDI,8),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD %R14,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RAX,0x100(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %RDX,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RDI,0x108(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (%R8,%R8,1),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%R8,%R8,2),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDX,0x1a0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (,%R8,4),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDX,0x198(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (%R8,%R8,4),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDX,0x190(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R11,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RAX,0x1a8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (%RAX,%RAX,2),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,0x188(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RCX,0x28(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA -0x1(%RCX),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,0xe0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (%R9,%R9,1),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,0xc0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (%R9,%R9,2),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RCX,0xb8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (,%R9,4),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RCX,0xb0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (%R9,%R9,4),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%RAX,%RAX,2),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,0xa8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA -0x1(%R10),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,0x1c8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x88(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (,%RAX,8),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,0x38(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R12,0x40(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RSI,0xd8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R11,0xa0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RBX,0x180(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDX,0x110(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JMP 477ddc <_ZNK6Kripke14DispatchHelperINS_12ArchT_OpenMPEEclINS_11LayoutT_DGZE10LTimesSdomJRNS_6SdomIdERKNS_4Core3SetESB_SB_SB_RNS8_5FieldIdJNS_9DirectionENS_5GroupENS_4ZoneEEEERNSC_IdJNS_6MomentESE_SF_EEERNSC_IdJSI_SD_EEEEEEvT_RKT0_DpOT1_.extracted+0x3fc>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XCHG %AX,%AX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XCHG %AX,%AX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 478640 <_ZNK6Kripke14DispatchHelperINS_12ArchT_OpenMPEEclINS_11LayoutT_DGZE10LTimesSdomJRNS_6SdomIdERKNS_4Core3SetESB_SB_SB_RNS8_5FieldIdJNS_9DirectionENS_5GroupENS_4ZoneEEEERNSC_IdJNS_6MomentESE_SF_EEERNSC_IdJSI_SD_EEEEEEvT_RKT0_DpOT1_.extracted+0xc60>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA 0xe5f09(%RIP),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x70(%RSP),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
LEA -0x28(%RBP),%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
JMP 403050 <__kmpc_for_static_fini@plt>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run icx_1

Source file and lines	Collapse.hpp:81-83
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/loop/forall.hpp:59
/home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/src/Kripke/Kernel/LTimes.cpp:62
/home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/internal/Iterators.hpp:55,177
/home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/Layout.hpp:55
/home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/View.hpp:79,110
/home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/openmp/kernel/Collapse.hpp:81-83

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 12% of vector register length is used (average across all SSE/AVX instructions).

Details

2% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX loads are used in vector version.
1% of SSE/AVX stores are used in vector version.
0% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX multiply instructions are used in vector version.
6% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

Workaround

Recompile with -mprefer-vector-width=512

CALL instructions

Detected function call instructions.

Details

__kmpc_for_static_init_8@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/openmp/kernel/Collapse.hpp:81

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VZEROUPPER: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/openmp/kernel/Collapse.hpp:81

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 208 bytes. The binary function is storing 456 bytes.

General properties

nb instructions	229
nb uops	231
loop length	1375
used x86 registers	16
used mmx registers	0
used xmm registers	0
used ymm registers	1
used zmm registers	0
nb stack references	57

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	38.50 cycles
front end	38.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	9.50	11.00	11.00	11.00	32.50	9.47	9.50	32.50	32.50	32.50	9.53	11.00
cycles	9.50	16.87	11.00	11.00	32.50	9.47	9.50	32.50	32.50	32.50	9.53	11.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	38.50
Dispatch	32.50
Overall L1	38.50

Vectorization ratios

all	2%
load	0%
store	1%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

Vector efficiency ratios

all	12%
load	10%
store	12%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 38.50 cycles. At this rate:

2% of peak load performance is reached (5.40 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
9% of peak store performance is reached (11.84 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 4779e0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
AND $-0x20,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SUB $0x240,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RDX,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOVL $0,0x74(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV (%R8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,0x178(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x10(%R8),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x18(%R8),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x20(%R8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,0x170(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x30(%R8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,0x98(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x38(%R8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,0x90(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x60(%R8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,0x168(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x68(%R8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,0x160(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xa8(%R8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,0x68(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV (%RDI),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV %R9,0xf0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xc8(%R8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,0x10(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xf0(%R8),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x110(%R8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x118(%R8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,0x88(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x158(%R8),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOVQ $0,0xf8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOVQ $0x1,0x1d8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA 0x1e0(%RSP),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA 0xe6a69(%RIP),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA 0x7c(%RSP),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA 0x100(%RSP),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA 0xf8(%RSP),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %ESI,0x78(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RAX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
CALL 403140 <__kmpc_for_static_init_8@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
ADD $0x20,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0xf8(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0xf0(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RCX,0x80(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CMP %RAX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JA 478640 <_ZNK6Kripke14DispatchHelperINS_12ArchT_OpenMPEEclINS_11LayoutT_DGZE10LTimesSdomJRNS_6SdomIdERKNS_4Core3SetESB_SB_SB_RNS8_5FieldIdJNS_9DirectionENS_5GroupENS_4ZoneEEEERNSC_IdJNS_6MomentESE_SF_EEERNSC_IdJSI_SD_EEEEEEvT_RKT0_DpOT1_.extracted+0xc60>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R15,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %R13,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RCX,0x48(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JLE 478640 <_ZNK6Kripke14DispatchHelperINS_12ArchT_OpenMPEEclINS_11LayoutT_DGZE10LTimesSdomJRNS_6SdomIdERKNS_4Core3SetESB_SB_SB_RNS8_5FieldIdJNS_9DirectionENS_5GroupENS_4ZoneEEEERNSC_IdJNS_6MomentESE_SF_EEERNSC_IdJSI_SD_EEEEEEvT_RKT0_DpOT1_.extracted+0xc60>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x80(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA 0x1(%RDX),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
INC %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RAX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
CMOVG %RCX,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	N/A
NOT %RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %RAX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RDX,0x158(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R13,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R13,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV (%RSP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
IMUL %R9,%RAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV %RAX,0x60(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R9,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SAR $0x3f,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
ANDN %R9,%RAX,%RAX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1-2	0.33	N/A
MOV %R13,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
NOT %RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV %R15,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %RAX,%RCX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV %RCX,0x148(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
IMUL %RSI,%RAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV %RAX,0x150(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
XOR %R13D,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
TEST %R9,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
MOV $0,%R10D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMOVS %R9,%R10	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	N/A
MOV %R15,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %R10,%RAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV %RAX,0x8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
IMUL %RSI,%R10	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV %RDI,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x10(%RSP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
IMUL %R8,%RCX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV %RCX,0x138(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R8,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SAR $0x3f,%RCX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
ANDN %R8,%RCX,%RCX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1-2	0.33	N/A
MOV %R15,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %RCX,%R11	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
IMUL %RSI,%RCX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
TEST %R8,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
MOV %R15,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0,%R15D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
CMOVS %R8,%R15	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	scal (12.5%)
MOV %RAX,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %R15,%RDX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
IMUL %RSI,%R15	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
ADD %RDX,%R15	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV %R15,0x128(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %RAX,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV %RSI,0x120(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x90(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x98(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SUB %RDX,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
ADD 0x8(%RSP),%R10	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
MOV %R10,0x140(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x48(%RSP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R10,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SHR $0x3,%R15	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (12.5%)
DEC %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %R15,0x1d0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %R11,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RCX,0x130(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (,%R8,8),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,0x1b8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
SUB %R8,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RAX,0x1b0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RSI,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x4,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
LEA (,%R9,8),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,0x20(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
SUB %R9,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RAX,0xc8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VPBROADCASTQ %RSI,%YMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVDQU %YMM0,0x1e0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
MOV %R10,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
AND $-0x8,%R15	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (12.5%)
LEA (,%RDX,8),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x60(%RSP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%RAX,%R11,8),%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD %R14,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R11,0x78(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R9,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SAL $0x6,%R11	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
MOV %R15,0x118(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %R15,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
IMUL %R9,%RDI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
LEA (%RAX,%RDI,8),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD %R14,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RAX,0x100(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %RDX,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RDI,0x108(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (%R8,%R8,1),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%R8,%R8,2),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDX,0x1a0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (,%R8,4),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDX,0x198(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (%R8,%R8,4),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDX,0x190(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R11,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RAX,0x1a8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (%RAX,%RAX,2),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,0x188(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RCX,0x28(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA -0x1(%RCX),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,0xe0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (%R9,%R9,1),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,0xc0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (%R9,%R9,2),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RCX,0xb8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (,%R9,4),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RCX,0xb0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (%R9,%R9,4),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%RAX,%RAX,2),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,0xa8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA -0x1(%R10),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,0x1c8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x88(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (,%RAX,8),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,0x38(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R12,0x40(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RSI,0xd8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R11,0xa0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RBX,0x180(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDX,0x110(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JMP 477ddc <_ZNK6Kripke14DispatchHelperINS_12ArchT_OpenMPEEclINS_11LayoutT_DGZE10LTimesSdomJRNS_6SdomIdERKNS_4Core3SetESB_SB_SB_RNS8_5FieldIdJNS_9DirectionENS_5GroupENS_4ZoneEEEERNSC_IdJNS_6MomentESE_SF_EEERNSC_IdJSI_SD_EEEEEEvT_RKT0_DpOT1_.extracted+0x3fc>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XCHG %AX,%AX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XCHG %AX,%AX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 478640 <_ZNK6Kripke14DispatchHelperINS_12ArchT_OpenMPEEclINS_11LayoutT_DGZE10LTimesSdomJRNS_6SdomIdERKNS_4Core3SetESB_SB_SB_RNS8_5FieldIdJNS_9DirectionENS_5GroupENS_4ZoneEEEERNSC_IdJNS_6MomentESE_SF_EEERNSC_IdJSI_SD_EEEEEEvT_RKT0_DpOT1_.extracted+0xc60>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA 0xe5f09(%RIP),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x70(%RSP),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
LEA -0x28(%RBP),%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
JMP 403050 <__kmpc_for_static_fini@plt>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

Name	Coverage (%)	Time (s)
▼void Kripke::DispatchHelper::operator()–	4.18	0.47
▼Loop 956 - Collapse.hpp:81-83 - exec–	0.00	0.01
▼Loop 962 - forall.hpp:59-59 - exec–	0.01	0.01
○Loop 963 - forall.hpp:59-59 - exec	2.89	0.32
▼Loop 959 - forall.hpp:59-59 - exec–	0.00	0.00
○Loop 961 - forall.hpp:59-59 - exec	1.28	0.14
○Loop 960 - forall.hpp:59-59 - exec	0.00	0.00
▼Loop 957 - forall.hpp:59-59 - exec–	0.00	0.00
○Loop 958 - forall.hpp:59-59 - exec	0.00	0.00

Report Configuration

Code clean check

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Execution units bottlenecks

512-bits vectorization

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CALL instructions

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Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

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Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code