OV - exec - Function void LPlusTimesSdom::operator()<Kripke::ArchLayoutT<Kripke::ArchT_OpenMP, Kripke::LayoutT_DGZ> >(Kripke::ArchLayoutT<Kripke::ArchT_OpenMP, Kripke::LayoutT_DGZ>, Kripke::SdomId, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Field<double, Kripke::Moment, Kripke::Group, Kripke::Zone>&, Kripke::Core::Field<double, Kripke::Direction, Kripke::Group, Kripke::Zone>&, Kripke::Core::Field<double, Kripke::Direction, Kripke::Moment>&) const [clone .extracted]

	Function: void LPlusTimesSdom::operator()<Kripke::ArchLayoutT<Kripke::ArchT_OpenMP, Kripke::LayoutT_ ...	Module: exec	Source: Collapse.hpp:81-83 [...]	Coverage (incl. loops): 1.50% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/loop/forall.hpp: 59 - 59

--------------------------------------------------------------------------------

59:   for (decltype(distance_it) i = 0; i < distance_it; ++i) {

/home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/src/Kripke/Kernel/LPlusTimes.cpp: 57 - 57

--------------------------------------------------------------------------------

57:             rhs(d,g,z) += ell_plus(d, nm) * phi_out(nm, g, z);

/home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/internal/Iterators.hpp: 55 - 177

--------------------------------------------------------------------------------

55:       : val(rhs.val)

[...]

177:     return value_type(val + rhs);

/home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/Layout.hpp: 55 - 55

--------------------------------------------------------------------------------

55:     return a * b;

/home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/View.hpp: 79 - 110

--------------------------------------------------------------------------------

79:       : layout(V.layout), data(V.data)

[...]

110:     return data[idx];

/home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/openmp/kernel/Collapse.hpp: 81 - 83

--------------------------------------------------------------------------------

81: #pragma omp parallel for private(i0, i1) firstprivate(privatizer) \

82:     RAJA_COLLAPSE(2)

83:     for (i0 = 0; i0 < l0; ++i0) {

0x46a260 PUSH	%RBP

0x46a261 MOV	%RSP,%RBP

0x46a264 PUSH	%R15

0x46a266 PUSH	%R14

0x46a268 PUSH	%R13

0x46a26a PUSH	%R12

0x46a26c PUSH	%RBX

0x46a26d AND	$-0x20,%RSP

0x46a271 SUB	$0x200,%RSP

0x46a278 MOV	%RDX,%RBX

0x46a27b MOVL	$0,0x74(%RSP)

0x46a283 MOV	(%R8),%RAX

0x46a286 MOV	%RAX,0x158(%RSP)

0x46a28e MOV	0x10(%R8),%RAX

0x46a292 MOV	%RAX,0x58(%RSP)

0x46a297 MOV	0x18(%R8),%RAX

0x46a29b MOV	%RAX,0x50(%RSP)

0x46a2a0 MOV	0x20(%R8),%RAX

0x46a2a4 MOV	%RAX,0x150(%RSP)

0x46a2ac MOV	0x30(%R8),%RAX

0x46a2b0 MOV	%RAX,0x98(%RSP)

0x46a2b8 MOV	0x38(%R8),%RAX

0x46a2bc MOV	%RAX,0x90(%RSP)

0x46a2c4 MOV	0x60(%R8),%RAX

0x46a2c8 MOV	%RAX,0x148(%RSP)

0x46a2d0 MOV	0x68(%R8),%RAX

0x46a2d4 MOV	%RAX,0x140(%RSP)

0x46a2dc MOV	0xa8(%R8),%R12

0x46a2e3 MOV	(%RDI),%ESI

0x46a2e5 MOV	%R9,0xe0(%RSP)

0x46a2ed MOV	0xc0(%R8),%RAX

0x46a2f4 MOV	%RAX,0x138(%RSP)

0x46a2fc MOV	0xf0(%R8),%R13

0x46a303 MOV	0x110(%R8),%R15

0x46a30a MOV	0x118(%R8),%RAX

0x46a311 MOV	%RAX,0x88(%RSP)

0x46a319 MOV	0x158(%R8),%R14

0x46a320 MOVQ	$0,0xe8(%RSP)

0x46a32c MOVQ	$0x1,0x198(%RSP)

0x46a338 SUB	$0x8,%RSP

0x46a33c LEA	0x1a0(%RSP),%RAX

0x46a344 LEA	0xf3fa5(%RIP),%RDI

0x46a34b LEA	0x7c(%RSP),%RCX

0x46a350 LEA	0xf0(%RSP),%R8

0x46a358 LEA	0xe8(%RSP),%R9

0x46a360 MOV	%ESI,0x78(%RSP)

0x46a364 MOV	$0x22,%EDX

0x46a369 PUSH	$0x1

0x46a36b PUSH	$0x1

0x46a36d PUSH	%RAX

0x46a36e CALL	403140 <__kmpc_for_static_init_8@plt>

0x46a373 ADD	$0x20,%RSP

0x46a377 MOV	0xe8(%RSP),%RCX

0x46a37f MOV	0xe0(%RSP),%RAX

0x46a387 MOV	%RCX,0x80(%RSP)

0x46a38f CMP	%RAX,%RCX

0x46a392 JA	46ad80

0x46a398 MOV	0x50(%RSP),%RCX

0x46a39d SUB	0x58(%RSP),%RCX

0x46a3a2 MOV	%RCX,0x48(%RSP)

0x46a3a7 JLE	46ad80

0x46a3ad MOV	%R15,%RSI

0x46a3b0 MOV	0x80(%RSP),%RDX

0x46a3b8 LEA	0x1(%RDX),%RCX

0x46a3bc INC	%RAX

0x46a3bf CMP	%RAX,%RCX

0x46a3c2 CMOVG	%RCX,%RAX

0x46a3c6 NOT	%RDX

0x46a3c9 ADD	%RAX,%RDX

0x46a3cc MOV	%RDX,0x130(%RSP)

0x46a3d4 MOV	0x58(%RSP),%RCX

0x46a3d9 MOV	%RCX,%R9

0x46a3dc IMUL	%R15,%R9

0x46a3e0 MOV	%R15,%RAX

0x46a3e3 SAR	$0x3f,%RAX

0x46a3e7 ANDN	%R15,%RAX,%RAX

0x46a3ec MOV	%RCX,%RDI

0x46a3ef NOT	%RDI

0x46a3f2 MOV	0x50(%RSP),%RDX

0x46a3f7 MOV	%RDX,%R8

0x46a3fa IMUL	%RAX,%R8

0x46a3fe MOV	%R8,0x118(%RSP)

0x46a406 IMUL	%RDI,%RAX

0x46a40a MOV	%RAX,0x120(%RSP)

0x46a412 XOR	%R10D,%R10D

0x46a415 TEST	%R15,%R15

0x46a418 MOV	$0,%R8D

0x46a41e CMOVS	%R15,%R8

0x46a422 MOV	%RDX,%RAX

0x46a425 IMUL	%R8,%RAX

0x46a429 IMUL	%RDI,%R8

0x46a42d ADD	%RAX,%R8

0x46a430 MOV	%R8,0x110(%RSP)

0x46a438 ADD	%RDX,%RDI

0x46a43b MOV	%RDI,0x108(%RSP)

0x46a443 MOV	0x90(%RSP),%RDI

0x46a44b MOV	0x98(%RSP),%RDX

0x46a453 SUB	%RDX,%RDI

0x46a456 MOV	0x48(%RSP),%R8

0x46a45b MOV	%R8,%RAX

0x46a45e SHR	$0x3,%RAX

0x46a462 DEC	%RAX

0x46a465 MOV	%RAX,0x190(%RSP)

0x46a46d MOV	%RDI,%R11

0x46a470 AND	$-0x4,%R11

0x46a474 LEA	(,%R15,8),%RAX

0x46a47c MOV	%RAX,0x20(%RSP)

0x46a481 SUB	%R15,%RAX

0x46a484 MOV	%RAX,0xc8(%RSP)

0x46a48c VPBROADCASTQ	%RDI,%YMM0

0x46a492 VMOVDQU	%YMM0,0x1a0(%RSP)

0x46a49b MOV	%R8,%R15

0x46a49e AND	$-0x8,%R15

0x46a4a2 LEA	(,%RDX,8),%RAX

0x46a4aa MOV	%R9,0x128(%RSP)

0x46a4b2 LEA	(%RAX,%R9,8),%R9

0x46a4b6 ADD	%R14,%R9

0x46a4b9 MOV	%R9,0x78(%RSP)

0x46a4be MOV	%RSI,%R9

0x46a4c1 SAL	$0x6,%R9

0x46a4c5 MOV	%R9,0x188(%RSP)

0x46a4cd MOV	%R12,%R9

0x46a4d0 MOV	%R15,0x100(%RSP)

0x46a4d8 ADD	%R15,%RCX

0x46a4db IMUL	%RSI,%RCX

0x46a4df LEA	(%RAX,%RCX,8),%RAX

0x46a4e3 ADD	%R14,%RAX

0x46a4e6 MOV	%RAX,0xf0(%RSP)

0x46a4ee ADD	%RDX,%RCX

0x46a4f1 MOV	%RCX,0xf8(%RSP)

0x46a4f9 MOV	%R11,0x28(%RSP)

0x46a4fe LEA	-0x1(%R11),%R11

0x46a502 LEA	(%RSI,%RSI,1),%RAX

0x46a506 MOV	%RAX,0xc0(%RSP)

0x46a50e LEA	(%RSI,%RSI,2),%RCX

0x46a512 MOV	%RCX,0xb8(%RSP)

0x46a51a LEA	(,%RSI,4),%RCX

0x46a522 MOV	%RCX,0xb0(%RSP)

0x46a52a LEA	(%RSI,%RSI,4),%RCX

0x46a52e MOV	%RCX,0xa8(%RSP)

0x46a536 LEA	(%RAX,%RAX,2),%RAX

0x46a53a MOV	%RAX,0xa0(%RSP)

0x46a542 LEA	-0x1(%R8),%RAX

0x46a546 MOV	%RAX,0x180(%RSP)

0x46a54e MOV	0x88(%RSP),%RAX

0x46a556 LEA	(,%RAX,8),%RAX

0x46a55e MOV	%RAX,0x38(%RSP)

0x46a563 MOV	%RBX,0x40(%RSP)

0x46a568 MOV	%RSI,0x10(%RSP)

0x46a56d MOV	%R9,0x18(%RSP)

0x46a572 MOV	%R13,0x168(%RSP)

0x46a57a MOV	%RDI,0x160(%RSP)

0x46a582 JMP	46a5dc

0x46a584 NOPW	%CS:(%RAX,%RAX,1)

0x46a593 NOPW	%CS:(%RAX,%RAX,1)

0x46a5a2 NOPW	%CS:(%RAX,%RAX,1)

0x46a5b1 NOPW	%CS:(%RAX,%RAX,1)

(804) 0x46a5c0 MOV	0x40(%RSP),%RBX

(804) 0x46a5c5 MOV	0x60(%RSP),%R10

(804) 0x46a5ca CMP	0x130(%RSP),%R10

(804) 0x46a5d2 LEA	0x1(%R10),%R10

(804) 0x46a5d6 JE	46ad80

(804) 0x46a5dc MOV	0x80(%RSP),%RAX

(804) 0x46a5e4 ADD	%R10,%RAX

(804) 0x46a5e7 MOV	%RAX,%RDX

(804) 0x46a5ea OR	%RBX,%RDX

(804) 0x46a5ed SHR	$0x20,%RDX

(804) 0x46a5f1 MOV	%R10,0x60(%RSP)

(804) 0x46a5f6 JE	46a640

(804) 0x46a5f8 CQTO

(804) 0x46a5fa IDIV	%RBX

(804) 0x46a5fd MOV	%RAX,%R12

(804) 0x46a600 JMP	46a647

0x46a602 NOPW	%CS:(%RAX,%RAX,1)

0x46a611 NOPW	%CS:(%RAX,%RAX,1)

0x46a620 NOPW	%CS:(%RAX,%RAX,1)

0x46a62f NOPW	%CS:(%RAX,%RAX,1)

0x46a63e XCHG	%AX,%AX

(804) 0x46a640 XOR	%EDX,%EDX

(804) 0x46a642 DIV	%EBX

(804) 0x46a644 MOV	%EAX,%R12D

(804) 0x46a647 ADD	0x158(%RSP),%R12

(804) 0x46a64f ADD	0x150(%RSP),%RDX

(804) 0x46a657 MOV	0x88(%RSP),%RBX

(804) 0x46a65f IMUL	%RDX,%RBX

(804) 0x46a663 MOV	0x90(%RSP),%R10

(804) 0x46a66b MOV	0x128(%RSP),%RCX

(804) 0x46a673 LEA	(%R10,%RCX,1),%RAX

(804) 0x46a677 ADD	0x120(%RSP),%RAX

(804) 0x46a67f ADD	0x118(%RSP),%RAX

(804) 0x46a687 ADD	%RBX,%RAX

(804) 0x46a68a LEA	-0x8(%R14,%RAX,8),%RAX

(804) 0x46a68f MOV	0x140(%RSP),%RSI

(804) 0x46a697 MOV	%RDX,0x8(%RSP)

(804) 0x46a69c IMUL	%RDX,%RSI

(804) 0x46a6a0 MOV	0x98(%RSP),%R9

(804) 0x46a6a8 LEA	(%R9,%RSI,1),%R15

(804) 0x46a6ac MOV	0x148(%RSP),%R8

(804) 0x46a6b4 IMUL	%R12,%R8

(804) 0x46a6b8 ADD	%R8,%R15

(804) 0x46a6bb MOV	0x18(%RSP),%RDX

(804) 0x46a6c0 MOV	%R15,0xd8(%RSP)

(804) 0x46a6c8 LEA	(%RDX,%R15,8),%R15

(804) 0x46a6cc CMP	%R15,%RAX

(804) 0x46a6cf SETAEB	0x30(%RSP)

(804) 0x46a6d4 ADD	%R10,%RSI

(804) 0x46a6d7 ADD	%R8,%RSI

(804) 0x46a6da LEA	-0x8(%RDX,%RSI,8),%R8

(804) 0x46a6df MOV	%RBX,%RDX

(804) 0x46a6e2 LEA	(%R9,%RCX,1),%RAX

(804) 0x46a6e6 ADD	%RBX,%RAX

(804) 0x46a6e9 MOV	0x110(%RSP),%RCX

(804) 0x46a6f1 LEA	(%RCX,%RAX,1),%RSI

(804) 0x46a6f5 LEA	(%R14,%RSI,8),%RSI

(804) 0x46a6f9 CMP	%RSI,%R8

(804) 0x46a6fc SETAE	%BL

(804) 0x46a6ff IMUL	0x138(%RSP),%R12

(804) 0x46a708 MOV	0x50(%RSP),%RSI

(804) 0x46a70d ADD	%R12,%RSI

(804) 0x46a710 LEA	-0x8(%R13,%RSI,8),%RSI

(804) 0x46a715 CMP	%R15,%RSI

(804) 0x46a718 SETB	%SIL

(804) 0x46a71c ADD	0x58(%RSP),%R12

(804) 0x46a721 LEA	(%R13,%R12,8),%R9

(804) 0x46a726 CMP	%R9,%R8

(804) 0x46a729 SETB	%R8B

(804) 0x46a72d TEST	%BL,0x30(%RSP)

(804) 0x46a731 JNE	46a8c0

(804) 0x46a737 OR	%R8B,%SIL

(804) 0x46a73a JE	46a8c0

(804) 0x46a740 MOV	%RAX,0xd0(%RSP)

(804) 0x46a748 CMPQ	$0x8,0x48(%RSP)

(804) 0x46a74e MOV	0x10(%RSP),%R10

(804) 0x46a753 JAE	46a980

(804) 0x46a759 MOV	0x8(%RSP),%RCX

(804) 0x46a75e MOV	0x100(%RSP),%RAX

(804) 0x46a766 CMP	0x48(%RSP),%RAX

(804) 0x46a76b JAE	46a5c0

(804) 0x46a771 IMUL	0x38(%RSP),%RCX

(804) 0x46a777 ADD	0xf0(%RSP),%RCX

(804) 0x46a77f ADD	0xf8(%RSP),%RDX

(804) 0x46a787 JMP	46a7da

0x46a789 NOPW	%CS:(%RAX,%RAX,1)

0x46a798 NOPW	%CS:(%RAX,%RAX,1)

0x46a7a7 NOPW	%CS:(%RAX,%RAX,1)

0x46a7b6 NOPW	%CS:(%RAX,%RAX,1)

  (807) 0x46a7c0 ADD	0x20(%RSP),%RCX

  (807) 0x46a7c5 ADD	%R10,%RDX

  (807) 0x46a7c8 CMP	0x180(%RSP),%RAX

  (807) 0x46a7d0 LEA	0x1(%RAX),%RAX

  (807) 0x46a7d4 JE	46a5c0

  (807) 0x46a7da TEST	%RDI,%RDI

  (807) 0x46a7dd JLE	46a7c0

  (807) 0x46a7df LEA	(%R12,%RAX,1),%RSI

  (807) 0x46a7e3 VMOVSD	(%R13,%RSI,8),%XMM18

  (807) 0x46a7eb CMPQ	$0,0x28(%RSP)

  (807) 0x46a7f1 JE	46a840

  (807) 0x46a7f3 MOV	%RDX,%R8

  (807) 0x46a7f6 VBROADCASTSD	%XMM18,%YMM0

  (807) 0x46a7fc XOR	%ESI,%ESI

  (807) 0x46a7fe XCHG	%AX,%AX

    (809) 0x46a800 VMOVUPD	(%RCX,%RSI,8),%YMM1

    (809) 0x46a805 VFMADD213PD	(%R15,%RSI,8),%YMM0,%YMM1

    (809) 0x46a80b VMOVUPD	%YMM1,(%R15,%RSI,8)

    (809) 0x46a811 ADD	$0x4,%RSI

    (809) 0x46a815 CMP	%R11,%RSI

    (809) 0x46a818 JLE	46a800

  (807) 0x46a81a MOV	%RCX,%RDX

  (807) 0x46a81d MOV	0x28(%RSP),%RCX

  (807) 0x46a822 MOV	%RCX,%R9

  (807) 0x46a825 CMP	%RCX,%RDI

  (807) 0x46a828 MOV	%RDX,%RCX

  (807) 0x46a82b MOV	%R8,%RDX

  (807) 0x46a82e JE	46a7c0

  (807) 0x46a830 JMP	46a843

0x46a832 NOPW	%CS:(%RAX,%RAX,1)

  (807) 0x46a840 XOR	%R9D,%R9D

  (807) 0x46a843 MOV	%RDI,%RSI

  (807) 0x46a846 SUB	%R9,%RSI

  (807) 0x46a849 MOV	0xd8(%RSP),%R8

  (807) 0x46a851 ADD	%R9,%R8

  (807) 0x46a854 MOV	%RDX,%RBX

  (807) 0x46a857 MOV	0x18(%RSP),%RDX

  (807) 0x46a85c LEA	(%RDX,%R8,8),%R8

  (807) 0x46a860 MOV	%RBX,%RDX

  (807) 0x46a863 ADD	%RBX,%R9

  (807) 0x46a866 LEA	(%R14,%R9,8),%R9

  (807) 0x46a86a XOR	%EBX,%EBX

  (807) 0x46a86c NOPL	(%RAX)

    (808) 0x46a870 VMOVSD	(%R9,%RBX,8),%XMM0

    (808) 0x46a876 VFMADD213SD	(%R8,%RBX,8),%XMM18,%XMM0

    (808) 0x46a87d VMOVSD	%XMM0,(%R8,%RBX,8)

    (808) 0x46a883 INC	%RBX

    (808) 0x46a886 CMP	%RBX,%RSI

    (808) 0x46a889 JNE	46a870

  (807) 0x46a88b JMP	46a7c0

0x46a890 NOPW	%CS:(%RAX,%RAX,1)

0x46a89f NOPW	%CS:(%RAX,%RAX,1)

0x46a8ae NOPW	%CS:(%RAX,%RAX,1)

0x46a8bd NOPL	(%RAX)

(804) 0x46a8c0 MOV	0x8(%RSP),%RDX

(804) 0x46a8c5 IMUL	0x38(%RSP),%RDX

(804) 0x46a8cb ADD	0x78(%RSP),%RDX

(804) 0x46a8d0 XOR	%EAX,%EAX

(804) 0x46a8d2 MOV	0x40(%RSP),%RBX

(804) 0x46a8d7 MOV	0x108(%RSP),%RCX

(804) 0x46a8df MOV	0x60(%RSP),%R10

(804) 0x46a8e4 MOV	0x20(%RSP),%R9

(804) 0x46a8e9 JMP	46a910

0x46a8eb NOPW	%CS:(%RAX,%RAX,1)

0x46a8fa NOPW	(%RAX,%RAX,1)

  (805) 0x46a900 ADD	%R9,%RDX

  (805) 0x46a903 CMP	%RCX,%RAX

  (805) 0x46a906 LEA	0x1(%RAX),%RAX

  (805) 0x46a90a JE	46a5ca

  (805) 0x46a910 TEST	%RDI,%RDI

  (805) 0x46a913 JLE	46a900

  (805) 0x46a915 LEA	(%R12,%RAX,1),%RSI

  (805) 0x46a919 XOR	%R8D,%R8D

  (805) 0x46a91c NOPL	(%RAX)

    (806) 0x46a920 VMOVSD	(%RDX,%R8,8),%XMM0

    (806) 0x46a926 VMOVSD	(%R13,%RSI,8),%XMM1

    (806) 0x46a92d VFMADD213SD	(%R15,%R8,8),%XMM0,%XMM1

    (806) 0x46a933 VMOVSD	%XMM1,(%R15,%R8,8)

    (806) 0x46a939 INC	%R8

    (806) 0x46a93c CMP	%R8,%RDI

    (806) 0x46a93f JNE	46a920

  (805) 0x46a941 JMP	46a900

0x46a943 NOPW	%CS:(%RAX,%RAX,1)

0x46a952 NOPW	%CS:(%RAX,%RAX,1)

0x46a961 NOPW	%CS:(%RAX,%RAX,1)

0x46a970 NOPW	%CS:(%RAX,%RAX,1)

0x46a97f NOP

(804) 0x46a980 MOV	0x38(%RSP),%RBX

(804) 0x46a985 MOV	0x8(%RSP),%RCX

(804) 0x46a98a IMUL	%RCX,%RBX

(804) 0x46a98e ADD	0x78(%RSP),%RBX

(804) 0x46a993 XOR	%EAX,%EAX

(804) 0x46a995 MOV	0x18(%RSP),%R9

(804) 0x46a99a MOV	%R12,0x178(%RSP)

(804) 0x46a9a2 MOV	%RDX,0x170(%RSP)

(804) 0x46a9aa JMP	46a9da

0x46a9ac NOPW	%CS:(%RAX,%RAX,1)

0x46a9bb NOPL	(%RAX,%RAX,1)

  (810) 0x46a9c0 ADD	0x188(%RSP),%RBX

  (810) 0x46a9c8 CMP	0x190(%RSP),%RAX

  (810) 0x46a9d0 LEA	0x1(%RAX),%RAX

  (810) 0x46a9d4 JE	46a75e

  (810) 0x46a9da TEST	%RDI,%RDI

  (810) 0x46a9dd JLE	46a9c0

  (810) 0x46a9df LEA	(%R12,%RAX,8),%RSI

  (810) 0x46a9e3 VMOVSD	(%R13,%RSI,8),%XMM25

  (810) 0x46a9eb VMOVSD	0x8(%R13,%RSI,8),%XMM24

  (810) 0x46a9f3 VMOVSD	0x10(%R13,%RSI,8),%XMM23

  (810) 0x46a9fb VMOVSD	0x18(%R13,%RSI,8),%XMM22

  (810) 0x46aa03 VMOVSD	0x20(%R13,%RSI,8),%XMM21

  (810) 0x46aa0b VMOVSD	0x28(%R13,%RSI,8),%XMM20

  (810) 0x46aa13 VMOVSD	0x30(%R13,%RSI,8),%XMM19

  (810) 0x46aa1b VMOVSD	0x38(%R13,%RSI,8),%XMM18

  (810) 0x46aa23 CMPQ	$0,0x28(%RSP)

  (810) 0x46aa29 MOV	%RAX,0x68(%RSP)

  (810) 0x46aa2e JE	46ab80

  (810) 0x46aa34 MOV	0x20(%RSP),%RSI

  (810) 0x46aa39 IMUL	%RAX,%RSI

  (810) 0x46aa3d VBROADCASTSD	%XMM25,%YMM26

  (810) 0x46aa43 VBROADCASTSD	%XMM24,%YMM27

  (810) 0x46aa49 VBROADCASTSD	%XMM23,%YMM28

  (810) 0x46aa4f VBROADCASTSD	%XMM22,%YMM29

  (810) 0x46aa55 VBROADCASTSD	%XMM21,%YMM30

  (810) 0x46aa5b VBROADCASTSD	%XMM20,%YMM31

  (810) 0x46aa61 VBROADCASTSD	%XMM19,%YMM1

  (810) 0x46aa67 VBROADCASTSD	%XMM18,%YMM0

  (810) 0x46aa6d XOR	%R8D,%R8D

  (810) 0x46aa70 MOV	0xc8(%RSP),%R9

  (810) 0x46aa78 MOV	0xc0(%RSP),%RAX

  (810) 0x46aa80 MOV	%RBX,0x30(%RSP)

  (810) 0x46aa85 MOV	%R11,%RBX

  (810) 0x46aa88 MOV	0xb8(%RSP),%R11

  (810) 0x46aa90 MOV	0xb0(%RSP),%R13

  (810) 0x46aa98 MOV	0xa8(%RSP),%RDI

  (810) 0x46aaa0 MOV	0xa0(%RSP),%RCX

  (810) 0x46aaa8 MOV	0xd0(%RSP),%RDX

    (811) 0x46aab0 LEA	(%RSI,%R8,1),%R10

    (811) 0x46aab4 ADD	%RDX,%R10

    (811) 0x46aab7 MOV	0x30(%RSP),%R12

    (811) 0x46aabc VMOVUPD	(%R12,%R8,8),%YMM2

    (811) 0x46aac2 VFMADD213PD	(%R15,%R8,8),%YMM26,%YMM2

    (811) 0x46aac9 MOV	0x10(%RSP),%R12

    (811) 0x46aace ADD	%R10,%R12

    (811) 0x46aad1 VFMADD231PD	(%R14,%R12,8),%YMM27,%YMM2

    (811) 0x46aad8 LEA	(%R10,%RAX,1),%R12

    (811) 0x46aadc VFMADD231PD	(%R14,%R12,8),%YMM28,%YMM2

    (811) 0x46aae3 LEA	(%R10,%R11,1),%R12

    (811) 0x46aae7 VFMADD231PD	(%R14,%R12,8),%YMM29,%YMM2

    (811) 0x46aaee LEA	(%R10,%R13,1),%R12

    (811) 0x46aaf2 VFMADD231PD	(%R14,%R12,8),%YMM30,%YMM2

    (811) 0x46aaf9 LEA	(%R10,%RDI,1),%R12

    (811) 0x46aafd VFMADD231PD	(%R14,%R12,8),%YMM31,%YMM2

    (811) 0x46ab04 LEA	(%R10,%RCX,1),%R12

    (811) 0x46ab08 VFMADD231PD	(%R14,%R12,8),%YMM1,%YMM2

    (811) 0x46ab0e ADD	%R9,%R10

    (811) 0x46ab11 VFMADD231PD	(%R14,%R10,8),%YMM0,%YMM2

    (811) 0x46ab17 VMOVUPD	%YMM2,(%R15,%R8,8)

    (811) 0x46ab1d ADD	$0x4,%R8

    (811) 0x46ab21 CMP	%RBX,%R8

    (811) 0x46ab24 JLE	46aab0

  (810) 0x46ab26 MOV	0x28(%RSP),%R8

  (810) 0x46ab2b MOV	%R8,%RSI

  (810) 0x46ab2e MOV	0x160(%RSP),%RDI

  (810) 0x46ab36 CMP	%R8,%RDI

  (810) 0x46ab39 MOV	0x18(%RSP),%R9

  (810) 0x46ab3e MOV	0x10(%RSP),%R10

  (810) 0x46ab43 MOV	%RBX,%R11

  (810) 0x46ab46 MOV	0x168(%RSP),%R13

  (810) 0x46ab4e MOV	0x178(%RSP),%R12

  (810) 0x46ab56 MOV	0x8(%RSP),%RCX

  (810) 0x46ab5b MOV	0x170(%RSP),%RDX

  (810) 0x46ab63 MOV	0x30(%RSP),%RBX

  (810) 0x46ab68 MOV	0x68(%RSP),%RAX

  (810) 0x46ab6d JE	46a9c0

  (810) 0x46ab73 JMP	46ab82

0x46ab75 NOPW	%CS:(%RAX,%RAX,1)

  (810) 0x46ab80 XOR	%ESI,%ESI

  (810) 0x46ab82 VPBROADCASTQ	%RSI,%YMM0

  (810) 0x46ab88 VMOVDQU	0x1a0(%RSP),%YMM1

  (810) 0x46ab91 VPSUBQ	%YMM0,%YMM1,%YMM0

  (810) 0x46ab95 VPCMPNLEUQ	0xa8380(%RIP),%YMM0,%K1

  (810) 0x46aba0 KORTESTB	%K1,%K1

  (810) 0x46aba4 JE	46a9c0

  (810) 0x46abaa MOV	0xd0(%RSP),%RAX

  (810) 0x46abb2 MOV	0x20(%RSP),%R8

  (810) 0x46abb7 IMUL	0x68(%RSP),%R8

  (810) 0x46abbd ADD	%RAX,%R8

  (810) 0x46abc0 ADD	%RSI,%R8

  (810) 0x46abc3 VMOVUPD	(%R14,%R8,8),%YMM0{%K1}{z}

  (810) 0x46abca VMOVAPD	%YMM0,%YMM17{%K1}

  (810) 0x46abd0 VBROADCASTSD	%XMM25,%YMM0

  (810) 0x46abd6 ADD	0xd8(%RSP),%RSI

  (810) 0x46abde VMOVUPD	(%R9,%RSI,8),%YMM1{%K1}{z}

  (810) 0x46abe5 VMOVAPD	%YMM1,%YMM16{%K1}

  (810) 0x46abeb VFMADD213PD	%YMM16,%YMM17,%YMM0

  (810) 0x46abf1 VMOVUPD	%YMM0,(%R9,%RSI,8){%K1}

  (810) 0x46abf8 MOV	0x10(%RSP),%RCX

  (810) 0x46abfd LEA	(%R8,%RCX,1),%R10

  (810) 0x46ac01 MOV	0x8(%RSP),%RCX

  (810) 0x46ac06 VMOVUPD	(%R14,%R10,8),%YMM1{%K1}{z}

  (810) 0x46ac0d VMOVAPD	%YMM1,%YMM15{%K1}

  (810) 0x46ac13 VBROADCASTSD	%XMM24,%YMM1

  (810) 0x46ac19 VMOVAPD	%YMM0,%YMM14{%K1}

  (810) 0x46ac1f VFMADD213PD	%YMM14,%YMM15,%YMM1

  (810) 0x46ac24 VMOVUPD	%YMM1,(%R9,%RSI,8){%K1}

  (810) 0x46ac2b MOV	0xc0(%RSP),%RAX

  (810) 0x46ac33 LEA	(%R8,%RAX,1),%R10

  (810) 0x46ac37 VMOVUPD	(%R14,%R10,8),%YMM0{%K1}{z}

  (810) 0x46ac3e VMOVAPD	%YMM0,%YMM13{%K1}

  (810) 0x46ac44 VBROADCASTSD	%XMM23,%YMM0

  (810) 0x46ac4a VMOVAPD	%YMM1,%YMM12{%K1}

  (810) 0x46ac50 VFMADD213PD	%YMM12,%YMM13,%YMM0

  (810) 0x46ac55 VMOVUPD	%YMM0,(%R9,%RSI,8){%K1}

  (810) 0x46ac5c MOV	0xb8(%RSP),%RAX

  (810) 0x46ac64 LEA	(%R8,%RAX,1),%R10

  (810) 0x46ac68 VMOVUPD	(%R14,%R10,8),%YMM1{%K1}{z}

  (810) 0x46ac6f VMOVAPD	%YMM1,%YMM11{%K1}

  (810) 0x46ac75 VBROADCASTSD	%XMM22,%YMM1

  (810) 0x46ac7b VMOVAPD	%YMM0,%YMM10{%K1}

  (810) 0x46ac81 VFMADD213PD	%YMM10,%YMM11,%YMM1

  (810) 0x46ac86 VMOVUPD	%YMM1,(%R9,%RSI,8){%K1}

  (810) 0x46ac8d MOV	0xb0(%RSP),%RAX

  (810) 0x46ac95 LEA	(%R8,%RAX,1),%R10

  (810) 0x46ac99 VMOVUPD	(%R14,%R10,8),%YMM0{%K1}{z}

  (810) 0x46aca0 VMOVAPD	%YMM0,%YMM9{%K1}

  (810) 0x46aca6 VBROADCASTSD	%XMM21,%YMM0

  (810) 0x46acac VMOVAPD	%YMM1,%YMM8{%K1}

  (810) 0x46acb2 VFMADD213PD	%YMM8,%YMM9,%YMM0

  (810) 0x46acb7 VMOVUPD	%YMM0,(%R9,%RSI,8){%K1}

  (810) 0x46acbe MOV	0xa8(%RSP),%RAX

  (810) 0x46acc6 LEA	(%R8,%RAX,1),%R10

  (810) 0x46acca VMOVUPD	(%R14,%R10,8),%YMM1{%K1}{z}

  (810) 0x46acd1 VMOVAPD	%YMM1,%YMM7{%K1}

  (810) 0x46acd7 VBROADCASTSD	%XMM20,%YMM1

  (810) 0x46acdd VMOVAPD	%YMM0,%YMM6{%K1}

  (810) 0x46ace3 VFMADD213PD	%YMM6,%YMM7,%YMM1

  (810) 0x46ace8 VMOVUPD	%YMM1,(%R9,%RSI,8){%K1}

  (810) 0x46acef MOV	0xa0(%RSP),%RAX

  (810) 0x46acf7 LEA	(%R8,%RAX,1),%R10

  (810) 0x46acfb MOV	0x68(%RSP),%RAX

  (810) 0x46ad00 VMOVUPD	(%R14,%R10,8),%YMM0{%K1}{z}

  (810) 0x46ad07 MOV	0x10(%RSP),%R10

  (810) 0x46ad0c VMOVAPD	%YMM0,%YMM5{%K1}

  (810) 0x46ad12 VBROADCASTSD	%XMM19,%YMM0

  (810) 0x46ad18 VMOVAPD	%YMM1,%YMM4{%K1}

  (810) 0x46ad1e VFMADD213PD	%YMM4,%YMM5,%YMM0

  (810) 0x46ad23 VMOVUPD	%YMM0,(%R9,%RSI,8){%K1}

  (810) 0x46ad2a ADD	0xc8(%RSP),%R8

  (810) 0x46ad32 VMOVUPD	(%R14,%R8,8),%YMM1{%K1}{z}

  (810) 0x46ad39 VMOVAPD	%YMM1,%YMM3{%K1}

  (810) 0x46ad3f VBROADCASTSD	%XMM18,%YMM1

  (810) 0x46ad45 VMOVUPD	0x1c0(%RSP),%YMM2

  (810) 0x46ad4e VMOVAPD	%YMM0,%YMM2{%K1}

  (810) 0x46ad54 VMOVUPD	%YMM2,0x1c0(%RSP)

  (810) 0x46ad5d VFMADD213PD	%YMM2,%YMM3,%YMM1

  (810) 0x46ad62 VMOVUPD	%YMM1,(%R9,%RSI,8){%K1}

  (810) 0x46ad69 JMP	46a9c0

0x46ad6e NOPW	%CS:(%RAX,%RAX,1)

0x46ad7d NOPL	(%RAX)

0x46ad80 LEA	0xf3589(%RIP),%RDI

0x46ad87 MOV	0x70(%RSP),%ESI

0x46ad8b LEA	-0x28(%RBP),%RSP

0x46ad8f POP	%RBX

0x46ad90 POP	%R12

0x46ad92 POP	%R13

0x46ad94 POP	%R14

0x46ad96 POP	%R15

0x46ad98 POP	%RBP

0x46ad99 VZEROUPPER

0x46ad9c JMP	403050

0x46ada1 NOPW	%CS:(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
►100.00+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run icx_1

Source file and lines	Collapse.hpp:81-83
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/loop/forall.hpp:59
/home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/src/Kripke/Kernel/LPlusTimes.cpp:57
/home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/internal/Iterators.hpp:55,177
/home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/Layout.hpp:55
/home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/View.hpp:79,110
/home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/openmp/kernel/Collapse.hpp:81-83

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 32.83 to 3.83 cycles (8.57x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 12% of vector register length is used (average across all SSE/AVX instructions).

Details

3% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX loads are used in vector version.
2% of SSE/AVX stores are used in vector version.
14% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

__kmpc_for_static_init_8@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/openmp/kernel/Collapse.hpp:81

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VZEROUPPER: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/openmp/kernel/Collapse.hpp:81

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 208 bytes. The binary function is storing 376 bytes.

General properties

nb instructions	195
nb uops	197
loop length	1222
used x86 registers	16
used mmx registers	0
used xmm registers	0
used ymm registers	1
used zmm registers	0
nb stack references	47

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	32.83 cycles
front end	32.83 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	7.30	7.20	11.00	11.00	27.50	7.20	7.10	27.50	27.50	27.50	7.20	11.00
cycles	7.30	10.53	11.00	11.00	27.50	7.20	7.10	27.50	27.50	27.50	7.20	11.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	32.83
Dispatch	27.50
Overall L1	32.83

Vectorization ratios

all	3%
load	0%
store	2%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	14%

Vector efficiency ratios

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	13%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 32.83 cycles. At this rate:

3% of peak load performance is reached (6.34 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
8% of peak store performance is reached (11.45 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 32.83 to 27.50 cycles (1.19x speedup).

ASM code

In the binary file, the address of the function is: 46a260

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
AND $-0x20,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SUB $0x200,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RDX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOVL $0,0x74(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV (%R8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,0x158(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x10(%R8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,0x58(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x18(%R8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,0x50(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x20(%R8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,0x150(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x30(%R8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,0x98(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x38(%R8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,0x90(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x60(%R8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,0x148(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x68(%R8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,0x140(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xa8(%R8),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV (%RDI),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R9,0xe0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xc0(%R8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,0x138(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xf0(%R8),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x110(%R8),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x118(%R8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,0x88(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x158(%R8),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOVQ $0,0xe8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOVQ $0x1,0x198(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA 0x1a0(%RSP),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA 0xf3fa5(%RIP),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA 0x7c(%RSP),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA 0xf0(%RSP),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA 0xe8(%RSP),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %ESI,0x78(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RAX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
CALL 403140 <__kmpc_for_static_init_8@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
ADD $0x20,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0xe8(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0xe0(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RCX,0x80(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CMP %RAX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JA 46ad80 <_ZNK14LPlusTimesSdomclIN6Kripke11ArchLayoutTINS1_12ArchT_OpenMPENS1_11LayoutT_DGZEEEEEvT_NS1_6SdomIdERKNS1_4Core3SetESB_SB_SB_RNS8_5FieldIdJNS1_6MomentENS1_5GroupENS1_4ZoneEEEERNSC_IdJNS1_9DirectionESE_SF_EEERNSC_IdJSI_SD_EEE.extracted+0xb20>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x50(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SUB 0x58(%RSP),%RCX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
MOV %RCX,0x48(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JLE 46ad80 <_ZNK14LPlusTimesSdomclIN6Kripke11ArchLayoutTINS1_12ArchT_OpenMPENS1_11LayoutT_DGZEEEEEvT_NS1_6SdomIdERKNS1_4Core3SetESB_SB_SB_RNS8_5FieldIdJNS1_6MomentENS1_5GroupENS1_4ZoneEEEERNSC_IdJNS1_9DirectionESE_SF_EEERNSC_IdJSI_SD_EEE.extracted+0xb20>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R15,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x80(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA 0x1(%RDX),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
INC %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RAX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
CMOVG %RCX,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	N/A
NOT %RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %RAX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RDX,0x130(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x58(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RCX,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %R15,%R9	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV %R15,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SAR $0x3f,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
ANDN %R15,%RAX,%RAX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1-2	0.33	N/A
MOV %RCX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
NOT %RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0x50(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RDX,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %RAX,%R8	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV %R8,0x118(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
IMUL %RDI,%RAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV %RAX,0x120(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
XOR %R10D,%R10D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
TEST %R15,%R15	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
MOV $0,%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMOVS %R15,%R8	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	N/A
MOV %RDX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %R8,%RAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
IMUL %RDI,%R8	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %RAX,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R8,0x110(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %RDX,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RDI,0x108(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x90(%RSP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x98(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SUB %RDX,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0x48(%RSP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R8,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x3,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
DEC %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RAX,0x190(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDI,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x4,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
LEA (,%R15,8),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,0x20(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
SUB %R15,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RAX,0xc8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VPBROADCASTQ %RDI,%YMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVDQU %YMM0,0x1a0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
MOV %R8,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x8,%R15	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
LEA (,%RDX,8),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R9,0x128(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (%RAX,%R9,8),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD %R14,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R9,0x78(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RSI,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SAL $0x6,%R9	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
MOV %R9,0x188(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R12,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R15,0x100(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %R15,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
IMUL %RSI,%RCX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
LEA (%RAX,%RCX,8),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD %R14,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RAX,0xf0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %RDX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RCX,0xf8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R11,0x28(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA -0x1(%R11),%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%RSI,%RSI,1),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,0xc0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (%RSI,%RSI,2),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RCX,0xb8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (,%RSI,4),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RCX,0xb0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (%RSI,%RSI,4),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RCX,0xa8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (%RAX,%RAX,2),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,0xa0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA -0x1(%R8),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,0x180(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x88(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (,%RAX,8),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,0x38(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RBX,0x40(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RSI,0x10(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R9,0x18(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R13,0x168(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDI,0x160(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JMP 46a5dc <_ZNK14LPlusTimesSdomclIN6Kripke11ArchLayoutTINS1_12ArchT_OpenMPENS1_11LayoutT_DGZEEEEEvT_NS1_6SdomIdERKNS1_4Core3SetESB_SB_SB_RNS8_5FieldIdJNS1_6MomentENS1_5GroupENS1_4ZoneEEEERNSC_IdJNS1_9DirectionESE_SF_EEERNSC_IdJSI_SD_EEE.extracted+0x37c>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XCHG %AX,%AX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA 0xf3589(%RIP),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x70(%RSP),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA -0x28(%RBP),%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
JMP 403050 <__kmpc_for_static_fini@plt>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run icx_1

Source file and lines	Collapse.hpp:81-83
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/loop/forall.hpp:59
/home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/src/Kripke/Kernel/LPlusTimes.cpp:57
/home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/internal/Iterators.hpp:55,177
/home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/Layout.hpp:55
/home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/View.hpp:79,110
/home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/openmp/kernel/Collapse.hpp:81-83

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 32.83 to 3.83 cycles (8.57x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 12% of vector register length is used (average across all SSE/AVX instructions).

Details

3% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX loads are used in vector version.
2% of SSE/AVX stores are used in vector version.
14% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

Workaround

Recompile with -mprefer-vector-width=512

CALL instructions

Detected function call instructions.

Details

__kmpc_for_static_init_8@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/openmp/kernel/Collapse.hpp:81

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VZEROUPPER: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/openmp/kernel/Collapse.hpp:81

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 208 bytes. The binary function is storing 376 bytes.

General properties

nb instructions	195
nb uops	197
loop length	1222
used x86 registers	16
used mmx registers	0
used xmm registers	0
used ymm registers	1
used zmm registers	0
nb stack references	47

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	32.83 cycles
front end	32.83 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	7.30	7.20	11.00	11.00	27.50	7.20	7.10	27.50	27.50	27.50	7.20	11.00
cycles	7.30	10.53	11.00	11.00	27.50	7.20	7.10	27.50	27.50	27.50	7.20	11.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	32.83
Dispatch	27.50
Overall L1	32.83

Vectorization ratios

all	3%
load	0%
store	2%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	14%

Vector efficiency ratios

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	13%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 32.83 cycles. At this rate:

3% of peak load performance is reached (6.34 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
8% of peak store performance is reached (11.45 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 46a260

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
AND $-0x20,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SUB $0x200,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RDX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOVL $0,0x74(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV (%R8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,0x158(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x10(%R8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,0x58(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x18(%R8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,0x50(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x20(%R8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,0x150(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x30(%R8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,0x98(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x38(%R8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,0x90(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x60(%R8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,0x148(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x68(%R8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,0x140(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xa8(%R8),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV (%RDI),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R9,0xe0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xc0(%R8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,0x138(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xf0(%R8),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x110(%R8),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x118(%R8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,0x88(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x158(%R8),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOVQ $0,0xe8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOVQ $0x1,0x198(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA 0x1a0(%RSP),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA 0xf3fa5(%RIP),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA 0x7c(%RSP),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA 0xf0(%RSP),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA 0xe8(%RSP),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %ESI,0x78(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RAX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
CALL 403140 <__kmpc_for_static_init_8@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
ADD $0x20,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0xe8(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0xe0(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RCX,0x80(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CMP %RAX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JA 46ad80 <_ZNK14LPlusTimesSdomclIN6Kripke11ArchLayoutTINS1_12ArchT_OpenMPENS1_11LayoutT_DGZEEEEEvT_NS1_6SdomIdERKNS1_4Core3SetESB_SB_SB_RNS8_5FieldIdJNS1_6MomentENS1_5GroupENS1_4ZoneEEEERNSC_IdJNS1_9DirectionESE_SF_EEERNSC_IdJSI_SD_EEE.extracted+0xb20>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x50(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SUB 0x58(%RSP),%RCX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
MOV %RCX,0x48(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JLE 46ad80 <_ZNK14LPlusTimesSdomclIN6Kripke11ArchLayoutTINS1_12ArchT_OpenMPENS1_11LayoutT_DGZEEEEEvT_NS1_6SdomIdERKNS1_4Core3SetESB_SB_SB_RNS8_5FieldIdJNS1_6MomentENS1_5GroupENS1_4ZoneEEEERNSC_IdJNS1_9DirectionESE_SF_EEERNSC_IdJSI_SD_EEE.extracted+0xb20>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R15,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x80(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA 0x1(%RDX),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
INC %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RAX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
CMOVG %RCX,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	N/A
NOT %RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %RAX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RDX,0x130(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x58(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RCX,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %R15,%R9	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV %R15,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SAR $0x3f,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
ANDN %R15,%RAX,%RAX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1-2	0.33	N/A
MOV %RCX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
NOT %RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0x50(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RDX,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %RAX,%R8	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV %R8,0x118(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
IMUL %RDI,%RAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV %RAX,0x120(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
XOR %R10D,%R10D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
TEST %R15,%R15	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
MOV $0,%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMOVS %R15,%R8	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	N/A
MOV %RDX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %R8,%RAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
IMUL %RDI,%R8	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %RAX,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R8,0x110(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %RDX,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RDI,0x108(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x90(%RSP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x98(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SUB %RDX,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0x48(%RSP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R8,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x3,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
DEC %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RAX,0x190(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDI,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x4,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
LEA (,%R15,8),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,0x20(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
SUB %R15,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RAX,0xc8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VPBROADCASTQ %RDI,%YMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVDQU %YMM0,0x1a0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
MOV %R8,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x8,%R15	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
LEA (,%RDX,8),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R9,0x128(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (%RAX,%R9,8),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD %R14,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R9,0x78(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RSI,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SAL $0x6,%R9	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
MOV %R9,0x188(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R12,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R15,0x100(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %R15,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
IMUL %RSI,%RCX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
LEA (%RAX,%RCX,8),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD %R14,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RAX,0xf0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %RDX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RCX,0xf8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R11,0x28(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA -0x1(%R11),%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%RSI,%RSI,1),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,0xc0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (%RSI,%RSI,2),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RCX,0xb8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (,%RSI,4),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RCX,0xb0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (%RSI,%RSI,4),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RCX,0xa8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (%RAX,%RAX,2),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,0xa0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA -0x1(%R8),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,0x180(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x88(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (,%RAX,8),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,0x38(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RBX,0x40(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RSI,0x10(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R9,0x18(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R13,0x168(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDI,0x160(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JMP 46a5dc <_ZNK14LPlusTimesSdomclIN6Kripke11ArchLayoutTINS1_12ArchT_OpenMPENS1_11LayoutT_DGZEEEEEvT_NS1_6SdomIdERKNS1_4Core3SetESB_SB_SB_RNS8_5FieldIdJNS1_6MomentENS1_5GroupENS1_4ZoneEEEERNSC_IdJNS1_9DirectionESE_SF_EEERNSC_IdJSI_SD_EEE.extracted+0x37c>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XCHG %AX,%AX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA 0xf3589(%RIP),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x70(%RSP),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA -0x28(%RBP),%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
JMP 403050 <__kmpc_for_static_fini@plt>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

Name	Coverage (%)	Time (s)
▼void LPlusTimesSdom::operator() >(Kripke::ArchLayoutT, Kripke::SdomId, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Set const&, K...–	1.50	0.17
▼Loop 804 - forall.hpp:59-59 - exec–	0.00	0.00
▼Loop 810 - forall.hpp:59-59 - exec–	0.00	0.01
○Loop 811 - forall.hpp:59-59 - exec	1.43	0.16
▼Loop 807 - forall.hpp:59-59 - exec–	0.00	0.00
○Loop 809 - forall.hpp:59-59 - exec	0.06	0.01
○Loop 808 - forall.hpp:59-59 - exec	0.00	0.00
▼Loop 805 - forall.hpp:59-59 - exec–	0.00	0.00
○Loop 806 - forall.hpp:59-59 - exec	0.00	0.00

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

CALL instructions

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Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code