OV - exec - Loop 2337

	Loop Id: 2337	Module: exec	Source: stl_algobase.h:438-1146 [...]	Coverage: 0.01%

0x4e328b LEA	(%R13,%R13,4),%R12

0x4e3290 SAL	$0x2,%R12

0x4e3294 MOV	%R12,%RDI

0x4e3297 CALL	403220 <_Znwm@plt>

0x4e329c MOVQ	$0,(%RAX)

0x4e32a3 MOVQ	$0,0x8(%RAX)

0x4e32ab MOVL	$0,0x10(%RAX)

0x4e32b2 MOV	%R13D,%R15D

0x4e32b5 MOV	%RAX,%RBX

0x4e32b8 LEA	(%RAX,%R12,1),%RCX

0x4e32bc LEA	0x14(%RAX),%R10

0x4e32c0 CMP	$0x1,%R13

0x4e32c4 JE	4e3468

0x4e32ca MOV	%RCX,%R8

0x4e32cd SUB	%R10,%R8

0x4e32d0 SUB	$0x14,%R8

0x4e32d4 SHR	$0x2,%R8

0x4e32d8 MOV	$0xccccccccccccccd,%RSI

0x4e32e2 IMUL	%RSI,%R8

0x4e32e6 INC	%R8

0x4e32e9 AND	$0x7,%R8D

0x4e32ed JE	4e33bd

0x4e32f3 CMP	$0x1,%R8

0x4e32f7 JE	4e339f

0x4e32fd CMP	$0x2,%R8

0x4e3301 JE	4e3389

0x4e3307 CMP	$0x3,%R8

0x4e330b JE	4e3374

0x4e330d CMP	$0x4,%R8

0x4e3311 JE	4e335f

0x4e3313 CMP	$0x5,%R8

0x4e3317 JE	4e334a

0x4e3319 CMP	$0x6,%R8

0x4e331d JE	4e3334

0x4e331f VMOVDQU	(%RAX),%XMM0

0x4e3323 MOV	0x10(%RAX),%R9D

0x4e3327 VMOVDQU	%XMM0,0x14(%RAX)

0x4e332c MOV	%R9D,0x10(%R10)

0x4e3330 LEA	0x28(%RAX),%R10

0x4e3334 VMOVDQU	(%RBX),%XMM1

0x4e3338 ADD	$0x14,%R10

0x4e333c VMOVDQU	%XMM1,-0x14(%R10)

0x4e3342 MOV	0x10(%RBX),%R11D

0x4e3346 MOV	%R11D,-0x4(%R10)

0x4e334a VMOVDQU	(%RBX),%XMM2

0x4e334e ADD	$0x14,%R10

0x4e3352 VMOVDQU	%XMM2,-0x14(%R10)

0x4e3358 MOV	0x10(%RBX),%EAX

0x4e335b MOV	%EAX,-0x4(%R10)

0x4e335f VMOVDQU	(%RBX),%XMM3

0x4e3363 ADD	$0x14,%R10

0x4e3367 VMOVDQU	%XMM3,-0x14(%R10)

0x4e336d MOV	0x10(%RBX),%EDI

0x4e3370 MOV	%EDI,-0x4(%R10)

0x4e3374 VMOVDQU	(%RBX),%XMM4

0x4e3378 ADD	$0x14,%R10

0x4e337c VMOVDQU	%XMM4,-0x14(%R10)

0x4e3382 MOV	0x10(%RBX),%EDX

0x4e3385 MOV	%EDX,-0x4(%R10)

0x4e3389 VMOVDQU	(%RBX),%XMM5

0x4e338d ADD	$0x14,%R10

0x4e3391 VMOVDQU	%XMM5,-0x14(%R10)

0x4e3397 MOV	0x10(%RBX),%R8D

0x4e339b MOV	%R8D,-0x4(%R10)

0x4e339f VMOVDQU	(%RBX),%XMM6

0x4e33a3 ADD	$0x14,%R10

0x4e33a7 VMOVDQU	%XMM6,-0x14(%R10)

0x4e33ad MOV	0x10(%RBX),%ESI

0x4e33b0 MOV	%ESI,-0x4(%R10)

0x4e33b4 CMP	%R10,%RCX

0x4e33b7 JE	4e3468

  (2339) 0x4e33bd VMOVDQU	(%RBX),%XMM7

  (2339) 0x4e33c1 ADD	$0xa0,%R10

  (2339) 0x4e33c8 VMOVDQU	%XMM7,-0xa0(%R10)

  (2339) 0x4e33d1 MOV	0x10(%RBX),%R9D

  (2339) 0x4e33d5 MOV	%R9D,-0x90(%R10)

  (2339) 0x4e33dc VMOVDQU	(%RBX),%XMM8

  (2339) 0x4e33e0 VMOVDQU	%XMM8,-0x8c(%R10)

  (2339) 0x4e33e9 MOV	0x10(%RBX),%R11D

  (2339) 0x4e33ed MOV	%R11D,-0x7c(%R10)

  (2339) 0x4e33f1 VMOVDQU	(%RBX),%XMM9

  (2339) 0x4e33f5 VMOVDQU	%XMM9,-0x78(%R10)

  (2339) 0x4e33fb MOV	0x10(%RBX),%EAX

  (2339) 0x4e33fe MOV	%EAX,-0x68(%R10)

  (2339) 0x4e3402 VMOVDQU	(%RBX),%XMM10

  (2339) 0x4e3406 VMOVDQU	%XMM10,-0x64(%R10)

  (2339) 0x4e340c MOV	0x10(%RBX),%EDI

  (2339) 0x4e340f MOV	%EDI,-0x54(%R10)

  (2339) 0x4e3413 VMOVDQU	(%RBX),%XMM11

  (2339) 0x4e3417 VMOVDQU	%XMM11,-0x50(%R10)

  (2339) 0x4e341d MOV	0x10(%RBX),%EDX

  (2339) 0x4e3420 MOV	%EDX,-0x40(%R10)

  (2339) 0x4e3424 VMOVDQU	(%RBX),%XMM12

  (2339) 0x4e3428 VMOVDQU	%XMM12,-0x3c(%R10)

  (2339) 0x4e342e MOV	0x10(%RBX),%R8D

  (2339) 0x4e3432 MOV	%R8D,-0x2c(%R10)

  (2339) 0x4e3436 VMOVDQU	(%RBX),%XMM13

  (2339) 0x4e343a VMOVDQU	%XMM13,-0x28(%R10)

  (2339) 0x4e3440 MOV	0x10(%RBX),%ESI

  (2339) 0x4e3443 MOV	%ESI,-0x18(%R10)

  (2339) 0x4e3447 VMOVDQU	(%RBX),%XMM14

  (2339) 0x4e344b VMOVDQU	%XMM14,-0x14(%R10)

  (2339) 0x4e3451 MOV	0x10(%RBX),%R9D

  (2339) 0x4e3455 MOV	%R9D,-0x4(%R10)

  (2339) 0x4e3459 CMP	%R10,%RCX

  (2339) 0x4e345c JNE	4e33bd

0x4e3462 NOPW	(%RAX,%RAX,1)

0x4e3468 MOV	0x28(%R14),%RSI

0x4e346c MOV	-0x50(%RBP),%RCX

0x4e3470 MOV	-0x48(%RBP),%RDX

0x4e3474 MOV	%RBX,%R8

0x4e3477 MOV	%R15D,%EDI

0x4e347a CALL	403370 <MPI_Testany@plt>

0x4e347f MOV	-0x34(%RBP),%R15D

0x4e3483 TEST	%R15D,%R15D

0x4e3486 JNE	4e34a8

0x4e34a8 MOVSXD	-0x38(%RBP),%R10

0x4e34ac MOV	0x28(%R14),%R11

0x4e34b0 MOV	0x40(%R14),%RCX

0x4e34b4 LEA	(%R11,%R10,4),%RDI

0x4e34b8 MOV	0x30(%R14),%RAX

0x4e34bc LEA	0x4(%RDI),%RSI

0x4e34c0 MOV	(%RCX,%R10,4),%R15D

0x4e34c4 MOV	%R10,%R9

0x4e34c7 CMP	%RSI,%RAX

0x4e34ca JE	4e34f0

0x4e34cc MOV	%RAX,%R8

0x4e34cf SUB	%RSI,%R8

0x4e34d2 CMP	$0x4,%R8

0x4e34d6 JLE	4e3680

0x4e34dc MOV	%R8,%RDX

0x4e34df CALL	403440 <memmove@plt>

0x4e34e4 MOV	0x40(%R14),%RCX

0x4e34e8 MOV	0x30(%R14),%RAX

0x4e34ec MOVSXD	-0x38(%RBP),%R9

0x4e34f0 LEA	(%RCX,%R9,4),%RDI

0x4e34f4 MOV	0x48(%R14),%R10

0x4e34f8 SUB	$0x4,%RAX

0x4e34fc LEA	0x4(%RDI),%RSI

0x4e3500 MOV	%RAX,0x30(%R14)

0x4e3504 CMP	%RSI,%R10

0x4e3507 JE	4e3522

0x4e3509 MOV	%R10,%RDX

0x4e350c SUB	%RSI,%RDX

0x4e350f CMP	$0x4,%RDX

0x4e3513 JLE	4e3694

0x4e3519 CALL	403440 <memmove@plt>

0x4e351e MOV	0x48(%R14),%R10

0x4e3522 MOV	0x60(%R14),%RDI

0x4e3526 MOV	0x58(%R14),%R11

0x4e352a MOV	%RDI,%R8

0x4e352d SUB	$0x4,%R10

0x4e3531 SUB	%R11,%R8

0x4e3534 MOV	%R10,0x48(%R14)

0x4e3538 SAR	$0x2,%R8

0x4e353c CMP	%RDI,%R11

0x4e353f JE	4e3648

0x4e3545 LEA	-0x1(%R8),%RDX

0x4e3549 XOR	%ECX,%ECX

0x4e354b AND	$0x7,%EDX

0x4e354e CMP	%R15D,(%R11)

0x4e3551 JE	4e3668

0x4e3557 MOV	$0x1,%ECX

0x4e355c CMP	%R8,%RCX

0x4e355f JAE	4e3648

0x4e3565 TEST	%RDX,%RDX

0x4e3568 JE	4e35e5

0x4e356a CMP	$0x1,%RDX

0x4e356e JE	4e35d3

0x4e3570 CMP	$0x2,%RDX

0x4e3574 JE	4e35c6

0x4e3576 CMP	$0x3,%RDX

0x4e357a JE	4e35b9

0x4e357c CMP	$0x4,%RDX

0x4e3580 JE	4e35ac

0x4e3582 CMP	$0x5,%RDX

0x4e3586 JE	4e359f

0x4e3588 CMP	$0x6,%RDX

0x4e358c JNE	4e3672

0x4e3592 CMP	%R15D,(%R11,%RCX,4)

0x4e3596 JE	4e3668

0x4e359c INC	%RCX

0x4e359f CMP	%R15D,(%R11,%RCX,4)

0x4e35a3 JE	4e3668

0x4e35a9 INC	%RCX

0x4e35ac CMP	%R15D,(%R11,%RCX,4)

0x4e35b0 JE	4e3668

0x4e35b6 INC	%RCX

0x4e35b9 CMP	%R15D,(%R11,%RCX,4)

0x4e35bd JE	4e3668

0x4e35c3 INC	%RCX

0x4e35c6 CMP	%R15D,(%R11,%RCX,4)

0x4e35ca JE	4e3668

0x4e35d0 INC	%RCX

0x4e35d3 CMP	%R15D,(%R11,%RCX,4)

0x4e35d7 JE	4e3668

0x4e35dd INC	%RCX

0x4e35e0 CMP	%R8,%RCX

0x4e35e3 JAE	4e3648

  (2338) 0x4e35e5 CMP	%R15D,(%R11,%RCX,4)

  (2338) 0x4e35e9 JE	4e3668

  (2338) 0x4e35eb LEA	0x1(%RCX),%R9

  (2338) 0x4e35ef MOV	%R9,%RCX

  (2338) 0x4e35f2 CMP	%R15D,(%R11,%R9,4)

  (2338) 0x4e35f6 JE	4e3668

  (2338) 0x4e35f8 INC	%RCX

  (2338) 0x4e35fb CMP	%R15D,(%R11,%RCX,4)

  (2338) 0x4e35ff JE	4e3668

  (2338) 0x4e3601 LEA	0x2(%R9),%RCX

  (2338) 0x4e3605 CMP	%R15D,0x8(%R11,%R9,4)

  (2338) 0x4e360a JE	4e3668

  (2338) 0x4e360c LEA	0x3(%R9),%RCX

  (2338) 0x4e3610 CMP	%R15D,0xc(%R11,%R9,4)

  (2338) 0x4e3615 JE	4e3668

  (2338) 0x4e3617 LEA	0x4(%R9),%RCX

  (2338) 0x4e361b CMP	%R15D,0x10(%R11,%R9,4)

  (2338) 0x4e3620 JE	4e3668

  (2338) 0x4e3622 LEA	0x5(%R9),%RCX

  (2338) 0x4e3626 CMP	%R15D,0x14(%R11,%R9,4)

  (2338) 0x4e362b JE	4e3668

  (2338) 0x4e362d LEA	0x6(%R9),%RCX

  (2338) 0x4e3631 CMP	%R15D,0x18(%R11,%R9,4)

  (2338) 0x4e3636 JE	4e3668

  (2338) 0x4e3638 LEA	0x7(%R9),%RCX

  (2338) 0x4e363c CMP	%R8,%RCX

  (2338) 0x4e363f JB	4e35e5

0x4e3641 NOPL	(%RAX)

0x4e3648 MOV	%R12,%RSI

0x4e364b MOV	%RBX,%RDI

0x4e364e DEC	%R13

0x4e3651 CALL	403230 <_ZdlPvm@plt>

0x4e3656 TEST	%R13D,%R13D

0x4e3659 JG	4e328b

0x4e3668 MOV	0x70(%R14),%R15

0x4e366c DECL	(%R15,%RCX,4)

0x4e3670 JMP	4e3648

0x4e3672 CMP	%R15D,0x4(%R11)

0x4e3676 JE	4e3668

0x4e3678 INC	%RCX

0x4e367b JMP	4e3592

0x4e3680 JNE	4e34f0

0x4e3686 MOV	0x4(%RDI),%EDX

0x4e3689 MOV	%EDX,(%RDI)

0x4e368b MOVSXD	-0x38(%RBP),%R9

0x4e368f JMP	4e34f0

0x4e3694 JNE	4e3522

0x4e369a MOV	0x4(%RDI),%ESI

0x4e369d MOV	%ESI,(%RDI)

0x4e369f JMP	4e3522

/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/stl_construct.h: 119 - 119

--------------------------------------------------------------------------------

119:       ::new((void*)__p) _Tp(std::forward<_Args>(__args)...);

/home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/src/Kripke/ParallelComm.cpp: 219 - 241

--------------------------------------------------------------------------------

219:   while(!done && num_requests > 0){

[...]

226:     MPI_Testany(num_requests, &recv_requests[0], &index, &complete_flag, &recv_status[0]);

227:

228:     if(complete_flag != 0){

229:

230:       // get subdomain that this completed for

231:       int sdom_id = recv_subdomains[index];

[...]

239:       for(size_t i = 0;i < queue_sdom_ids.size();++ i){

240:         if(queue_sdom_ids[i] == sdom_id){

241:           queue_depends[i] --;

/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/stl_uninitialized.h: 667 - 667

--------------------------------------------------------------------------------

667: 	      ++__first;

/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/stl_vector.h: 385 - 1131

--------------------------------------------------------------------------------

385:       _M_deallocate(pointer __p, size_t __n)

[...]

400: 	this->_M_impl._M_end_of_storage = this->_M_impl._M_start + __n;

[...]

992:       size() const _GLIBCXX_NOEXCEPT

993:       { return size_type(this->_M_impl._M_finish - this->_M_impl._M_start); }

[...]

1131: 	return *(this->_M_impl._M_start + __n);

/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/new_allocator.h: 151 - 172

--------------------------------------------------------------------------------

151: 	return static_cast<_Tp*>(_GLIBCXX_OPERATOR_NEW(__n * sizeof(_Tp)));

[...]

172: 	_GLIBCXX_OPERATOR_DELETE(_GLIBCXX_SIZED_DEALLOC(__p, __n));

/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/stl_algobase.h: 438 - 1146

--------------------------------------------------------------------------------

438: 	{ *__to = std::move(*__from); }

[...]

450: 	  const ptrdiff_t _Num = __last - __first;

451: 	  if (__builtin_expect(_Num > 1, true))

452: 	    __builtin_memmove(__result, __first, sizeof(_Tp) * _Num);

453: 	  else if (_Num == 1)

[...]

939:       for (; __first != __last; ++__first)

940: 	*__first = __value;

[...]

1146:       if (__n <= 0)

/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/stl_iterator.h: 1068 - 1139

--------------------------------------------------------------------------------

1068:       : _M_current(__i) { }

[...]

1139:       { return __normal_iterator(_M_current + __n); }

/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/vector.tcc: 184 - 186

--------------------------------------------------------------------------------

184:       if (__position + 1 != end())

185: 	_GLIBCXX_MOVE3(__position + 1, end(), __position);

186:       --this->_M_impl._M_finish;

Coverage (%)	Name	Source Location	Module
►100.00+	Kripke::SweepComm::readySubdom[...]	SweepComm.cpp:65	exec
○	Kripke::SweepSolver(Kripke::Co[...]	stl_vector.h:992	exec
○	Kripke::SteadyStateSolver(Krip[...]	stl_vector.h:300	exec
○	main	kripke.cpp:485	exec
○	__libc_start_call_main		libc.so.6

Path /

Metric	Value
CQA speedup if no scalar integer	1.90
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	11.69
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.75
Bottlenecks	micro-operation queue,
Function	Kripke::ParallelComm::testRecieves()
Source	stl_construct.h:119-119,ParallelComm.cpp:219-219,ParallelComm.cpp:226-228,ParallelComm.cpp:231-231,ParallelComm.cpp:239-241,stl_uninitialized.h:667-667,stl_vector.h:385-385,stl_vector.h:400-400,stl_vector.h:992-993,stl_vector.h:1131-1131,new_allocator.h:151-151,new_allocator.h:172-172,stl_algobase.h:438-438,stl_algobase.h:450-453,stl_algobase.h:939-940,stl_algobase.h:1146-1146,stl_iterator.h:1068-1068,stl_iterator.h:1139-1139,vector.tcc:184-186
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	33.33
CQA cycles if no scalar integer	17.50
CQA cycles if FP arith vectorized	33.33
CQA cycles if fully vectorized	2.85
Front-end cycles	33.33
P0 cycles	19.00
P1 cycles	14.00
P2 cycles	14.33
P3 cycles	14.33
P4 cycles	13.50
P5 cycles	14.00
P6 cycles	19.00
P7 cycles	13.50
P8 cycles	13.50
P9 cycles	13.50
P10 cycles	14.00
P11 cycles	14.33
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	187.00
Nb uops	194.00
Nb loads	43.00
Nb stores	22.00
Nb stack references	4.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	14.88
Bytes prefetched	0.00
Bytes loaded	308.00
Bytes stored	188.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	19.18
Vectorization ratio load	31.82
Vectorization ratio store	31.82
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.78
Vector-efficiency ratio store	12.78
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	10.64

Metric	Value
CQA speedup if no scalar integer	1.90
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	11.69
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.75
Bottlenecks	micro-operation queue,
Function	Kripke::ParallelComm::testRecieves()
Source	stl_construct.h:119-119,ParallelComm.cpp:219-219,ParallelComm.cpp:226-228,ParallelComm.cpp:231-231,ParallelComm.cpp:239-241,stl_uninitialized.h:667-667,stl_vector.h:385-385,stl_vector.h:400-400,stl_vector.h:992-993,stl_vector.h:1131-1131,new_allocator.h:151-151,new_allocator.h:172-172,stl_algobase.h:438-438,stl_algobase.h:450-453,stl_algobase.h:939-940,stl_algobase.h:1146-1146,stl_iterator.h:1068-1068,stl_iterator.h:1139-1139,vector.tcc:184-186
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	33.33
CQA cycles if no scalar integer	17.50
CQA cycles if FP arith vectorized	33.33
CQA cycles if fully vectorized	2.85
Front-end cycles	33.33
P0 cycles	19.00
P1 cycles	14.00
P2 cycles	14.33
P3 cycles	14.33
P4 cycles	13.50
P5 cycles	14.00
P6 cycles	19.00
P7 cycles	13.50
P8 cycles	13.50
P9 cycles	13.50
P10 cycles	14.00
P11 cycles	14.33
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	187.00
Nb uops	194.00
Nb loads	43.00
Nb stores	22.00
Nb stack references	4.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	14.88
Bytes prefetched	0.00
Bytes loaded	308.00
Bytes stored	188.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	19.18
Vectorization ratio load	31.82
Vectorization ratio store	31.82
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.78
Vector-efficiency ratio store	12.78
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	10.64

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	Kripke::ParallelComm::testRecieves()
Source file and lines	stl_algobase.h:438-1146
Module	exec

The loop is defined in:

/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/stl_construct.h:119
/home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/src/Kripke/ParallelComm.cpp:219,226-231,239-241
/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/stl_uninitialized.h:667
/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/stl_vector.h:385,400,992-993,1131
/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/new_allocator.h:151,172
/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/stl_algobase.h:438,450-453,939-940,1146
/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/stl_iterator.h:1068,1139
/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/vector.tcc:184-186

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 28160 paths individually, rerun with max-paths=28160
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 28160 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 33.33 to 17.50 cycles (1.90x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 12% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 33.33 to 2.85 cycles (11.69x speedup).

Details

19% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

31% of SSE/AVX loads are used in vector version.
31% of SSE/AVX stores are used in vector version.
0% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

MPI_Testany@plt: 1 occurrences►
memmove@plt: 2 occurrences►
- /cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/stl_algobase.h:452
operator delete(void*, unsigned long): 1 occurrences►
- /cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/new_allocator.h:172
operator new(unsigned long): 1 occurrences►

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DEC: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/src/Kripke/ParallelComm.cpp:241

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 308 bytes. The binary loop is storing 188 bytes.

General properties

nb instructions	187
nb uops	194
loop length	751
used x86 registers	15
used mmx registers	0
used xmm registers	7
used ymm registers	0
used zmm registers	0
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	33.33 cycles
front end	33.33 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	19.00	14.00	14.33	14.33	13.50	14.00	19.00	13.50	13.50	13.50	14.00	14.33
cycles	19.00	14.00	14.33	14.33	13.50	14.00	19.00	13.50	13.50	13.50	14.00	14.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	33.33
Dispatch	19.00
Overall L1	33.33

Vectorization ratios

all	19%
load	31%
store	31%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 33.33 cycles. At this rate:

4% of peak load performance is reached (9.24 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (5.64 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 33.33 to 19.00 cycles (1.75x speedup).

ASM code

In the binary file, the address of the loop is: 4e328b

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
LEA (%R13,%R13,4),%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SAL $0x2,%R12	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
MOV %R12,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 403220 <_Znwm@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOVQ $0,(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOVQ $0,0x8(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOVL $0,0x10(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %R13D,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RAX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%RAX,%R12,1),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA 0x14(%RAX),%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP $0x1,%R13	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4e3468 <_ZN6Kripke12ParallelComm12testRecievesEv+0x218>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RCX,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %R10,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
SUB $0x14,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x2,%R8	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
MOV $0xccccccccccccccd,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	scal (12.5%)
IMUL %RSI,%R8	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
INC %R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $0x7,%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
JE 4e33bd <_ZN6Kripke12ParallelComm12testRecievesEv+0x16d>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x1,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4e339f <_ZN6Kripke12ParallelComm12testRecievesEv+0x14f>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x2,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4e3389 <_ZN6Kripke12ParallelComm12testRecievesEv+0x139>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x3,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4e3374 <_ZN6Kripke12ParallelComm12testRecievesEv+0x124>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x4,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4e335f <_ZN6Kripke12ParallelComm12testRecievesEv+0x10f>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x5,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4e334a <_ZN6Kripke12ParallelComm12testRecievesEv+0xfa>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x6,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4e3334 <_ZN6Kripke12ParallelComm12testRecievesEv+0xe4>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVDQU (%RAX),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
MOV 0x10(%RAX),%R9D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVDQU %XMM0,0x14(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOV %R9D,0x10(%R10)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
LEA 0x28(%RAX),%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVDQU (%RBX),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
ADD $0x14,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVDQU %XMM1,-0x14(%R10)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOV 0x10(%RBX),%R11D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R11D,-0x4(%R10)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VMOVDQU (%RBX),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
ADD $0x14,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVDQU %XMM2,-0x14(%R10)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOV 0x10(%RBX),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %EAX,-0x4(%R10)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VMOVDQU (%RBX),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
ADD $0x14,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVDQU %XMM3,-0x14(%R10)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOV 0x10(%RBX),%EDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %EDI,-0x4(%R10)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VMOVDQU (%RBX),%XMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
ADD $0x14,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVDQU %XMM4,-0x14(%R10)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOV 0x10(%RBX),%EDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV %EDX,-0x4(%R10)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VMOVDQU (%RBX),%XMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
ADD $0x14,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVDQU %XMM5,-0x14(%R10)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOV 0x10(%RBX),%R8D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R8D,-0x4(%R10)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VMOVDQU (%RBX),%XMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
ADD $0x14,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVDQU %XMM6,-0x14(%R10)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOV 0x10(%RBX),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV %ESI,-0x4(%R10)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CMP %R10,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4e3468 <_ZN6Kripke12ParallelComm12testRecievesEv+0x218>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x28(%R14),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x50(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x48(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %RBX,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R15D,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 403370 <MPI_Testany@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x34(%RBP),%R15D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
TEST %R15D,%R15D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
JNE 4e34a8 <_ZN6Kripke12ParallelComm12testRecievesEv+0x258>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOVSXD -0x38(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x28(%R14),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x40(%R14),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%R11,%R10,4),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x30(%R14),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA 0x4(%RDI),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV (%RCX,%R10,4),%R15D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R10,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RSI,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4e34f0 <_ZN6Kripke12ParallelComm12testRecievesEv+0x2a0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RAX,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %RSI,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP $0x4,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JLE 4e3680 <_ZN6Kripke12ParallelComm12testRecievesEv+0x430>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R8,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CALL 403440 <memmove@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV 0x40(%R14),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x30(%R14),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOVSXD -0x38(%RBP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%RCX,%R9,4),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x48(%R14),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SUB $0x4,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA 0x4(%RDI),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,0x30(%R14)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CMP %RSI,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4e3522 <_ZN6Kripke12ParallelComm12testRecievesEv+0x2d2>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R10,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SUB %RSI,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
CMP $0x4,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JLE 4e3694 <_ZN6Kripke12ParallelComm12testRecievesEv+0x444>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CALL 403440 <memmove@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV 0x48(%R14),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x60(%R14),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x58(%R14),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RDI,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB $0x4,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %R11,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R10,0x48(%R14)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
SAR $0x2,%R8	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
CMP %RDI,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4e3648 <_ZN6Kripke12ParallelComm12testRecievesEv+0x3f8>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA -0x1(%R8),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $0x7,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (6.3%)
CMP %R15D,(%R11)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (6.3%)
JE 4e3668 <_ZN6Kripke12ParallelComm12testRecievesEv+0x418>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV $0x1,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP %R8,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JAE 4e3648 <_ZN6Kripke12ParallelComm12testRecievesEv+0x3f8>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
TEST %RDX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JE 4e35e5 <_ZN6Kripke12ParallelComm12testRecievesEv+0x395>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x1,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4e35d3 <_ZN6Kripke12ParallelComm12testRecievesEv+0x383>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x2,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4e35c6 <_ZN6Kripke12ParallelComm12testRecievesEv+0x376>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x3,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4e35b9 <_ZN6Kripke12ParallelComm12testRecievesEv+0x369>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x4,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4e35ac <_ZN6Kripke12ParallelComm12testRecievesEv+0x35c>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x5,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4e359f <_ZN6Kripke12ParallelComm12testRecievesEv+0x34f>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x6,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JNE 4e3672 <_ZN6Kripke12ParallelComm12testRecievesEv+0x422>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP %R15D,(%R11,%RCX,4)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (6.3%)
JE 4e3668 <_ZN6Kripke12ParallelComm12testRecievesEv+0x418>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
INC %RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R15D,(%R11,%RCX,4)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (6.3%)
JE 4e3668 <_ZN6Kripke12ParallelComm12testRecievesEv+0x418>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
INC %RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R15D,(%R11,%RCX,4)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (6.3%)
JE 4e3668 <_ZN6Kripke12ParallelComm12testRecievesEv+0x418>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
INC %RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R15D,(%R11,%RCX,4)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (6.3%)
JE 4e3668 <_ZN6Kripke12ParallelComm12testRecievesEv+0x418>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
INC %RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R15D,(%R11,%RCX,4)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (6.3%)
JE 4e3668 <_ZN6Kripke12ParallelComm12testRecievesEv+0x418>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
INC %RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R15D,(%R11,%RCX,4)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (6.3%)
JE 4e3668 <_ZN6Kripke12ParallelComm12testRecievesEv+0x418>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
INC %RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R8,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JAE 4e3648 <_ZN6Kripke12ParallelComm12testRecievesEv+0x3f8>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R12,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
DEC %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 403230 <_ZdlPvm@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
TEST %R13D,%R13D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
JG 4e328b <_ZN6Kripke12ParallelComm12testRecievesEv+0x3b>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x70(%R14),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
DECL (%R15,%RCX,4)	3	0.20	0.20	0.33	0.33	0.50	0.20	0.20	0.50	0.50	0.50	0.20	0.33	1	0.50	scal (6.3%)
JMP 4e3648 <_ZN6Kripke12ParallelComm12testRecievesEv+0x3f8>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
CMP %R15D,0x4(%R11)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (6.3%)
JE 4e3668 <_ZN6Kripke12ParallelComm12testRecievesEv+0x418>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
INC %RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JMP 4e3592 <_ZN6Kripke12ParallelComm12testRecievesEv+0x342>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
JNE 4e34f0 <_ZN6Kripke12ParallelComm12testRecievesEv+0x2a0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x4(%RDI),%EDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV %EDX,(%RDI)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOVSXD -0x38(%RBP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JMP 4e34f0 <_ZN6Kripke12ParallelComm12testRecievesEv+0x2a0>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
JNE 4e3522 <_ZN6Kripke12ParallelComm12testRecievesEv+0x2d2>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x4(%RDI),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV %ESI,(%RDI)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
JMP 4e3522 <_ZN6Kripke12ParallelComm12testRecievesEv+0x2d2>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A

Function	Kripke::ParallelComm::testRecieves()
Source file and lines	stl_algobase.h:438-1146
Module	exec

The loop is defined in:

/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/stl_construct.h:119
/home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/src/Kripke/ParallelComm.cpp:219,226-231,239-241
/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/stl_uninitialized.h:667
/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/stl_vector.h:385,400,992-993,1131
/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/new_allocator.h:151,172
/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/stl_algobase.h:438,450-453,939-940,1146
/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/stl_iterator.h:1068,1139
/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/vector.tcc:184-186

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 28160 paths individually, rerun with max-paths=28160
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

19% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

31% of SSE/AVX loads are used in vector version.
31% of SSE/AVX stores are used in vector version.
0% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

MPI_Testany@plt: 1 occurrences►
memmove@plt: 2 occurrences►
- /cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/stl_algobase.h:452
operator delete(void*, unsigned long): 1 occurrences►
- /cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/new_allocator.h:172
operator new(unsigned long): 1 occurrences►

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DEC: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/src/Kripke/ParallelComm.cpp:241

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 308 bytes. The binary loop is storing 188 bytes.

General properties

nb instructions	187
nb uops	194
loop length	751
used x86 registers	15
used mmx registers	0
used xmm registers	7
used ymm registers	0
used zmm registers	0
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	33.33 cycles
front end	33.33 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	19.00	14.00	14.33	14.33	13.50	14.00	19.00	13.50	13.50	13.50	14.00	14.33
cycles	19.00	14.00	14.33	14.33	13.50	14.00	19.00	13.50	13.50	13.50	14.00	14.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	33.33
Dispatch	19.00
Overall L1	33.33

Vectorization ratios

all	19%
load	31%
store	31%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 33.33 cycles. At this rate:

4% of peak load performance is reached (9.24 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (5.64 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 4e328b

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
LEA (%R13,%R13,4),%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SAL $0x2,%R12	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
MOV %R12,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 403220 <_Znwm@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOVQ $0,(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOVQ $0,0x8(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOVL $0,0x10(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %R13D,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RAX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%RAX,%R12,1),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA 0x14(%RAX),%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP $0x1,%R13	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4e3468 <_ZN6Kripke12ParallelComm12testRecievesEv+0x218>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RCX,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %R10,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
SUB $0x14,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x2,%R8	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
MOV $0xccccccccccccccd,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	scal (12.5%)
IMUL %RSI,%R8	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
INC %R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $0x7,%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
JE 4e33bd <_ZN6Kripke12ParallelComm12testRecievesEv+0x16d>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x1,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4e339f <_ZN6Kripke12ParallelComm12testRecievesEv+0x14f>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x2,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4e3389 <_ZN6Kripke12ParallelComm12testRecievesEv+0x139>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x3,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4e3374 <_ZN6Kripke12ParallelComm12testRecievesEv+0x124>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x4,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4e335f <_ZN6Kripke12ParallelComm12testRecievesEv+0x10f>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x5,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4e334a <_ZN6Kripke12ParallelComm12testRecievesEv+0xfa>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x6,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4e3334 <_ZN6Kripke12ParallelComm12testRecievesEv+0xe4>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVDQU (%RAX),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
MOV 0x10(%RAX),%R9D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVDQU %XMM0,0x14(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOV %R9D,0x10(%R10)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
LEA 0x28(%RAX),%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVDQU (%RBX),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
ADD $0x14,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVDQU %XMM1,-0x14(%R10)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOV 0x10(%RBX),%R11D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R11D,-0x4(%R10)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VMOVDQU (%RBX),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
ADD $0x14,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVDQU %XMM2,-0x14(%R10)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOV 0x10(%RBX),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %EAX,-0x4(%R10)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VMOVDQU (%RBX),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
ADD $0x14,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVDQU %XMM3,-0x14(%R10)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOV 0x10(%RBX),%EDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %EDI,-0x4(%R10)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VMOVDQU (%RBX),%XMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
ADD $0x14,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVDQU %XMM4,-0x14(%R10)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOV 0x10(%RBX),%EDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV %EDX,-0x4(%R10)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VMOVDQU (%RBX),%XMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
ADD $0x14,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVDQU %XMM5,-0x14(%R10)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOV 0x10(%RBX),%R8D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R8D,-0x4(%R10)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VMOVDQU (%RBX),%XMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
ADD $0x14,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVDQU %XMM6,-0x14(%R10)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOV 0x10(%RBX),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV %ESI,-0x4(%R10)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CMP %R10,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4e3468 <_ZN6Kripke12ParallelComm12testRecievesEv+0x218>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x28(%R14),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x50(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x48(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %RBX,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R15D,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 403370 <MPI_Testany@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x34(%RBP),%R15D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
TEST %R15D,%R15D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
JNE 4e34a8 <_ZN6Kripke12ParallelComm12testRecievesEv+0x258>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOVSXD -0x38(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x28(%R14),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x40(%R14),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%R11,%R10,4),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x30(%R14),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA 0x4(%RDI),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV (%RCX,%R10,4),%R15D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R10,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RSI,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4e34f0 <_ZN6Kripke12ParallelComm12testRecievesEv+0x2a0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RAX,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %RSI,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP $0x4,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JLE 4e3680 <_ZN6Kripke12ParallelComm12testRecievesEv+0x430>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R8,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CALL 403440 <memmove@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV 0x40(%R14),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x30(%R14),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOVSXD -0x38(%RBP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%RCX,%R9,4),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x48(%R14),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SUB $0x4,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA 0x4(%RDI),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,0x30(%R14)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CMP %RSI,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4e3522 <_ZN6Kripke12ParallelComm12testRecievesEv+0x2d2>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R10,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SUB %RSI,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
CMP $0x4,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JLE 4e3694 <_ZN6Kripke12ParallelComm12testRecievesEv+0x444>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CALL 403440 <memmove@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV 0x48(%R14),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x60(%R14),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x58(%R14),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RDI,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB $0x4,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %R11,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R10,0x48(%R14)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
SAR $0x2,%R8	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
CMP %RDI,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4e3648 <_ZN6Kripke12ParallelComm12testRecievesEv+0x3f8>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA -0x1(%R8),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $0x7,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (6.3%)
CMP %R15D,(%R11)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (6.3%)
JE 4e3668 <_ZN6Kripke12ParallelComm12testRecievesEv+0x418>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV $0x1,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP %R8,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JAE 4e3648 <_ZN6Kripke12ParallelComm12testRecievesEv+0x3f8>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
TEST %RDX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JE 4e35e5 <_ZN6Kripke12ParallelComm12testRecievesEv+0x395>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x1,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4e35d3 <_ZN6Kripke12ParallelComm12testRecievesEv+0x383>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x2,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4e35c6 <_ZN6Kripke12ParallelComm12testRecievesEv+0x376>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x3,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4e35b9 <_ZN6Kripke12ParallelComm12testRecievesEv+0x369>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x4,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4e35ac <_ZN6Kripke12ParallelComm12testRecievesEv+0x35c>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x5,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4e359f <_ZN6Kripke12ParallelComm12testRecievesEv+0x34f>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x6,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JNE 4e3672 <_ZN6Kripke12ParallelComm12testRecievesEv+0x422>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP %R15D,(%R11,%RCX,4)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (6.3%)
JE 4e3668 <_ZN6Kripke12ParallelComm12testRecievesEv+0x418>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
INC %RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R15D,(%R11,%RCX,4)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (6.3%)
JE 4e3668 <_ZN6Kripke12ParallelComm12testRecievesEv+0x418>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
INC %RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R15D,(%R11,%RCX,4)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (6.3%)
JE 4e3668 <_ZN6Kripke12ParallelComm12testRecievesEv+0x418>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
INC %RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R15D,(%R11,%RCX,4)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (6.3%)
JE 4e3668 <_ZN6Kripke12ParallelComm12testRecievesEv+0x418>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
INC %RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R15D,(%R11,%RCX,4)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (6.3%)
JE 4e3668 <_ZN6Kripke12ParallelComm12testRecievesEv+0x418>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
INC %RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R15D,(%R11,%RCX,4)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (6.3%)
JE 4e3668 <_ZN6Kripke12ParallelComm12testRecievesEv+0x418>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
INC %RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R8,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JAE 4e3648 <_ZN6Kripke12ParallelComm12testRecievesEv+0x3f8>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R12,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
DEC %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 403230 <_ZdlPvm@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
TEST %R13D,%R13D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
JG 4e328b <_ZN6Kripke12ParallelComm12testRecievesEv+0x3b>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x70(%R14),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
DECL (%R15,%RCX,4)	3	0.20	0.20	0.33	0.33	0.50	0.20	0.20	0.50	0.50	0.50	0.20	0.33	1	0.50	scal (6.3%)
JMP 4e3648 <_ZN6Kripke12ParallelComm12testRecievesEv+0x3f8>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
CMP %R15D,0x4(%R11)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (6.3%)
JE 4e3668 <_ZN6Kripke12ParallelComm12testRecievesEv+0x418>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
INC %RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JMP 4e3592 <_ZN6Kripke12ParallelComm12testRecievesEv+0x342>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
JNE 4e34f0 <_ZN6Kripke12ParallelComm12testRecievesEv+0x2a0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x4(%RDI),%EDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV %EDX,(%RDI)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOVSXD -0x38(%RBP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JMP 4e34f0 <_ZN6Kripke12ParallelComm12testRecievesEv+0x2a0>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
JNE 4e3522 <_ZN6Kripke12ParallelComm12testRecievesEv+0x2d2>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x4(%RDI),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV %ESI,(%RDI)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
JMP 4e3522 <_ZN6Kripke12ParallelComm12testRecievesEv+0x2d2>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A

Report Configuration

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Workaround

Execution units bottlenecks

CALL instructions

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Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

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Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code