OV - exec - Loop 2184

	Loop Id: 2184	Module: exec	Source: forall.hpp:59-59 [...]	Coverage: 0.08%

0x4be3d0 MOV	-0x58(%RBP),%RBX

0x4be3d4 MOV	-0x88(%RBP),%RDI

0x4be3db LEA	(,%RBX,8),%RCX

0x4be3e3 MOV	-0xb8(%RBP),%R10

0x4be3ea MOV	-0x60(%RBP),%R9

0x4be3ee MOV	-0x98(%RBP),%RDX

0x4be3f5 LEA	(%RCX,%RDI,1),%R8

0x4be3f9 MOV	-0x90(%RBP),%RDI

0x4be400 LEA	(%R10,%R9,8),%RAX

0x4be404 ADD	%RCX,%RDI

0x4be407 MOV	-0x78(%RBP),%R9

0x4be40b ADD	%RDX,%RCX

0x4be40e XOR	%R10D,%R10D

0x4be411 MOV	-0x70(%RBP),%RDX

0x4be415 TESTB	$0x1,-0x40(%RBP)

0x4be419 JE	4be4ce

0x4be41f VMOVSD	(%R12),%XMM5

0x4be425 MOV	-0x68(%RBP),%RBX

0x4be429 VADDSD	%XMM5,%XMM5,%XMM0

0x4be42d MOV	-0x48(%RBP),%R10

0x4be431 VMOVSD	(%R13),%XMM10

0x4be437 VDIVSD	(%R10),%XMM0,%XMM1

0x4be43c VMOVSD	(%RBX),%XMM13

0x4be440 VMULSD	(%RAX),%XMM1,%XMM6

0x4be444 VADDSD	%XMM10,%XMM10,%XMM11

0x4be449 VADDSD	%XMM13,%XMM13,%XMM14

0x4be44e VMOVSD	(%R8),%XMM2

0x4be453 MOV	-0x70(%RBP),%RDX

0x4be457 VDIVSD	(%R9),%XMM11,%XMM12

0x4be45c VDIVSD	(%R11),%XMM14,%XMM15

0x4be461 VFMADD231SD	(%RSI),%XMM12,%XMM6

0x4be466 VADDSD	%XMM1,%XMM15,%XMM4

0x4be46a VFMADD132SD	(%RDX),%XMM2,%XMM15

0x4be46f VADDSD	(%RDI),%XMM12,%XMM8

0x4be473 MOV	-0x40(%RBP),%RBX

0x4be477 MOV	$0x1,%R10D

0x4be47d VADDSD	%XMM4,%XMM8,%XMM9

0x4be481 VADDSD	%XMM6,%XMM15,%XMM7

0x4be485 ADD	%R15,%R9

0x4be488 ADD	%R14,%R8

0x4be48b VDIVSD	%XMM9,%XMM7,%XMM10

0x4be490 ADD	%R14,%RDI

0x4be493 VMOVSD	%XMM10,(%RCX)

0x4be497 VMOVAPD	%XMM10,%XMM11

0x4be49c VFMSUB213SD	(%RSI),%XMM3,%XMM11

0x4be4a1 VMOVAPD	%XMM10,%XMM12

0x4be4a6 ADD	%R14,%RCX

0x4be4a9 VMOVSD	%XMM11,(%RSI)

0x4be4ad VFMSUB213SD	(%RDX),%XMM3,%XMM12

0x4be4b2 VMOVSD	%XMM12,(%RDX)

0x4be4b6 VFMSUB213SD	(%RAX),%XMM3,%XMM10

0x4be4bb ADD	%R15,%RDX

0x4be4be VMOVSD	%XMM10,(%RAX)

0x4be4c2 ADD	%R15,%RAX

0x4be4c5 CMP	%RBX,%R10

0x4be4c8 JE	4be612

0x4be4ce MOV	%R10,-0x38(%RBP)

0x4be4d2 MOV	-0x68(%RBP),%RBX

  (2183) 0x4be4d6 VMOVSD	(%R12),%XMM4

  (2183) 0x4be4dc MOV	-0x48(%RBP),%R10

  (2183) 0x4be4e0 VADDSD	%XMM4,%XMM4,%XMM2

  (2183) 0x4be4e4 VMOVSD	(%R13),%XMM13

  (2183) 0x4be4ea VMOVSD	(%RBX),%XMM5

  (2183) 0x4be4ee VDIVSD	(%R10),%XMM2,%XMM6

  (2183) 0x4be4f3 VMULSD	(%RAX),%XMM6,%XMM9

  (2183) 0x4be4f7 VADDSD	%XMM13,%XMM13,%XMM14

  (2183) 0x4be4fc VADDSD	%XMM5,%XMM5,%XMM0

  (2183) 0x4be500 VMOVSD	(%R8),%XMM7

  (2183) 0x4be505 VDIVSD	(%R9),%XMM14,%XMM15

  (2183) 0x4be50a VDIVSD	(%R11),%XMM0,%XMM1

  (2183) 0x4be50f VFMADD231SD	(%RSI),%XMM15,%XMM9

  (2183) 0x4be514 VADDSD	%XMM6,%XMM1,%XMM8

  (2183) 0x4be518 VFMADD132SD	(%RDX),%XMM7,%XMM1

  (2183) 0x4be51d VADDSD	(%RDI),%XMM15,%XMM11

  (2183) 0x4be521 ADD	%R14,%R8

  (2183) 0x4be524 ADD	%R15,%R9

  (2183) 0x4be527 VADDSD	%XMM8,%XMM11,%XMM12

  (2183) 0x4be52c VADDSD	%XMM9,%XMM1,%XMM10

  (2183) 0x4be531 ADD	%R14,%RDI

  (2183) 0x4be534 VDIVSD	%XMM12,%XMM10,%XMM13

  (2183) 0x4be539 VMOVSD	%XMM13,(%RCX)

  (2183) 0x4be53d VMOVAPD	%XMM13,%XMM14

  (2183) 0x4be542 VFMSUB213SD	(%RSI),%XMM3,%XMM14

  (2183) 0x4be547 VMOVAPD	%XMM13,%XMM15

  (2183) 0x4be54c ADD	%R14,%RCX

  (2183) 0x4be54f VMOVSD	%XMM14,(%RSI)

  (2183) 0x4be553 VFMSUB213SD	(%RDX),%XMM3,%XMM15

  (2183) 0x4be558 VMOVSD	%XMM15,(%RDX)

  (2183) 0x4be55c VFMSUB213SD	(%RAX),%XMM3,%XMM13

  (2183) 0x4be561 ADD	%R15,%RDX

  (2183) 0x4be564 VMOVSD	%XMM13,(%RAX)

  (2183) 0x4be568 VMOVSD	(%R12),%XMM8

  (2183) 0x4be56e ADD	%R15,%RAX

  (2183) 0x4be571 VADDSD	%XMM8,%XMM8,%XMM7

  (2183) 0x4be576 VMOVSD	(%R13),%XMM5

  (2183) 0x4be57c VMOVSD	(%RBX),%XMM4

  (2183) 0x4be580 VDIVSD	(%R10),%XMM7,%XMM9

  (2183) 0x4be585 VMULSD	(%RAX),%XMM9,%XMM12

  (2183) 0x4be589 VADDSD	%XMM5,%XMM5,%XMM0

  (2183) 0x4be58d VADDSD	%XMM4,%XMM4,%XMM2

  (2183) 0x4be591 VMOVSD	(%R8),%XMM11

  (2183) 0x4be596 VDIVSD	(%R9),%XMM0,%XMM1

  (2183) 0x4be59b VDIVSD	(%R11),%XMM2,%XMM6

  (2183) 0x4be5a0 VFMADD231SD	(%RSI),%XMM1,%XMM12

  (2183) 0x4be5a5 VADDSD	%XMM9,%XMM6,%XMM10

  (2183) 0x4be5aa VFMADD132SD	(%RDX),%XMM11,%XMM6

  (2183) 0x4be5af VADDSD	(%RDI),%XMM1,%XMM14

  (2183) 0x4be5b3 ADD	%R15,%R9

  (2183) 0x4be5b6 ADD	%R14,%R8

  (2183) 0x4be5b9 VADDSD	%XMM10,%XMM14,%XMM15

  (2183) 0x4be5be VADDSD	%XMM12,%XMM6,%XMM13

  (2183) 0x4be5c3 ADD	%R14,%RDI

  (2183) 0x4be5c6 VDIVSD	%XMM15,%XMM13,%XMM5

  (2183) 0x4be5cb VMOVSD	%XMM5,(%RCX)

  (2183) 0x4be5cf VMOVAPD	%XMM5,%XMM0

  (2183) 0x4be5d3 VFMSUB213SD	(%RSI),%XMM3,%XMM0

  (2183) 0x4be5d8 VMOVAPD	%XMM5,%XMM1

  (2183) 0x4be5dc ADD	%R14,%RCX

  (2183) 0x4be5df VMOVSD	%XMM0,(%RSI)

  (2183) 0x4be5e3 VFMSUB213SD	(%RDX),%XMM3,%XMM1

  (2183) 0x4be5e8 ADDQ	$0x2,-0x38(%RBP)

  (2183) 0x4be5ed MOV	-0x40(%RBP),%R10

  (2183) 0x4be5f1 VMOVSD	%XMM1,(%RDX)

  (2183) 0x4be5f5 VFMSUB213SD	(%RAX),%XMM3,%XMM5

  (2183) 0x4be5fa ADD	%R15,%RDX

  (2183) 0x4be5fd VMOVSD	%XMM5,(%RAX)

  (2183) 0x4be601 ADD	%R15,%RAX

  (2183) 0x4be604 CMP	%R10,-0x38(%RBP)

  (2183) 0x4be608 JNE	4be4d6

0x4be60e MOV	%RBX,-0x68(%RBP)

0x4be612 INCQ	-0x50(%RBP)

0x4be616 MOV	-0xa0(%RBP),%RCX

0x4be61d MOV	-0xa8(%RBP),%RAX

0x4be624 MOV	-0xb0(%RBP),%RDI

0x4be62b MOV	-0x50(%RBP),%R8

0x4be62f ADD	%RAX,-0x58(%RBP)

0x4be633 ADD	%RDI,-0x60(%RBP)

0x4be637 ADD	%RCX,%R11

0x4be63a ADD	%RCX,%RSI

0x4be63d CMP	%R8,-0x80(%RBP)

0x4be641 JNE	4be3d0

/home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/Operators.hpp: 304 - 304

--------------------------------------------------------------------------------

304:   RAJA_HOST_DEVICE constexpr Ret operator()(const Arg1& lhs,

/home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/loop/forall.hpp: 59 - 59

--------------------------------------------------------------------------------

59:   for (decltype(distance_it) i = 0; i < distance_it; ++i) {

/home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/View.hpp: 107 - 107

--------------------------------------------------------------------------------

107:   RAJA_HOST_DEVICE RAJA_INLINE value_type &operator()(Args... args) const

/home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/src/Kripke/Kernel/SweepSubdomain.cpp: 87 - 105

--------------------------------------------------------------------------------

87:             double xcos_dxi = 2.0 * xcos(d) / dx(i);

88:             double ycos_dyj = 2.0 * ycos(d) / dy(j);

89:             double zcos_dzk = 2.0 * zcos(d) / dz(k);

90:

91:             Zone z(zone_layout(*i, *j, *k));

92:

93:             /* Calculate new zonal flux */

94:             double psi_d_g_z = (rhs(d,g,z)

95:                 + psi_lf(d, g, j, k) * xcos_dxi

96:                 + psi_fr(d, g, i, k) * ycos_dyj

97:                 + psi_bo(d, g, i, j) * zcos_dzk)

98:                 / (xcos_dxi + ycos_dyj + zcos_dzk + sigt(g, z));

99:

100:             psi(d, g, z) = psi_d_g_z;

101:

102:             /* Apply diamond-difference relationships */

103:             psi_lf(d, g, j, k) = 2.0 * psi_d_g_z - psi_lf(d, g, j, k);

104:             psi_fr(d, g, i, k) = 2.0 * psi_d_g_z - psi_fr(d, g, i, k);

105:             psi_bo(d, g, i, j) = 2.0 * psi_d_g_z - psi_bo(d, g, i, j);

Coverage (%)	Name	Source Location	Module
○98.10	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○1.90	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.73
CQA speedup if fully vectorized	2.33
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.30
Bottlenecks
Function	void RAJA::internal::StatementExecutor, RAJA::statement::For<2l, RAJA::policy::loop::loop_exec, RAJA::statement::For<3l, RAJA::policy::loop::loop_exec, RAJA::statement::For<4l, RAJA::policy::loop::loop_exec, RAJA::statement::Lambda<0l> > > > > >::exec, RAJA::statement::For<2l, RAJA::policy::loop::loop_exec, RAJA::statement::For<3l, RAJA::policy::loop::loop_exec, RAJA::statement::For<4l, RAJA::policy::loop::loop_exec, RAJA::statement::Lambda<0l> > > > > >, camp::tuple, Kripke::Direction>, RAJA::impl::Span, Kripke::Group>, RAJA::impl::Span, Kripke::ZoneK>, RAJA::impl::Span, Kripke::ZoneJ>, RAJA::impl::Span, Kripke::ZoneI> >, camp::tuple<>, SweepSdom::operator() >(Kripke::ArchLayoutT, Kripke::Core::DataStore&, Kripke::SdomId) const::{lambda(Kripke::Direction, Kripke::Group, Kripke::ZoneK, Kripke::ZoneJ, Kripke::ZoneI)#1}>&>(RAJA::internal::LoopData, RAJA::statement::For<2l, RAJA::policy::loop::loop_exec, RAJA::statement::For<3l, RAJA::policy::loop::loop_exec, RAJA::statement::For<4l, RAJA::policy::loop::loop_exec, RAJA::statement::Lambda<0l> > > > > >, camp::tuple, Kripke::Direction>, RAJA::impl::Span, Kripke::Group>, RAJA::impl::Span, Kripke::ZoneK>, RAJA::impl::Span, Kripke::ZoneJ>, RAJA::impl::Span, Kripke::ZoneI> >, camp::tuple<>, SweepSdom::operator() >(Kripke::ArchLayoutT, Kripke::Core::DataStore&, Kripke::SdomId) const::{lambda(Kripke::Direction, Kripke::Group, Kripke::ZoneK, Kripke::ZoneJ, Kripke::ZoneI)#1}>&) [clone ._omp_fn.0]
Source	Operators.hpp:304-304,forall.hpp:59-59,View.hpp:107-107,SweepSubdomain.cpp:87-89,SweepSubdomain.cpp:94-94,SweepSubdomain.cpp:97-100,SweepSubdomain.cpp:103-105
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	12.67
CQA cycles if no scalar integer	12.67
CQA cycles if FP arith vectorized	7.33
CQA cycles if fully vectorized	5.44
Front-end cycles	9.78
P0 cycles	5.47
P1 cycles	5.47
P2 cycles	9.89
P3 cycles	9.89
P4 cycles	3.50
P5 cycles	5.47
P6 cycles	5.47
P7 cycles	3.50
P8 cycles	3.50
P9 cycles	3.50
P10 cycles	5.47
P11 cycles	9.89
DIV/SQRT cycles	10.67
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	55.67
Nb uops	58.67
Nb loads	29.67
Nb stores	7.00
Nb stack references	16.33
FLOP/cycle	1.16
Nb FLOP add-sub	4.67
Nb FLOP mul	0.67
Nb FLOP fma	3.33
Nb FLOP div	2.67
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	24.04
Bytes prefetched	0.00
Bytes loaded	230.33
Bytes stored	56.00
Stride 0	3.00
Stride 1	0.00
Stride n	0.00
Stride unknown	16.00
Stride indirect	0.00
Vectorization ratio all	4.04
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	33.33
Vector-efficiency ratio all	12.45
Vector-efficiency ratio load	11.57
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	12.50
Vector-efficiency ratio other	11.20

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	19.20
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.09
Bottlenecks	P2, P3, P11,
Function	void RAJA::internal::StatementExecutor, RAJA::statement::For<2l, RAJA::policy::loop::loop_exec, RAJA::statement::For<3l, RAJA::policy::loop::loop_exec, RAJA::statement::For<4l, RAJA::policy::loop::loop_exec, RAJA::statement::Lambda<0l> > > > > >::exec, RAJA::statement::For<2l, RAJA::policy::loop::loop_exec, RAJA::statement::For<3l, RAJA::policy::loop::loop_exec, RAJA::statement::For<4l, RAJA::policy::loop::loop_exec, RAJA::statement::Lambda<0l> > > > > >, camp::tuple, Kripke::Direction>, RAJA::impl::Span, Kripke::Group>, RAJA::impl::Span, Kripke::ZoneK>, RAJA::impl::Span, Kripke::ZoneJ>, RAJA::impl::Span, Kripke::ZoneI> >, camp::tuple<>, SweepSdom::operator() >(Kripke::ArchLayoutT, Kripke::Core::DataStore&, Kripke::SdomId) const::{lambda(Kripke::Direction, Kripke::Group, Kripke::ZoneK, Kripke::ZoneJ, Kripke::ZoneI)#1}>&>(RAJA::internal::LoopData, RAJA::statement::For<2l, RAJA::policy::loop::loop_exec, RAJA::statement::For<3l, RAJA::policy::loop::loop_exec, RAJA::statement::For<4l, RAJA::policy::loop::loop_exec, RAJA::statement::Lambda<0l> > > > > >, camp::tuple, Kripke::Direction>, RAJA::impl::Span, Kripke::Group>, RAJA::impl::Span, Kripke::ZoneK>, RAJA::impl::Span, Kripke::ZoneJ>, RAJA::impl::Span, Kripke::ZoneI> >, camp::tuple<>, SweepSdom::operator() >(Kripke::ArchLayoutT, Kripke::Core::DataStore&, Kripke::SdomId) const::{lambda(Kripke::Direction, Kripke::Group, Kripke::ZoneK, Kripke::ZoneJ, Kripke::ZoneI)#1}>&) [clone ._omp_fn.0]
Source	Operators.hpp:304-304,forall.hpp:59-59,View.hpp:107-107,SweepSubdomain.cpp:87-89,SweepSubdomain.cpp:94-94,SweepSubdomain.cpp:97-100,SweepSubdomain.cpp:103-105
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	6.00
CQA cycles if no scalar integer	6.00
CQA cycles if FP arith vectorized	6.00
CQA cycles if fully vectorized	0.31
Front-end cycles	5.50
P0 cycles	2.00
P1 cycles	2.00
P2 cycles	6.00
P3 cycles	6.00
P4 cycles	2.50
P5 cycles	2.00
P6 cycles	2.00
P7 cycles	2.50
P8 cycles	2.50
P9 cycles	2.50
P10 cycles	2.00
P11 cycles	6.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	30.00
Nb uops	33.00
Nb loads	18.00
Nb stores	5.00
Nb stack references	16.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	29.50
Bytes prefetched	0.00
Bytes loaded	137.00
Bytes stored	40.00
Stride 0	3.00
Stride 1	0.00
Stride n	0.00
Stride unknown	16.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	11.51
Vector-efficiency ratio load	10.94
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	1.56

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	2.00
CQA speedup if fully vectorized	2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.32
Bottlenecks	P0,
Function	void RAJA::internal::StatementExecutor, RAJA::statement::For<2l, RAJA::policy::loop::loop_exec, RAJA::statement::For<3l, RAJA::policy::loop::loop_exec, RAJA::statement::For<4l, RAJA::policy::loop::loop_exec, RAJA::statement::Lambda<0l> > > > > >::exec, RAJA::statement::For<2l, RAJA::policy::loop::loop_exec, RAJA::statement::For<3l, RAJA::policy::loop::loop_exec, RAJA::statement::For<4l, RAJA::policy::loop::loop_exec, RAJA::statement::Lambda<0l> > > > > >, camp::tuple, Kripke::Direction>, RAJA::impl::Span, Kripke::Group>, RAJA::impl::Span, Kripke::ZoneK>, RAJA::impl::Span, Kripke::ZoneJ>, RAJA::impl::Span, Kripke::ZoneI> >, camp::tuple<>, SweepSdom::operator() >(Kripke::ArchLayoutT, Kripke::Core::DataStore&, Kripke::SdomId) const::{lambda(Kripke::Direction, Kripke::Group, Kripke::ZoneK, Kripke::ZoneJ, Kripke::ZoneI)#1}>&>(RAJA::internal::LoopData, RAJA::statement::For<2l, RAJA::policy::loop::loop_exec, RAJA::statement::For<3l, RAJA::policy::loop::loop_exec, RAJA::statement::For<4l, RAJA::policy::loop::loop_exec, RAJA::statement::Lambda<0l> > > > > >, camp::tuple, Kripke::Direction>, RAJA::impl::Span, Kripke::Group>, RAJA::impl::Span, Kripke::ZoneK>, RAJA::impl::Span, Kripke::ZoneJ>, RAJA::impl::Span, Kripke::ZoneI> >, camp::tuple<>, SweepSdom::operator() >(Kripke::ArchLayoutT, Kripke::Core::DataStore&, Kripke::SdomId) const::{lambda(Kripke::Direction, Kripke::Group, Kripke::ZoneK, Kripke::ZoneJ, Kripke::ZoneI)#1}>&) [clone ._omp_fn.0]
Source	Operators.hpp:304-304,forall.hpp:59-59,View.hpp:107-107,SweepSubdomain.cpp:87-89,SweepSubdomain.cpp:94-94,SweepSubdomain.cpp:97-100,SweepSubdomain.cpp:103-105
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	16.00
CQA cycles if no scalar integer	16.00
CQA cycles if FP arith vectorized	8.00
CQA cycles if fully vectorized	8.00
Front-end cycles	12.17
P0 cycles	7.20
P1 cycles	7.20
P2 cycles	12.00
P3 cycles	12.00
P4 cycles	4.50
P5 cycles	7.20
P6 cycles	7.20
P7 cycles	4.50
P8 cycles	4.50
P9 cycles	4.50
P10 cycles	7.20
P11 cycles	12.00
DIV/SQRT cycles	16.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	70.00
Nb uops	73.00
Nb loads	36.00
Nb stores	9.00
Nb stack references	17.00
FLOP/cycle	1.38
Nb FLOP add-sub	7.00
Nb FLOP mul	1.00
Nb FLOP fma	5.00
Nb FLOP div	4.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	22.06
Bytes prefetched	0.00
Bytes loaded	281.00
Bytes stored	72.00
Stride 0	3.00
Stride 1	0.00
Stride n	0.00
Stride unknown	16.00
Stride indirect	0.00
Vectorization ratio all	5.88
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	50.00
Vector-efficiency ratio all	12.91
Vector-efficiency ratio load	11.89
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	12.50
Vector-efficiency ratio other	16.02

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	2.00
CQA speedup if fully vectorized	2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.37
Bottlenecks	P0,
Function	void RAJA::internal::StatementExecutor, RAJA::statement::For<2l, RAJA::policy::loop::loop_exec, RAJA::statement::For<3l, RAJA::policy::loop::loop_exec, RAJA::statement::For<4l, RAJA::policy::loop::loop_exec, RAJA::statement::Lambda<0l> > > > > >::exec, RAJA::statement::For<2l, RAJA::policy::loop::loop_exec, RAJA::statement::For<3l, RAJA::policy::loop::loop_exec, RAJA::statement::For<4l, RAJA::policy::loop::loop_exec, RAJA::statement::Lambda<0l> > > > > >, camp::tuple, Kripke::Direction>, RAJA::impl::Span, Kripke::Group>, RAJA::impl::Span, Kripke::ZoneK>, RAJA::impl::Span, Kripke::ZoneJ>, RAJA::impl::Span, Kripke::ZoneI> >, camp::tuple<>, SweepSdom::operator() >(Kripke::ArchLayoutT, Kripke::Core::DataStore&, Kripke::SdomId) const::{lambda(Kripke::Direction, Kripke::Group, Kripke::ZoneK, Kripke::ZoneJ, Kripke::ZoneI)#1}>&>(RAJA::internal::LoopData, RAJA::statement::For<2l, RAJA::policy::loop::loop_exec, RAJA::statement::For<3l, RAJA::policy::loop::loop_exec, RAJA::statement::For<4l, RAJA::policy::loop::loop_exec, RAJA::statement::Lambda<0l> > > > > >, camp::tuple, Kripke::Direction>, RAJA::impl::Span, Kripke::Group>, RAJA::impl::Span, Kripke::ZoneK>, RAJA::impl::Span, Kripke::ZoneJ>, RAJA::impl::Span, Kripke::ZoneI> >, camp::tuple<>, SweepSdom::operator() >(Kripke::ArchLayoutT, Kripke::Core::DataStore&, Kripke::SdomId) const::{lambda(Kripke::Direction, Kripke::Group, Kripke::ZoneK, Kripke::ZoneJ, Kripke::ZoneI)#1}>&) [clone ._omp_fn.0]
Source	Operators.hpp:304-304,forall.hpp:59-59,View.hpp:107-107,SweepSubdomain.cpp:87-89,SweepSubdomain.cpp:94-94,SweepSubdomain.cpp:97-100,SweepSubdomain.cpp:103-105
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	16.00
CQA cycles if no scalar integer	16.00
CQA cycles if FP arith vectorized	8.00
CQA cycles if fully vectorized	8.00
Front-end cycles	11.67
P0 cycles	7.20
P1 cycles	7.20
P2 cycles	11.67
P3 cycles	11.67
P4 cycles	3.50
P5 cycles	7.20
P6 cycles	7.20
P7 cycles	3.50
P8 cycles	3.50
P9 cycles	3.50
P10 cycles	7.20
P11 cycles	11.67
DIV/SQRT cycles	16.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	67.00
Nb uops	70.00
Nb loads	35.00
Nb stores	7.00
Nb stack references	16.00
FLOP/cycle	1.38
Nb FLOP add-sub	7.00
Nb FLOP mul	1.00
Nb FLOP fma	5.00
Nb FLOP div	4.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	20.56
Bytes prefetched	0.00
Bytes loaded	273.00
Bytes stored	56.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	6.25
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	50.00
Vector-efficiency ratio all	12.94
Vector-efficiency ratio load	11.89
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	12.50
Vector-efficiency ratio other	16.02

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	void RAJA::internal::StatementExecutor, RAJA::statement::For<2l, RAJA::policy::loop::loop_exec, RAJA::statement::For<3l, RAJA::policy::loop::loop_exec, RAJA::statement::For<4l, RAJA::policy::loop::loop_exec, RAJA::statement::Lambda<0l> > > > > >::exec, RAJA::statement::For<2l, RAJA::policy::loop::loop_exec, RAJA::statement::For<3l, RAJA::policy::loop::loop_exec, RAJA::statement::For<4l, RAJA::policy::loop::loop_exec, RAJA::statement::Lambda<0l> > > > > >, camp::tuple, Kripke::Direction>, RAJA::impl::Span, Kripke::Group>, RAJA::impl::Span, Kripke::ZoneK>, RAJA::impl::Span, Kripke::ZoneJ>, RAJA::impl::Span, Kripke::ZoneI> >, camp::tuple<>, SweepSdom::operator() >(Kripke::ArchLayoutT, Kripke::Core::DataStore&, Kripke::SdomId) const::{lambda(Kripke::Direction, Kripke::Group, Kripke::ZoneK, Kripke::ZoneJ, Kripke::ZoneI)#1}>&>(RAJA::internal::LoopData, RAJA::statement::For<2l, RAJA::policy::loop::loop_exec, RAJA::statement::For<3l, RAJA::policy::loop::loop_exec, RAJA::statement::For<4l, RAJA::policy::loop::loop_exec, RAJA::statement::Lambda<0l> > > > > >, camp::tuple, Kripke::Direction>, RAJA::impl::Span, Kripke::Group>, RAJA::impl::Span, Kripke::ZoneK>, RAJA::impl::Span, Kripke::ZoneJ>, RAJA::impl::Span, Kripke::ZoneI> >, camp::tuple<>, SweepSdom::operator() >(Kripke::ArchLayoutT, Kripke::Core::DataStore&, Kripke::SdomId) const::{lambda(Kripke::Direction, Kripke::Group, Kripke::ZoneK, Kripke::ZoneJ, Kripke::ZoneI)#1}>&) [clone ._omp_fn.0]
Source file and lines	forall.hpp:59-59
Module	exec

The loop is defined in:

/home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/Operators.hpp:304
/home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/loop/forall.hpp:59
/home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/View.hpp:107
/home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/src/Kripke/Kernel/SweepSubdomain.cpp:87-105

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).
This loop has 3 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is probably not vectorized. Only 12% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 12.67 to 5.44 cycles (2.33x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.67 to 9.94 cycles (1.27x speedup).

FMA

Detected 3.33 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. Estimated speedup by perfect pairing: 2.11x. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

ADD: 0 occurrences
INC: 0 occurrences

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 16 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

11 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 14.666666666667 FP arithmetical operations:

8: addition or subtraction (3 inside FMA instructions)
4: multiply (3 inside FMA instructions)
2.67: divide

The binary loop is loading 230 bytes (28 double precision FP elements). The binary loop is storing 56 bytes (7 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.05 FP operations per loaded or stored byte.

General properties

nb instructions	55.67
nb uops	58.67
loop length	256.67
used x86 registers	13.67
used mmx registers	0
used xmm registers	10.67
used ymm registers	0
used zmm registers	0
nb stack references	16.33

Front-end

MACRO FUSION NOT POSSIBLE

micro-operation queue	9.78 cycles
front end	9.78 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	5.47	5.47	9.89	9.89	3.50	5.47	5.47	3.50	3.50	3.50	5.47	9.89
cycles	5.47	5.47	9.89	9.89	3.50	5.47	5.47	3.50	3.50	3.50	5.47	9.89

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	10.67
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	9.78
Dispatch	9.89
DIV/SQRT	10.67
Data deps.	0.00
Overall L1	12.67

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	7%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	100%

INT+FP

all	4%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	33%

Vector efficiency ratios

INT

all	10%
load	10%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	5%

all	13%
load	12%
store	12%
mul	12%
add-sub	12%
fma	12%
div/sqrt	12%
other	25%

INT+FP

all	12%
load	11%
store	12%
mul	12%
add-sub	12%
fma	12%
div/sqrt	12%
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 12.67 cycles. At this rate:

9% of peak load performance is reached (19.15 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (4.89 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Function	void RAJA::internal::StatementExecutor, RAJA::statement::For<2l, RAJA::policy::loop::loop_exec, RAJA::statement::For<3l, RAJA::policy::loop::loop_exec, RAJA::statement::For<4l, RAJA::policy::loop::loop_exec, RAJA::statement::Lambda<0l> > > > > >::exec, RAJA::statement::For<2l, RAJA::policy::loop::loop_exec, RAJA::statement::For<3l, RAJA::policy::loop::loop_exec, RAJA::statement::For<4l, RAJA::policy::loop::loop_exec, RAJA::statement::Lambda<0l> > > > > >, camp::tuple, Kripke::Direction>, RAJA::impl::Span, Kripke::Group>, RAJA::impl::Span, Kripke::ZoneK>, RAJA::impl::Span, Kripke::ZoneJ>, RAJA::impl::Span, Kripke::ZoneI> >, camp::tuple<>, SweepSdom::operator() >(Kripke::ArchLayoutT, Kripke::Core::DataStore&, Kripke::SdomId) const::{lambda(Kripke::Direction, Kripke::Group, Kripke::ZoneK, Kripke::ZoneJ, Kripke::ZoneI)#1}>&>(RAJA::internal::LoopData, RAJA::statement::For<2l, RAJA::policy::loop::loop_exec, RAJA::statement::For<3l, RAJA::policy::loop::loop_exec, RAJA::statement::For<4l, RAJA::policy::loop::loop_exec, RAJA::statement::Lambda<0l> > > > > >, camp::tuple, Kripke::Direction>, RAJA::impl::Span, Kripke::Group>, RAJA::impl::Span, Kripke::ZoneK>, RAJA::impl::Span, Kripke::ZoneJ>, RAJA::impl::Span, Kripke::ZoneI> >, camp::tuple<>, SweepSdom::operator() >(Kripke::ArchLayoutT, Kripke::Core::DataStore&, Kripke::SdomId) const::{lambda(Kripke::Direction, Kripke::Group, Kripke::ZoneK, Kripke::ZoneJ, Kripke::ZoneI)#1}>&) [clone ._omp_fn.0]
Source file and lines	forall.hpp:59-59
Module	exec

The loop is defined in:

/home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/Operators.hpp:304
/home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/loop/forall.hpp:59
/home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/View.hpp:107
/home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/src/Kripke/Kernel/SweepSubdomain.cpp:87-105

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 11% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 6.00 to 0.31 cycles (19.20x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by reading data from caches/RAM (load units are a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 6.00 to 5.50 cycles (1.09x speedup).

Workaround

Read less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

ADD: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/loop/forall.hpp:59
- /home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/loop/forall.hpp:59
INC: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/loop/forall.hpp:59

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 16 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 137 bytes. The binary loop is storing 40 bytes.

General properties

nb instructions	30
nb uops	33
loop length	144
used x86 registers	11
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	16

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	5.50 cycles
front end	5.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	2.00	2.00	6.00	6.00	2.50	2.00	2.00	2.50	2.50	2.50	2.00	6.00
cycles	2.00	2.00	6.00	6.00	2.50	2.00	2.00	2.50	2.50	2.50	2.00	6.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	5.50
Dispatch	6.00
Data deps.	0.00
Overall L1	6.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	11%
load	10%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	1%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.00 cycles. At this rate:

11% of peak load performance is reached (22.83 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (6.67 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4be3d0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
MOV -0x58(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x88(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (,%RBX,8),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0xb8(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x60(%RBP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x98(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
LEA (%RCX,%RDI,1),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0x90(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%R10,%R9,8),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD %RCX,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0x78(%RBP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %RDX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
XOR %R10D,%R10D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0x70(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
TESTB $0x1,-0x40(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	2	0.33	scal (1.6%)
JE 4be4ce <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl1EEEEJNS2_3ForILl2ENS_6policy4loop9loop_execEJNS8_ILl3ESB_JNS8_ILl4ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEEEEE4execIRNS0_8LoopDataINS5_4listIJSH_EEENS5_5tupleIJNS_4impl4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPST_EEST_EENSP_INSR_INSS_5GroupElPSX_EESX_EENSP_INSQ_24strided_numeric_iteratorINSS_5ZoneKElPS12_EES12_EENSP_INS11_INSS_5ZoneJElPS16_EES16_EENSP_INS11_INSS_5ZoneIElPS1A_EES1A_EEEEENSN_IJEEEJZNK9SweepSdomclINSS_11ArchLayoutTINSS_12ArchT_OpenMPENSS_11LayoutT_DGZEEEEEvT_RNSS_4Core9DataStoreENSS_6SdomIdEEUlST_SX_S12_S16_S1A_E_EEEEEvOS1M_._omp_fn.0+0xdde>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R10,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0x68(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RBX,-0x68(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
INCQ -0x50(%RBP)	3	0.20	0.20	0.33	0.33	0.50	0.20	0.20	0.50	0.50	0.50	0.20	0.33	1	0.50	scal (12.5%)
MOV -0xa0(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0xa8(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0xb0(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x50(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %RAX,-0x58(%RBP)	2	0.20	0.20	0.33	0.33	0.50	0.20	0.20	0.50	0.50	0.50	0.20	0.33	1	0.50	scal (12.5%)
ADD %RDI,-0x60(%RBP)	2	0.20	0.20	0.33	0.33	0.50	0.20	0.20	0.50	0.50	0.50	0.20	0.33	1	0.50	scal (12.5%)
ADD %RCX,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
ADD %RCX,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
CMP %R8,-0x80(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
JNE 4be3d0 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl1EEEEJNS2_3ForILl2ENS_6policy4loop9loop_execEJNS8_ILl3ESB_JNS8_ILl4ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEEEEE4execIRNS0_8LoopDataINS5_4listIJSH_EEENS5_5tupleIJNS_4impl4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPST_EEST_EENSP_INSR_INSS_5GroupElPSX_EESX_EENSP_INSQ_24strided_numeric_iteratorINSS_5ZoneKElPS12_EES12_EENSP_INS11_INSS_5ZoneJElPS16_EES16_EENSP_INS11_INSS_5ZoneIElPS1A_EES1A_EEEEENSN_IJEEEJZNK9SweepSdomclINSS_11ArchLayoutTINSS_12ArchT_OpenMPENSS_11LayoutT_DGZEEEEEvT_RNSS_4Core9DataStoreENSS_6SdomIdEEUlST_SX_S12_S16_S1A_E_EEEEEvOS1M_._omp_fn.0+0xce0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Function	void RAJA::internal::StatementExecutor, RAJA::statement::For<2l, RAJA::policy::loop::loop_exec, RAJA::statement::For<3l, RAJA::policy::loop::loop_exec, RAJA::statement::For<4l, RAJA::policy::loop::loop_exec, RAJA::statement::Lambda<0l> > > > > >::exec, RAJA::statement::For<2l, RAJA::policy::loop::loop_exec, RAJA::statement::For<3l, RAJA::policy::loop::loop_exec, RAJA::statement::For<4l, RAJA::policy::loop::loop_exec, RAJA::statement::Lambda<0l> > > > > >, camp::tuple, Kripke::Direction>, RAJA::impl::Span, Kripke::Group>, RAJA::impl::Span, Kripke::ZoneK>, RAJA::impl::Span, Kripke::ZoneJ>, RAJA::impl::Span, Kripke::ZoneI> >, camp::tuple<>, SweepSdom::operator() >(Kripke::ArchLayoutT, Kripke::Core::DataStore&, Kripke::SdomId) const::{lambda(Kripke::Direction, Kripke::Group, Kripke::ZoneK, Kripke::ZoneJ, Kripke::ZoneI)#1}>&>(RAJA::internal::LoopData, RAJA::statement::For<2l, RAJA::policy::loop::loop_exec, RAJA::statement::For<3l, RAJA::policy::loop::loop_exec, RAJA::statement::For<4l, RAJA::policy::loop::loop_exec, RAJA::statement::Lambda<0l> > > > > >, camp::tuple, Kripke::Direction>, RAJA::impl::Span, Kripke::Group>, RAJA::impl::Span, Kripke::ZoneK>, RAJA::impl::Span, Kripke::ZoneJ>, RAJA::impl::Span, Kripke::ZoneI> >, camp::tuple<>, SweepSdom::operator() >(Kripke::ArchLayoutT, Kripke::Core::DataStore&, Kripke::SdomId) const::{lambda(Kripke::Direction, Kripke::Group, Kripke::ZoneK, Kripke::ZoneJ, Kripke::ZoneI)#1}>&) [clone ._omp_fn.0]
Source file and lines	forall.hpp:59-59
Module	exec

The loop is defined in:

/home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/Operators.hpp:304
/home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/loop/forall.hpp:59
/home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/View.hpp:107
/home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/src/Kripke/Kernel/SweepSubdomain.cpp:87-105

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 16.00 to 12.17 cycles (1.32x speedup).

Workaround

Reduce the number of division or square root instructions:
- If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
Check whether you really need double precision. If not, switch to single precision to speedup execution

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 16.00 to 12.17 cycles (1.32x speedup).

FMA

Detected 5 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

ADD: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/loop/forall.hpp:59
- /home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/loop/forall.hpp:59
INC: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/loop/forall.hpp:59

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 16 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

17 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 22 FP arithmetical operations:

12: addition or subtraction (5 inside FMA instructions)
6: multiply (5 inside FMA instructions)
4: divide

The binary loop is loading 281 bytes (35 double precision FP elements). The binary loop is storing 72 bytes (9 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.06 FP operations per loaded or stored byte.

General properties

nb instructions	70
nb uops	73
loop length	319
used x86 registers	15
used mmx registers	0
used xmm registers	16
used ymm registers	0
used zmm registers	0
nb stack references	17
ADD-SUB / MUL ratio	7.00

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	12.17 cycles
front end	12.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	7.20	7.20	12.00	12.00	4.50	7.20	7.20	4.50	4.50	4.50	7.20	12.00
cycles	7.20	7.20	12.00	12.00	4.50	7.20	7.20	4.50	4.50	4.50	7.20	12.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	16.00
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	12.17
Dispatch	12.00
DIV/SQRT	16.00
Data deps.	0.00
Overall L1	16.00

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	7%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	100%

INT+FP

all	5%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	50%

Vector efficiency ratios

INT

all	10%
load	9%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	7%

all	13%
load	12%
store	12%
mul	12%
add-sub	12%
fma	12%
div/sqrt	12%
other	25%

INT+FP

all	12%
load	11%
store	12%
mul	12%
add-sub	12%
fma	12%
div/sqrt	12%
other	16%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 16.00 cycles. At this rate:

9% of peak load performance is reached (17.56 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (4.50 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4be3d0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
MOV -0x58(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x88(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (,%RBX,8),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0xb8(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x60(%RBP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x98(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%RCX,%RDI,1),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0x90(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%R10,%R9,8),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD %RCX,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0x78(%RBP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %RDX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
XOR %R10D,%R10D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0x70(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
TESTB $0x1,-0x40(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	2	0.33	scal (1.6%)
JE 4be4ce <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl1EEEEJNS2_3ForILl2ENS_6policy4loop9loop_execEJNS8_ILl3ESB_JNS8_ILl4ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEEEEE4execIRNS0_8LoopDataINS5_4listIJSH_EEENS5_5tupleIJNS_4impl4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPST_EEST_EENSP_INSR_INSS_5GroupElPSX_EESX_EENSP_INSQ_24strided_numeric_iteratorINSS_5ZoneKElPS12_EES12_EENSP_INS11_INSS_5ZoneJElPS16_EES16_EENSP_INS11_INSS_5ZoneIElPS1A_EES1A_EEEEENSN_IJEEEJZNK9SweepSdomclINSS_11ArchLayoutTINSS_12ArchT_OpenMPENSS_11LayoutT_DGZEEEEEvT_RNSS_4Core9DataStoreENSS_6SdomIdEEUlST_SX_S12_S16_S1A_E_EEEEEvOS1M_._omp_fn.0+0xdde>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSD (%R12),%XMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x68(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VADDSD %XMM5,%XMM5,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
MOV -0x48(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD (%R13),%XMM10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VDIVSD (%R10),%XMM0,%XMM1	1	1	0	0.33	0.33	0	0	0	0	0	0	0	0.33	13-15	4	scal (12.5%)
VMOVSD (%RBX),%XMM13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMULSD (%RAX),%XMM1,%XMM6	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VADDSD %XMM10,%XMM10,%XMM11	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VADDSD %XMM13,%XMM13,%XMM14	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD (%R8),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x70(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VDIVSD (%R9),%XMM11,%XMM12	1	1	0	0.33	0.33	0	0	0	0	0	0	0	0.33	13-15	4	scal (12.5%)
VDIVSD (%R11),%XMM14,%XMM15	1	1	0	0.33	0.33	0	0	0	0	0	0	0	0.33	13-15	4	scal (12.5%)
VFMADD231SD (%RSI),%XMM12,%XMM6	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VADDSD %XMM1,%XMM15,%XMM4	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VFMADD132SD (%RDX),%XMM2,%XMM15	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VADDSD (%RDI),%XMM12,%XMM8	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
MOV -0x40(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV $0x1,%R10D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VADDSD %XMM4,%XMM8,%XMM9	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VADDSD %XMM6,%XMM15,%XMM7	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
ADD %R15,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %R14,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VDIVSD %XMM9,%XMM7,%XMM10	1	1	0	0	0	0	0	0	0	0	0	0	0	13-15	4	scal (12.5%)
ADD %R14,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVSD %XMM10,(%RCX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVAPD %XMM10,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VFMSUB213SD (%RSI),%XMM3,%XMM11	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVAPD %XMM10,%XMM12	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
ADD %R14,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVSD %XMM11,(%RSI)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VFMSUB213SD (%RDX),%XMM3,%XMM12	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD %XMM12,(%RDX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VFMSUB213SD (%RAX),%XMM3,%XMM10	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
ADD %R15,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVSD %XMM10,(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %R15,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP %RBX,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4be612 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl1EEEEJNS2_3ForILl2ENS_6policy4loop9loop_execEJNS8_ILl3ESB_JNS8_ILl4ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEEEEE4execIRNS0_8LoopDataINS5_4listIJSH_EEENS5_5tupleIJNS_4impl4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPST_EEST_EENSP_INSR_INSS_5GroupElPSX_EESX_EENSP_INSQ_24strided_numeric_iteratorINSS_5ZoneKElPS12_EES12_EENSP_INS11_INSS_5ZoneJElPS16_EES16_EENSP_INS11_INSS_5ZoneIElPS1A_EES1A_EEEEENSN_IJEEEJZNK9SweepSdomclINSS_11ArchLayoutTINSS_12ArchT_OpenMPENSS_11LayoutT_DGZEEEEEvT_RNSS_4Core9DataStoreENSS_6SdomIdEEUlST_SX_S12_S16_S1A_E_EEEEEvOS1M_._omp_fn.0+0xf22>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R10,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0x68(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RBX,-0x68(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
INCQ -0x50(%RBP)	3	0.20	0.20	0.33	0.33	0.50	0.20	0.20	0.50	0.50	0.50	0.20	0.33	1	0.50	scal (12.5%)
MOV -0xa0(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0xa8(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0xb0(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x50(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %RAX,-0x58(%RBP)	2	0.20	0.20	0.33	0.33	0.50	0.20	0.20	0.50	0.50	0.50	0.20	0.33	1	0.50	scal (12.5%)
ADD %RDI,-0x60(%RBP)	2	0.20	0.20	0.33	0.33	0.50	0.20	0.20	0.50	0.50	0.50	0.20	0.33	1	0.50	scal (12.5%)
ADD %RCX,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %RCX,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP %R8,-0x80(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
JNE 4be3d0 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl1EEEEJNS2_3ForILl2ENS_6policy4loop9loop_execEJNS8_ILl3ESB_JNS8_ILl4ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEEEEE4execIRNS0_8LoopDataINS5_4listIJSH_EEENS5_5tupleIJNS_4impl4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPST_EEST_EENSP_INSR_INSS_5GroupElPSX_EESX_EENSP_INSQ_24strided_numeric_iteratorINSS_5ZoneKElPS12_EES12_EENSP_INS11_INSS_5ZoneJElPS16_EES16_EENSP_INS11_INSS_5ZoneIElPS1A_EES1A_EEEEENSN_IJEEEJZNK9SweepSdomclINSS_11ArchLayoutTINSS_12ArchT_OpenMPENSS_11LayoutT_DGZEEEEEvT_RNSS_4Core9DataStoreENSS_6SdomIdEEUlST_SX_S12_S16_S1A_E_EEEEEvOS1M_._omp_fn.0+0xce0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Function	void RAJA::internal::StatementExecutor, RAJA::statement::For<2l, RAJA::policy::loop::loop_exec, RAJA::statement::For<3l, RAJA::policy::loop::loop_exec, RAJA::statement::For<4l, RAJA::policy::loop::loop_exec, RAJA::statement::Lambda<0l> > > > > >::exec, RAJA::statement::For<2l, RAJA::policy::loop::loop_exec, RAJA::statement::For<3l, RAJA::policy::loop::loop_exec, RAJA::statement::For<4l, RAJA::policy::loop::loop_exec, RAJA::statement::Lambda<0l> > > > > >, camp::tuple, Kripke::Direction>, RAJA::impl::Span, Kripke::Group>, RAJA::impl::Span, Kripke::ZoneK>, RAJA::impl::Span, Kripke::ZoneJ>, RAJA::impl::Span, Kripke::ZoneI> >, camp::tuple<>, SweepSdom::operator() >(Kripke::ArchLayoutT, Kripke::Core::DataStore&, Kripke::SdomId) const::{lambda(Kripke::Direction, Kripke::Group, Kripke::ZoneK, Kripke::ZoneJ, Kripke::ZoneI)#1}>&>(RAJA::internal::LoopData, RAJA::statement::For<2l, RAJA::policy::loop::loop_exec, RAJA::statement::For<3l, RAJA::policy::loop::loop_exec, RAJA::statement::For<4l, RAJA::policy::loop::loop_exec, RAJA::statement::Lambda<0l> > > > > >, camp::tuple, Kripke::Direction>, RAJA::impl::Span, Kripke::Group>, RAJA::impl::Span, Kripke::ZoneK>, RAJA::impl::Span, Kripke::ZoneJ>, RAJA::impl::Span, Kripke::ZoneI> >, camp::tuple<>, SweepSdom::operator() >(Kripke::ArchLayoutT, Kripke::Core::DataStore&, Kripke::SdomId) const::{lambda(Kripke::Direction, Kripke::Group, Kripke::ZoneK, Kripke::ZoneJ, Kripke::ZoneI)#1}>&) [clone ._omp_fn.0]
Source file and lines	forall.hpp:59-59
Module	exec

The loop is defined in:

/home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/Operators.hpp:304
/home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/loop/forall.hpp:59
/home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/View.hpp:107
/home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/src/Kripke/Kernel/SweepSubdomain.cpp:87-105

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Workaround

Reduce the number of division or square root instructions:
- If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
Check whether you really need double precision. If not, switch to single precision to speedup execution

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 16.00 to 11.67 cycles (1.37x speedup).

FMA

Detected 5 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

ADD: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/loop/forall.hpp:59
- /home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/loop/forall.hpp:59
INC: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/loop/forall.hpp:59

Type of elements and instruction set

17 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 22 FP arithmetical operations:

12: addition or subtraction (5 inside FMA instructions)
6: multiply (5 inside FMA instructions)
4: divide

The binary loop is loading 273 bytes (34 double precision FP elements). The binary loop is storing 56 bytes (7 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.07 FP operations per loaded or stored byte.

General properties

nb instructions	67
nb uops	70
loop length	307
used x86 registers	15
used mmx registers	0
used xmm registers	16
used ymm registers	0
used zmm registers	0
nb stack references	16
ADD-SUB / MUL ratio	7.00

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	11.67 cycles
front end	11.67 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	7.20	7.20	11.67	11.67	3.50	7.20	7.20	3.50	3.50	3.50	7.20	11.67
cycles	7.20	7.20	11.67	11.67	3.50	7.20	7.20	3.50	3.50	3.50	7.20	11.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	16.00
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	11.67
Dispatch	11.67
DIV/SQRT	16.00
Data deps.	0.00
Overall L1	16.00

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	7%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	100%

INT+FP

all	6%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	50%

Vector efficiency ratios

INT

all	10%
load	9%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	7%

all	13%
load	12%
store	12%
mul	12%
add-sub	12%
fma	12%
div/sqrt	12%
other	25%

INT+FP

all	12%
load	11%
store	12%
mul	12%
add-sub	12%
fma	12%
div/sqrt	12%
other	16%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 16.00 cycles. At this rate:

8% of peak load performance is reached (17.06 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (3.50 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4be3d0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
MOV -0x58(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x88(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (,%RBX,8),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0xb8(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x60(%RBP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x98(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%RCX,%RDI,1),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0x90(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%R10,%R9,8),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD %RCX,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0x78(%RBP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %RDX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
XOR %R10D,%R10D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0x70(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
TESTB $0x1,-0x40(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	2	0.33	scal (1.6%)
JE 4be4ce <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl1EEEEJNS2_3ForILl2ENS_6policy4loop9loop_execEJNS8_ILl3ESB_JNS8_ILl4ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEEEEE4execIRNS0_8LoopDataINS5_4listIJSH_EEENS5_5tupleIJNS_4impl4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPST_EEST_EENSP_INSR_INSS_5GroupElPSX_EESX_EENSP_INSQ_24strided_numeric_iteratorINSS_5ZoneKElPS12_EES12_EENSP_INS11_INSS_5ZoneJElPS16_EES16_EENSP_INS11_INSS_5ZoneIElPS1A_EES1A_EEEEENSN_IJEEEJZNK9SweepSdomclINSS_11ArchLayoutTINSS_12ArchT_OpenMPENSS_11LayoutT_DGZEEEEEvT_RNSS_4Core9DataStoreENSS_6SdomIdEEUlST_SX_S12_S16_S1A_E_EEEEEvOS1M_._omp_fn.0+0xdde>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSD (%R12),%XMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x68(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VADDSD %XMM5,%XMM5,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
MOV -0x48(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD (%R13),%XMM10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VDIVSD (%R10),%XMM0,%XMM1	1	1	0	0.33	0.33	0	0	0	0	0	0	0	0.33	13-15	4	scal (12.5%)
VMOVSD (%RBX),%XMM13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMULSD (%RAX),%XMM1,%XMM6	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VADDSD %XMM10,%XMM10,%XMM11	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VADDSD %XMM13,%XMM13,%XMM14	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD (%R8),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x70(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VDIVSD (%R9),%XMM11,%XMM12	1	1	0	0.33	0.33	0	0	0	0	0	0	0	0.33	13-15	4	scal (12.5%)
VDIVSD (%R11),%XMM14,%XMM15	1	1	0	0.33	0.33	0	0	0	0	0	0	0	0.33	13-15	4	scal (12.5%)
VFMADD231SD (%RSI),%XMM12,%XMM6	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VADDSD %XMM1,%XMM15,%XMM4	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VFMADD132SD (%RDX),%XMM2,%XMM15	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VADDSD (%RDI),%XMM12,%XMM8	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
MOV -0x40(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV $0x1,%R10D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VADDSD %XMM4,%XMM8,%XMM9	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VADDSD %XMM6,%XMM15,%XMM7	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
ADD %R15,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %R14,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VDIVSD %XMM9,%XMM7,%XMM10	1	1	0	0	0	0	0	0	0	0	0	0	0	13-15	4	scal (12.5%)
ADD %R14,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVSD %XMM10,(%RCX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVAPD %XMM10,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VFMSUB213SD (%RSI),%XMM3,%XMM11	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVAPD %XMM10,%XMM12	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
ADD %R14,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVSD %XMM11,(%RSI)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VFMSUB213SD (%RDX),%XMM3,%XMM12	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD %XMM12,(%RDX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VFMSUB213SD (%RAX),%XMM3,%XMM10	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
ADD %R15,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVSD %XMM10,(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %R15,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP %RBX,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4be612 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl1EEEEJNS2_3ForILl2ENS_6policy4loop9loop_execEJNS8_ILl3ESB_JNS8_ILl4ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEEEEE4execIRNS0_8LoopDataINS5_4listIJSH_EEENS5_5tupleIJNS_4impl4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPST_EEST_EENSP_INSR_INSS_5GroupElPSX_EESX_EENSP_INSQ_24strided_numeric_iteratorINSS_5ZoneKElPS12_EES12_EENSP_INS11_INSS_5ZoneJElPS16_EES16_EENSP_INS11_INSS_5ZoneIElPS1A_EES1A_EEEEENSN_IJEEEJZNK9SweepSdomclINSS_11ArchLayoutTINSS_12ArchT_OpenMPENSS_11LayoutT_DGZEEEEEvT_RNSS_4Core9DataStoreENSS_6SdomIdEEUlST_SX_S12_S16_S1A_E_EEEEEvOS1M_._omp_fn.0+0xf22>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
INCQ -0x50(%RBP)	3	0.20	0.20	0.33	0.33	0.50	0.20	0.20	0.50	0.50	0.50	0.20	0.33	1	0.50	scal (12.5%)
MOV -0xa0(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0xa8(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0xb0(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x50(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %RAX,-0x58(%RBP)	2	0.20	0.20	0.33	0.33	0.50	0.20	0.20	0.50	0.50	0.50	0.20	0.33	1	0.50	scal (12.5%)
ADD %RDI,-0x60(%RBP)	2	0.20	0.20	0.33	0.33	0.50	0.20	0.20	0.50	0.50	0.50	0.20	0.33	1	0.50	scal (12.5%)
ADD %RCX,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %RCX,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP %R8,-0x80(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
JNE 4be3d0 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl1EEEEJNS2_3ForILl2ENS_6policy4loop9loop_execEJNS8_ILl3ESB_JNS8_ILl4ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEEEEE4execIRNS0_8LoopDataINS5_4listIJSH_EEENS5_5tupleIJNS_4impl4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPST_EEST_EENSP_INSR_INSS_5GroupElPSX_EESX_EENSP_INSQ_24strided_numeric_iteratorINSS_5ZoneKElPS12_EES12_EENSP_INS11_INSS_5ZoneJElPS16_EES16_EENSP_INS11_INSS_5ZoneIElPS1A_EES1A_EEEEENSN_IJEEEJZNK9SweepSdomclINSS_11ArchLayoutTINSS_12ArchT_OpenMPENSS_11LayoutT_DGZEEEEEvT_RNSS_4Core9DataStoreENSS_6SdomIdEEUlST_SX_S12_S16_S1A_E_EEEEEvOS1M_._omp_fn.0+0xce0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

FMA

Workaround

Complex instructions

Details

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Complex instructions

Details

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

FMA

Workaround

Complex instructions

Details

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

FMA

Workaround

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop