OV - exec - Function Kripke::ParallelComm::testRecieves()

	Function: Kripke::ParallelComm::testRecieves()	Module: exec	Source: ParallelComm.cpp:214-251 [...]	Coverage (incl. loops): 0.02% \| (excl. loops): 0.00%

/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/stl_construct.h: 119 - 119

--------------------------------------------------------------------------------

119:       ::new((void*)__p) _Tp(std::forward<_Args>(__args)...);

/home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/src/Kripke/ParallelComm.cpp: 214 - 251

--------------------------------------------------------------------------------

214: void ParallelComm::testRecieves(void){

215: #ifdef KRIPKE_USE_MPI

216:   // Check for any recv requests that have completed

217:   int num_requests = recv_requests.size();

218:   bool done = false;

219:   while(!done && num_requests > 0){

[...]

226:     MPI_Testany(num_requests, &recv_requests[0], &index, &complete_flag, &recv_status[0]);

227:

228:     if(complete_flag != 0){

229:

230:       // get subdomain that this completed for

231:       int sdom_id = recv_subdomains[index];

[...]

239:       for(size_t i = 0;i < queue_sdom_ids.size();++ i){

240:         if(queue_sdom_ids[i] == sdom_id){

241:           queue_depends[i] --;

[...]

251: }

/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/stl_uninitialized.h: 667 - 667

--------------------------------------------------------------------------------

667: 	      ++__first;

/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/stl_vector.h: 385 - 1131

--------------------------------------------------------------------------------

385:       _M_deallocate(pointer __p, size_t __n)

[...]

400: 	this->_M_impl._M_end_of_storage = this->_M_impl._M_start + __n;

[...]

992:       size() const _GLIBCXX_NOEXCEPT

993:       { return size_type(this->_M_impl._M_finish - this->_M_impl._M_start); }

[...]

1131: 	return *(this->_M_impl._M_start + __n);

/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/new_allocator.h: 151 - 172

--------------------------------------------------------------------------------

151: 	return static_cast<_Tp*>(_GLIBCXX_OPERATOR_NEW(__n * sizeof(_Tp)));

[...]

172: 	_GLIBCXX_OPERATOR_DELETE(_GLIBCXX_SIZED_DEALLOC(__p, __n));

/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/stl_algobase.h: 438 - 1146

--------------------------------------------------------------------------------

438: 	{ *__to = std::move(*__from); }

[...]

450: 	  const ptrdiff_t _Num = __last - __first;

451: 	  if (__builtin_expect(_Num > 1, true))

452: 	    __builtin_memmove(__result, __first, sizeof(_Tp) * _Num);

453: 	  else if (_Num == 1)

[...]

939:       for (; __first != __last; ++__first)

940: 	*__first = __value;

[...]

1146:       if (__n <= 0)

/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/stl_iterator.h: 1068 - 1139

--------------------------------------------------------------------------------

1068:       : _M_current(__i) { }

[...]

1139:       { return __normal_iterator(_M_current + __n); }

/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/vector.tcc: 184 - 186

--------------------------------------------------------------------------------

184:       if (__position + 1 != end())

185: 	_GLIBCXX_MOVE3(__position + 1, end(), __position);

186:       --this->_M_impl._M_finish;

0x4e3250 PUSH	%RBP

0x4e3251 MOV	%RSP,%RBP

0x4e3254 PUSH	%R15

0x4e3256 LEA	-0x38(%RBP),%RDX

0x4e325a PUSH	%R14

0x4e325c MOV	%RDI,%R14

0x4e325f PUSH	%R13

0x4e3261 PUSH	%R12

0x4e3263 PUSH	%RBX

0x4e3264 SUB	$0x28,%RSP

0x4e3268 MOV	0x30(%RDI),%RAX

0x4e326c MOV	%RDX,-0x48(%RBP)

0x4e3270 SUB	0x28(%RDI),%RAX

0x4e3274 SAR	$0x2,%RAX

0x4e3278 LEA	-0x34(%RBP),%RDI

0x4e327c MOV	%RDI,-0x50(%RBP)

0x4e3280 TEST	%EAX,%EAX

0x4e3282 JLE	4e3493

0x4e3288 MOVSXD	%EAX,%R13

(2337) 0x4e328b LEA	(%R13,%R13,4),%R12

(2337) 0x4e3290 SAL	$0x2,%R12

(2337) 0x4e3294 MOV	%R12,%RDI

(2337) 0x4e3297 CALL	403220 <_Znwm@plt>

(2337) 0x4e329c MOVQ	$0,(%RAX)

(2337) 0x4e32a3 MOVQ	$0,0x8(%RAX)

(2337) 0x4e32ab MOVL	$0,0x10(%RAX)

(2337) 0x4e32b2 MOV	%R13D,%R15D

(2337) 0x4e32b5 MOV	%RAX,%RBX

(2337) 0x4e32b8 LEA	(%RAX,%R12,1),%RCX

(2337) 0x4e32bc LEA	0x14(%RAX),%R10

(2337) 0x4e32c0 CMP	$0x1,%R13

(2337) 0x4e32c4 JE	4e3468

(2337) 0x4e32ca MOV	%RCX,%R8

(2337) 0x4e32cd SUB	%R10,%R8

(2337) 0x4e32d0 SUB	$0x14,%R8

(2337) 0x4e32d4 SHR	$0x2,%R8

(2337) 0x4e32d8 MOV	$0xccccccccccccccd,%RSI

(2337) 0x4e32e2 IMUL	%RSI,%R8

(2337) 0x4e32e6 INC	%R8

(2337) 0x4e32e9 AND	$0x7,%R8D

(2337) 0x4e32ed JE	4e33bd

(2337) 0x4e32f3 CMP	$0x1,%R8

(2337) 0x4e32f7 JE	4e339f

(2337) 0x4e32fd CMP	$0x2,%R8

(2337) 0x4e3301 JE	4e3389

(2337) 0x4e3307 CMP	$0x3,%R8

(2337) 0x4e330b JE	4e3374

(2337) 0x4e330d CMP	$0x4,%R8

(2337) 0x4e3311 JE	4e335f

(2337) 0x4e3313 CMP	$0x5,%R8

(2337) 0x4e3317 JE	4e334a

(2337) 0x4e3319 CMP	$0x6,%R8

(2337) 0x4e331d JE	4e3334

(2337) 0x4e331f VMOVDQU	(%RAX),%XMM0

(2337) 0x4e3323 MOV	0x10(%RAX),%R9D

(2337) 0x4e3327 VMOVDQU	%XMM0,0x14(%RAX)

(2337) 0x4e332c MOV	%R9D,0x10(%R10)

(2337) 0x4e3330 LEA	0x28(%RAX),%R10

(2337) 0x4e3334 VMOVDQU	(%RBX),%XMM1

(2337) 0x4e3338 ADD	$0x14,%R10

(2337) 0x4e333c VMOVDQU	%XMM1,-0x14(%R10)

(2337) 0x4e3342 MOV	0x10(%RBX),%R11D

(2337) 0x4e3346 MOV	%R11D,-0x4(%R10)

(2337) 0x4e334a VMOVDQU	(%RBX),%XMM2

(2337) 0x4e334e ADD	$0x14,%R10

(2337) 0x4e3352 VMOVDQU	%XMM2,-0x14(%R10)

(2337) 0x4e3358 MOV	0x10(%RBX),%EAX

(2337) 0x4e335b MOV	%EAX,-0x4(%R10)

(2337) 0x4e335f VMOVDQU	(%RBX),%XMM3

(2337) 0x4e3363 ADD	$0x14,%R10

(2337) 0x4e3367 VMOVDQU	%XMM3,-0x14(%R10)

(2337) 0x4e336d MOV	0x10(%RBX),%EDI

(2337) 0x4e3370 MOV	%EDI,-0x4(%R10)

(2337) 0x4e3374 VMOVDQU	(%RBX),%XMM4

(2337) 0x4e3378 ADD	$0x14,%R10

(2337) 0x4e337c VMOVDQU	%XMM4,-0x14(%R10)

(2337) 0x4e3382 MOV	0x10(%RBX),%EDX

(2337) 0x4e3385 MOV	%EDX,-0x4(%R10)

(2337) 0x4e3389 VMOVDQU	(%RBX),%XMM5

(2337) 0x4e338d ADD	$0x14,%R10

(2337) 0x4e3391 VMOVDQU	%XMM5,-0x14(%R10)

(2337) 0x4e3397 MOV	0x10(%RBX),%R8D

(2337) 0x4e339b MOV	%R8D,-0x4(%R10)

(2337) 0x4e339f VMOVDQU	(%RBX),%XMM6

(2337) 0x4e33a3 ADD	$0x14,%R10

(2337) 0x4e33a7 VMOVDQU	%XMM6,-0x14(%R10)

(2337) 0x4e33ad MOV	0x10(%RBX),%ESI

(2337) 0x4e33b0 MOV	%ESI,-0x4(%R10)

(2337) 0x4e33b4 CMP	%R10,%RCX

(2337) 0x4e33b7 JE	4e3468

  (2339) 0x4e33bd VMOVDQU	(%RBX),%XMM7

  (2339) 0x4e33c1 ADD	$0xa0,%R10

  (2339) 0x4e33c8 VMOVDQU	%XMM7,-0xa0(%R10)

  (2339) 0x4e33d1 MOV	0x10(%RBX),%R9D

  (2339) 0x4e33d5 MOV	%R9D,-0x90(%R10)

  (2339) 0x4e33dc VMOVDQU	(%RBX),%XMM8

  (2339) 0x4e33e0 VMOVDQU	%XMM8,-0x8c(%R10)

  (2339) 0x4e33e9 MOV	0x10(%RBX),%R11D

  (2339) 0x4e33ed MOV	%R11D,-0x7c(%R10)

  (2339) 0x4e33f1 VMOVDQU	(%RBX),%XMM9

  (2339) 0x4e33f5 VMOVDQU	%XMM9,-0x78(%R10)

  (2339) 0x4e33fb MOV	0x10(%RBX),%EAX

  (2339) 0x4e33fe MOV	%EAX,-0x68(%R10)

  (2339) 0x4e3402 VMOVDQU	(%RBX),%XMM10

  (2339) 0x4e3406 VMOVDQU	%XMM10,-0x64(%R10)

  (2339) 0x4e340c MOV	0x10(%RBX),%EDI

  (2339) 0x4e340f MOV	%EDI,-0x54(%R10)

  (2339) 0x4e3413 VMOVDQU	(%RBX),%XMM11

  (2339) 0x4e3417 VMOVDQU	%XMM11,-0x50(%R10)

  (2339) 0x4e341d MOV	0x10(%RBX),%EDX

  (2339) 0x4e3420 MOV	%EDX,-0x40(%R10)

  (2339) 0x4e3424 VMOVDQU	(%RBX),%XMM12

  (2339) 0x4e3428 VMOVDQU	%XMM12,-0x3c(%R10)

  (2339) 0x4e342e MOV	0x10(%RBX),%R8D

  (2339) 0x4e3432 MOV	%R8D,-0x2c(%R10)

  (2339) 0x4e3436 VMOVDQU	(%RBX),%XMM13

  (2339) 0x4e343a VMOVDQU	%XMM13,-0x28(%R10)

  (2339) 0x4e3440 MOV	0x10(%RBX),%ESI

  (2339) 0x4e3443 MOV	%ESI,-0x18(%R10)

  (2339) 0x4e3447 VMOVDQU	(%RBX),%XMM14

  (2339) 0x4e344b VMOVDQU	%XMM14,-0x14(%R10)

  (2339) 0x4e3451 MOV	0x10(%RBX),%R9D

  (2339) 0x4e3455 MOV	%R9D,-0x4(%R10)

  (2339) 0x4e3459 CMP	%R10,%RCX

  (2339) 0x4e345c JNE	4e33bd

(2337) 0x4e3462 NOPW	(%RAX,%RAX,1)

(2337) 0x4e3468 MOV	0x28(%R14),%RSI

(2337) 0x4e346c MOV	-0x50(%RBP),%RCX

(2337) 0x4e3470 MOV	-0x48(%RBP),%RDX

(2337) 0x4e3474 MOV	%RBX,%R8

(2337) 0x4e3477 MOV	%R15D,%EDI

(2337) 0x4e347a CALL	403370 <MPI_Testany@plt>

(2337) 0x4e347f MOV	-0x34(%RBP),%R15D

(2337) 0x4e3483 TEST	%R15D,%R15D

(2337) 0x4e3486 JNE	4e34a8

0x4e3488 MOV	%R12,%RSI

0x4e348b MOV	%RBX,%RDI

0x4e348e CALL	403230 <_ZdlPvm@plt>

0x4e3493 ADD	$0x28,%RSP

0x4e3497 POP	%RBX

0x4e3498 POP	%R12

0x4e349a POP	%R13

0x4e349c POP	%R14

0x4e349e POP	%R15

0x4e34a0 POP	%RBP

0x4e34a1 RET

0x4e34a2 NOPW	(%RAX,%RAX,1)

(2337) 0x4e34a8 MOVSXD	-0x38(%RBP),%R10

(2337) 0x4e34ac MOV	0x28(%R14),%R11

(2337) 0x4e34b0 MOV	0x40(%R14),%RCX

(2337) 0x4e34b4 LEA	(%R11,%R10,4),%RDI

(2337) 0x4e34b8 MOV	0x30(%R14),%RAX

(2337) 0x4e34bc LEA	0x4(%RDI),%RSI

(2337) 0x4e34c0 MOV	(%RCX,%R10,4),%R15D

(2337) 0x4e34c4 MOV	%R10,%R9

(2337) 0x4e34c7 CMP	%RSI,%RAX

(2337) 0x4e34ca JE	4e34f0

(2337) 0x4e34cc MOV	%RAX,%R8

(2337) 0x4e34cf SUB	%RSI,%R8

(2337) 0x4e34d2 CMP	$0x4,%R8

(2337) 0x4e34d6 JLE	4e3680

(2337) 0x4e34dc MOV	%R8,%RDX

(2337) 0x4e34df CALL	403440 <memmove@plt>

(2337) 0x4e34e4 MOV	0x40(%R14),%RCX

(2337) 0x4e34e8 MOV	0x30(%R14),%RAX

(2337) 0x4e34ec MOVSXD	-0x38(%RBP),%R9

(2337) 0x4e34f0 LEA	(%RCX,%R9,4),%RDI

(2337) 0x4e34f4 MOV	0x48(%R14),%R10

(2337) 0x4e34f8 SUB	$0x4,%RAX

(2337) 0x4e34fc LEA	0x4(%RDI),%RSI

(2337) 0x4e3500 MOV	%RAX,0x30(%R14)

(2337) 0x4e3504 CMP	%RSI,%R10

(2337) 0x4e3507 JE	4e3522

(2337) 0x4e3509 MOV	%R10,%RDX

(2337) 0x4e350c SUB	%RSI,%RDX

(2337) 0x4e350f CMP	$0x4,%RDX

(2337) 0x4e3513 JLE	4e3694

(2337) 0x4e3519 CALL	403440 <memmove@plt>

(2337) 0x4e351e MOV	0x48(%R14),%R10

(2337) 0x4e3522 MOV	0x60(%R14),%RDI

(2337) 0x4e3526 MOV	0x58(%R14),%R11

(2337) 0x4e352a MOV	%RDI,%R8

(2337) 0x4e352d SUB	$0x4,%R10

(2337) 0x4e3531 SUB	%R11,%R8

(2337) 0x4e3534 MOV	%R10,0x48(%R14)

(2337) 0x4e3538 SAR	$0x2,%R8

(2337) 0x4e353c CMP	%RDI,%R11

(2337) 0x4e353f JE	4e3648

(2337) 0x4e3545 LEA	-0x1(%R8),%RDX

(2337) 0x4e3549 XOR	%ECX,%ECX

(2337) 0x4e354b AND	$0x7,%EDX

(2337) 0x4e354e CMP	%R15D,(%R11)

(2337) 0x4e3551 JE	4e3668

(2337) 0x4e3557 MOV	$0x1,%ECX

(2337) 0x4e355c CMP	%R8,%RCX

(2337) 0x4e355f JAE	4e3648

(2337) 0x4e3565 TEST	%RDX,%RDX

(2337) 0x4e3568 JE	4e35e5

(2337) 0x4e356a CMP	$0x1,%RDX

(2337) 0x4e356e JE	4e35d3

(2337) 0x4e3570 CMP	$0x2,%RDX

(2337) 0x4e3574 JE	4e35c6

(2337) 0x4e3576 CMP	$0x3,%RDX

(2337) 0x4e357a JE	4e35b9

(2337) 0x4e357c CMP	$0x4,%RDX

(2337) 0x4e3580 JE	4e35ac

(2337) 0x4e3582 CMP	$0x5,%RDX

(2337) 0x4e3586 JE	4e359f

(2337) 0x4e3588 CMP	$0x6,%RDX

(2337) 0x4e358c JNE	4e3672

(2337) 0x4e3592 CMP	%R15D,(%R11,%RCX,4)

(2337) 0x4e3596 JE	4e3668

(2337) 0x4e359c INC	%RCX

(2337) 0x4e359f CMP	%R15D,(%R11,%RCX,4)

(2337) 0x4e35a3 JE	4e3668

(2337) 0x4e35a9 INC	%RCX

(2337) 0x4e35ac CMP	%R15D,(%R11,%RCX,4)

(2337) 0x4e35b0 JE	4e3668

(2337) 0x4e35b6 INC	%RCX

(2337) 0x4e35b9 CMP	%R15D,(%R11,%RCX,4)

(2337) 0x4e35bd JE	4e3668

(2337) 0x4e35c3 INC	%RCX

(2337) 0x4e35c6 CMP	%R15D,(%R11,%RCX,4)

(2337) 0x4e35ca JE	4e3668

(2337) 0x4e35d0 INC	%RCX

(2337) 0x4e35d3 CMP	%R15D,(%R11,%RCX,4)

(2337) 0x4e35d7 JE	4e3668

(2337) 0x4e35dd INC	%RCX

(2337) 0x4e35e0 CMP	%R8,%RCX

(2337) 0x4e35e3 JAE	4e3648

  (2338) 0x4e35e5 CMP	%R15D,(%R11,%RCX,4)

  (2338) 0x4e35e9 JE	4e3668

  (2338) 0x4e35eb LEA	0x1(%RCX),%R9

  (2338) 0x4e35ef MOV	%R9,%RCX

  (2338) 0x4e35f2 CMP	%R15D,(%R11,%R9,4)

  (2338) 0x4e35f6 JE	4e3668

  (2338) 0x4e35f8 INC	%RCX

  (2338) 0x4e35fb CMP	%R15D,(%R11,%RCX,4)

  (2338) 0x4e35ff JE	4e3668

  (2338) 0x4e3601 LEA	0x2(%R9),%RCX

  (2338) 0x4e3605 CMP	%R15D,0x8(%R11,%R9,4)

  (2338) 0x4e360a JE	4e3668

  (2338) 0x4e360c LEA	0x3(%R9),%RCX

  (2338) 0x4e3610 CMP	%R15D,0xc(%R11,%R9,4)

  (2338) 0x4e3615 JE	4e3668

  (2338) 0x4e3617 LEA	0x4(%R9),%RCX

  (2338) 0x4e361b CMP	%R15D,0x10(%R11,%R9,4)

  (2338) 0x4e3620 JE	4e3668

  (2338) 0x4e3622 LEA	0x5(%R9),%RCX

  (2338) 0x4e3626 CMP	%R15D,0x14(%R11,%R9,4)

  (2338) 0x4e362b JE	4e3668

  (2338) 0x4e362d LEA	0x6(%R9),%RCX

  (2338) 0x4e3631 CMP	%R15D,0x18(%R11,%R9,4)

  (2338) 0x4e3636 JE	4e3668

  (2338) 0x4e3638 LEA	0x7(%R9),%RCX

  (2338) 0x4e363c CMP	%R8,%RCX

  (2338) 0x4e363f JB	4e35e5

(2337) 0x4e3641 NOPL	(%RAX)

(2337) 0x4e3648 MOV	%R12,%RSI

(2337) 0x4e364b MOV	%RBX,%RDI

(2337) 0x4e364e DEC	%R13

(2337) 0x4e3651 CALL	403230 <_ZdlPvm@plt>

(2337) 0x4e3656 TEST	%R13D,%R13D

(2337) 0x4e3659 JG	4e328b

0x4e365f JMP	4e3493

0x4e3664 NOPL	(%RAX)

(2337) 0x4e3668 MOV	0x70(%R14),%R15

(2337) 0x4e366c DECL	(%R15,%RCX,4)

(2337) 0x4e3670 JMP	4e3648

(2337) 0x4e3672 CMP	%R15D,0x4(%R11)

(2337) 0x4e3676 JE	4e3668

(2337) 0x4e3678 INC	%RCX

(2337) 0x4e367b JMP	4e3592

(2337) 0x4e3680 JNE	4e34f0

(2337) 0x4e3686 MOV	0x4(%RDI),%EDX

(2337) 0x4e3689 MOV	%EDX,(%RDI)

(2337) 0x4e368b MOVSXD	-0x38(%RBP),%R9

(2337) 0x4e368f JMP	4e34f0

(2337) 0x4e3694 JNE	4e3522

(2337) 0x4e369a MOV	0x4(%RDI),%ESI

(2337) 0x4e369d MOV	%ESI,(%RDI)

(2337) 0x4e369f JMP	4e3522

0x4e36a4 MOV	%RAX,%R13

0x4e36a7 JMP	4157f4

0x4e36ac NOPL	(%RAX)

Coverage (%)	Name	Source Location	Module
►94.87+	Kripke::SweepComm::readySubdom[...]	SweepComm.cpp:65	exec
○	Kripke::SweepSolver(Kripke::Co[...]	stl_vector.h:992	exec
○	Kripke::SteadyStateSolver(Krip[...]	stl_vector.h:300	exec
○	main	kripke.cpp:485	exec
○	__libc_start_call_main		libc.so.6
►5.13+	Kripke::SweepSolver(Kripke::Co[...]	stl_vector.h:992	exec
○	Kripke::SteadyStateSolver(Krip[...]	stl_vector.h:300	exec
○	main	kripke.cpp:485	exec
○	__libc_start_call_main		libc.so.6

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_5

Source file and lines	ParallelComm.cpp:214-251
Module	exec

The function is defined in:

/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/stl_construct.h:119
/home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/src/Kripke/ParallelComm.cpp:214-219,226-231,239-241,251
/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/stl_uninitialized.h:667
/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/stl_vector.h:385,400,992-993,1131
/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/new_allocator.h:151,172
/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/stl_algobase.h:438,450-453,939-940,1146
/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/stl_iterator.h:1068,1139
/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/vector.tcc:184-186

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 10% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 6.17 to 0.41 cycles (15.16x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

operator delete(void*, unsigned long): 1 occurrences►

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 16 bytes. The binary function is storing 16 bytes.

General properties

nb instructions	36
nb uops	37
loop length	112
used x86 registers	11
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	6.17 cycles
front end	6.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	1.50	1.13	3.00	3.00	4.50	0.93	1.50	4.50	4.50	4.50	0.93	3.00
cycles	1.50	1.13	3.00	3.00	4.50	0.93	1.50	4.50	4.50	4.50	0.93	3.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.17
Dispatch	4.50
Overall L1	6.17

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	10%
load	NA (no load vectorizable/vectorized instructions)
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 6.17 cycles. At this rate:

1% of peak load performance is reached (2.59 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (2.59 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 6.17 to 4.50 cycles (1.37x speedup).

ASM code

In the binary file, the address of the function is: 4e3250

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
LEA -0x38(%RBP),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RDI,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0x28,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x30(%RDI),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RDX,-0x48(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
SUB 0x28(%RDI),%RAX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
SAR $0x2,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
LEA -0x34(%RBP),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDI,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
TEST %EAX,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
JLE 4e3493 <_ZN6Kripke12ParallelComm12testRecievesEv+0x243>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOVSXD %EAX,%R13	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	scal (6.3%)
MOV %R12,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 403230 <_ZdlPvm@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
ADD $0x28,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 4e3493 <_ZN6Kripke12ParallelComm12testRecievesEv+0x243>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JMP 4157f4 <_ZN6Kripke12ParallelComm12testRecievesEv.cold>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_5

Source file and lines	ParallelComm.cpp:214-251
Module	exec

The function is defined in:

/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/stl_construct.h:119
/home/eoseret/qaas_runs_GNR/173-926-6874/intel/Kripke/build/Kripke/src/Kripke/ParallelComm.cpp:214-219,226-231,239-241,251
/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/stl_uninitialized.h:667
/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/stl_vector.h:385,400,992-993,1131
/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/new_allocator.h:151,172
/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/stl_algobase.h:438,450-453,939-940,1146
/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/stl_iterator.h:1068,1139
/cluster/comp/gcc/14.2.0/include/c++/14.2.0/bits/vector.tcc:184-186

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

operator delete(void*, unsigned long): 1 occurrences►

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 16 bytes. The binary function is storing 16 bytes.

General properties

nb instructions	36
nb uops	37
loop length	112
used x86 registers	11
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	6.17 cycles
front end	6.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	1.50	1.13	3.00	3.00	4.50	0.93	1.50	4.50	4.50	4.50	0.93	3.00
cycles	1.50	1.13	3.00	3.00	4.50	0.93	1.50	4.50	4.50	4.50	0.93	3.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.17
Dispatch	4.50
Overall L1	6.17

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	10%
load	NA (no load vectorizable/vectorized instructions)
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 6.17 cycles. At this rate:

1% of peak load performance is reached (2.59 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (2.59 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 4e3250

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
LEA -0x38(%RBP),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RDI,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0x28,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x30(%RDI),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RDX,-0x48(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
SUB 0x28(%RDI),%RAX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
SAR $0x2,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
LEA -0x34(%RBP),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDI,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
TEST %EAX,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
JLE 4e3493 <_ZN6Kripke12ParallelComm12testRecievesEv+0x243>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOVSXD %EAX,%R13	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	scal (6.3%)
MOV %R12,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 403230 <_ZdlPvm@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
ADD $0x28,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 4e3493 <_ZN6Kripke12ParallelComm12testRecievesEv+0x243>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JMP 4157f4 <_ZN6Kripke12ParallelComm12testRecievesEv.cold>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

Name	Coverage (%)	Time (s)
▼Kripke::ParallelComm::testRecieves()–	0.02	0.00
▼Loop 2337 - stl_algobase.h:438-1146 - exec–	0.01	0.05
○Loop 2339 - stl_algobase.h:939-940 - exec	0.00	0.01
○Loop 2338 - ParallelComm.cpp:239-240 - exec	0.00	0.00

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code