	*************************************************
	*                                               *
	*          ONE-View report generation           *
	*                                               *
	*************************************************

[MAQAO] Info: Experiment configuration summary is available adding -dbg=1 in command line

* [MAQAO] Warning: Experiment directory /beegfs/hackathon/users/eoseret/qaas_runs_test/178-663-0018/intel/TeaLeaf/run/oneview_runs/compilers/aocc_3/oneview_results_1786631552 already exists and is reused.
           It can be replaced using --replace in the command line.
[MAQAO] Info: 
[MAQAO] Info: START THE APPLICATION PROFILING
[MAQAO] Info: -> RUNNING THE PROFILER...
[MAQAO] Info:   LPROF has already been run
[MAQAO] Info: STOP THE APPLICATION PROFILING
[MAQAO] Info: 
[MAQAO] Info: START FUNCTIONS AND LOOPS ANALYSIS ...
[MAQAO] Info: STOP FUNCTIONS AND LOOPS ANALYSIS ...
[MAQAO] Info: 
[MAQAO] Info: START THE REPORT GENERATION
[MAQAO] Info: -> ONE-VIEW EXPERIMENT DIRECTORY: /beegfs/hackathon/users/eoseret/qaas_runs_test/178-663-0018/intel/TeaLeaf/run/oneview_runs/compilers/aocc_3/oneview_results_1786631552


+====================================================================================================================+
+                                                    1  -  GLOBAL                                                    +
+====================================================================================================================+


+--------------------------------------------------------------------------------------------------------------------+
+                                             1.1  -  Experiment Summary                                             +
+--------------------------------------------------------------------------------------------------------------------+

  Application:			/beegfs/hackathon/users/eoseret/qaas_runs_test/178-663-0018/intel/TeaLeaf/run/binaries/aocc_3/exec
  Timestamp:			2026-08-13 16:32:32
  Universal Timestamp:		1786631552
  Experiment Type:		MPI; OpenMP; Throughput; 
  Machine:			gmz12.benchmarkcenter.megware.com
  Architecture:			x86_64
  Micro Architecture:		ZEN_V5
  Model Name:			AMD EPYC 9655 96-Core Processor
  Cache Size:			1024 KB
  Number of Cores:		96
  OS Version:			Linux 5.14.0-687.29.1.el9_8.x86_64 #1 SMP PREEMPT_DYNAMIC Thu Jul 23 16:18:48 EDT 2026
  Compilation Options:		
		exec: AMD clang version 17.0.6 (CLANG: AOCC_5.1.0-Build#1994 2025_12_23) /cluster/comp/aocc/5.1.0/bin/clang-17 --driver-mode=g++ -D USE_OMP -I /beegfs/hackathon/users/eoseret/qaas_runs_test/178-663-0018/intel/TeaLeaf/build/TeaLeaf/src/omp -I /beegfs/hackathon/users/eoseret/qaas_runs_test/178-663-0018/intel/TeaLeaf/build/aocc_3/generated -I /beegfs/hackathon/users/eoseret/qaas_runs_test/178-663-0018/intel/TeaLeaf/build/TeaLeaf/driver -O3 -march=znver5 -mprefer-vector-width=256 -ffast-math -g -fno-omit-frame-pointer -fcf-protection=none -nopie -grecord-command-line -D NDEBUG -std=c++17 -O3 -Wall -fopenmp=libomp -MD -MT CMakeFiles/tealeaf.dir/src/omp/cg.cpp.o -MF CMakeFiles/tealeaf.dir/src/omp/cg.cpp.o.d -o CMakeFiles/tealeaf.dir/src/omp/cg.cpp.o -c /beegfs/hackathon/users/eoseret/qaas_runs_test/178-663-0018/intel/TeaLeaf/build/TeaLeaf/src/omp/cg.cpp -I /cluster/hpcx/2.23/ompi5-aocc-mt/include -I /cluster/hpcx/2.23/ompi5-aocc-mt/include/openmpi 
  Number of processes observed:	8
  Number of threads observed:	192
  MAQAO version:		2026.1.0
  MAQAO build:			6d1be1d51c1e63266254997eb301734a7264775d::20260810-150026




+--------------------------------------------------------------------------------------------------------------------+
+                                               1.2  -  Global Metrics                                               +
+--------------------------------------------------------------------------------------------------------------------+

  Total Time:				22.10 s
  Max (Thread Active Time):		16.61 s
  Average Active Time:			11.32 s
  Activity Ratio:			97.7 %
  Average number of active threads:	98.398
  Affinity Stability:			97.4 %
  Time spent in analyzed loops:		53.5 %
  Time spent in analyzed innermost loops: 53.0 %
  Time spent in user code:		54.5 %
  Compilation Options Score:		100
  Array Access Efficiency:		99.5 %

   Potential Speedups
  ----------------------------------------------------
  Perfect Flow Complexity:		1.00
  Perfect OpenMP/MPI/Pthread/TBB:	1.70
  Perfect OpenMP/MPI/Pthread/TBB + Load Distribution:	2.63
  If No Scalar Integer:
      Potential Speedup:		1.00
      Nb Loops to get 80%:		2
  If FP Vectorized:
      Potential Speedup:		1.03
      Nb Loops to get 80%:		1
  If Fully Vectorized:
      Potential Speedup:		1.37
      Nb Loops to get 80%:		3
  If Only FP Arithmetic:
      Potential Speedup:		1.03
      Nb Loops to get 80%:		1




+--------------------------------------------------------------------------------------------------------------------+
+                                             1.3  -  Potential Speedups                                             +
+--------------------------------------------------------------------------------------------------------------------+

  If No Scalar Integer:
      Number of loops   | 1      | 7      | 14     | 20     | 28     | 
      Cumulated Speedup | 1.0018 | 1.0036 | 1.0036 | 1.0036 | 1.0036 | 
  Top 5 loops:
    exec - 18:	1.0018
    exec - 22:	1.0032
    exec - 25:	1.0036
    exec - 8:	1.0036
    exec - 2:	1.0036

  If FP Vectorized:
      Number of loops   | 1      | 7      | 14     | 20     | 28     | 
      Cumulated Speedup | 1.0227 | 1.0258 | 1.0258 | 1.0258 | 1.0258 | 
  Top 5 loops:
    exec - 19:	1.0227
    exec - 18:	1.0244
    exec - 22:	1.0257
    exec - 11:	1.0258
    exec - 2:	1.0258

  If Fully Vectorized:
      Number of loops   | 1      | 7      | 14     | 20     | 28     | 
      Cumulated Speedup | 1.1533 | 1.3641 | 1.3676 | 1.3692 | 1.3705 | 
  Top 5 loops:
    exec - 19:	1.1533
    exec - 23:	1.2891
    exec - 26:	1.3557
    exec - 18:	1.3594
    exec - 22:	1.3624

  If Only FP Arithmetic:
      Number of loops   | 1      | 7      | 14     | 20     | 28     | 
      Cumulated Speedup | 1.0261 | 1.0306 | 1.0313 | 1.0314 | 1.0314 | 
  Top 5 loops:
    exec - 26:	1.0261
    exec - 18:	1.028
    exec - 22:	1.0295
    exec - 25:	1.0299
    exec - 96:	1.0302



+====================================================================================================================+
+                                                   2  -  SUMMARY                                                    +
+====================================================================================================================+


+--------------------------------------------------------------------------------------------------------------------+
+                                             2.1  -  EXPERIMENT QUALITY                                             +
+--------------------------------------------------------------------------------------------------------------------+

  [4 / 4] Application profile is long enough (16.61 s)
To have good quality measurements, it is advised that the application profiling time is greater than 10 seconds.

  [3 / 3] Most of time spent in analyzed modules comes from functions with source/debug info
-g option gives access to debugging informations, such are source locations.

  [2.9987740244377 / 3] Most of time spent in analyzed modules (99.96%) comes from functions compiled with architecture specialization option
-march=znver5


  [3 / 3] Most of time spent in analyzed modules comes from functions with compilation options informations and
-fno-omit-frame-pointer is present
-fno-omit-frame-pointer improves the accuracy of callchains found during the application profiling.

  [3 / 3] Optimization level option is correctly used


  [3 / 3] Host configuration allows retrieval of all necessary metrics.


  [2 / 2] Application is correctly profiled ("Others" category represents 0.64 % of the execution time)
To have a representative profiling, it is advised that the category "Others" represents less than 20% of the execution
time in order to analyze as much as possible of the user code

  [1 / 1] Lstopo present. The Topology lstopo report will be generated.



+--------------------------------------------------------------------------------------------------------------------+
+                                                2.2  -  CODE QUALITY                                                +
+--------------------------------------------------------------------------------------------------------------------+

  [4 / 4] Enough time of the experiment time spent in analyzed loops (53.54%)
If the time spent in analyzed loops is less than 30%, standard loop optimizations will have a limited impact on
application performances.

  [2 / 4] A significant amount of threads are idle (48.75%)
On average, more than 10% of observed threads are idle. Such threads are probably IO/sync waiting. Some hints: use
faster filesystems to read/write data, improve parallel load balancing and/or scheduling.

  [4 / 4] CPU activity is good
CPU cores are active 97.69% of time

  [4 / 4] Loop profile is not flat
At least one loop coverage is greater than 4% (26.59%), representing an hotspot for the application

  [4 / 4] Enough time of the experiment time spent in analyzed innermost loops (53.03%)
If the time spent in analyzed innermost loops is less than 15%, standard innermost loop optimizations such as
vectorisation will have a limited impact on application performances.

  [4 / 4] Affinity is good (97.39%)
Threads are not migrating to CPU cores: probably successfully pinned

  [3 / 3] Less than 10% (0.00%) is spend in BLAS1 operations
It could be more efficient to inline by hand BLAS1 operations

  [0 / 3] Too many functions do not use all threads
Functions running on a reduced number of threads (typically sequential code) cover at least 10% of application
walltime (44.28%). Check both "Max Inclusive Time Over Threads" and "Nb Threads" in Functions or Loops tabs and
consider parallelizing sequential regions or improving parallelization of regions running on a reduced number of
threads

  [3 / 3] Cumulative Outermost/In between loops coverage (0.51%) lower than cumulative innermost loop coverage (53.03%)
Having cumulative Outermost/In between loops coverage greater than cumulative innermost loop coverage will make loop
optimization more complex

  [2 / 2] Less than 10% (0.00%) is spend in BLAS2 operations
BLAS2 calls usually could make a poor cache usage and could benefit from inlining.

  [2 / 2] Less than 10% (0.00%) is spend in Libm/SVML (special functions)



+--------------------------------------------------------------------------------------------------------------------+
+                                               2.3  -  LOOPS OVERVIEW                                               +
+--------------------------------------------------------------------------------------------------------------------+

  Top 5 loops:
   + exec - 19  :
     analysis: Execution Time: 26 % - Vectorization Ratio: 100.00 % - Vector Length Use: 50.00 %

   + exec - 23  :
     analysis: Execution Time: 18 % - Vectorization Ratio: 100.00 % - Vector Length Use: 50.00 %

   + exec - 26  :
     analysis: Execution Time: 7 % - Vectorization Ratio: 100.00 % - Vector Length Use: 50.00 %

   + exec - 18  :
     analysis: Execution Time: 0 % - Vectorization Ratio: 20.00 % - Vector Length Use: 15.50 %
     Loop Computation Issues: 6
        [4] [SA] Less than 10% of the FP ADD/SUB/MUL arithmetic operations are performed using FMA - Reorganize
            arithmetic expressions to exhibit potential for FMA. This issue costs 4 points.
        [2] [SA] Presence of a large number of scalar integer instructions - Simplify loop structure, perform loop
            splitting or perform unroll and jam. This issue costs 2 points.
     Control Flow Issues: 15
        [13] [SA] Too many paths (9 paths) - Simplify control structure. There are 9 issues ( = paths) costing 1 point
            each with a malus of 4 points.
        [2] [SA] Non innermost loop (Outermost) - Collapse loop with innermost ones. This issue costs 2 points.
     Data Access Issues: 4
        [2] [SA] Presence of special instructions executing on a single port (INSERT/EXTRACT, SHUFFLE/PERM) - Simplify
            data access and try to get stride 1 access. There are 2 issues (= instructions) costing 1 point each.
        [2] [SA] More than 20% of the loads are accessing the stack - Perform loop splitting to decrease pressure on
            registers. This issue costs 2 points.
     Vectorization Roadblocks: 15
        [13] [SA] Too many paths (9 paths) - Simplify control structure. There are 9 issues ( = paths) costing 1 point
            each with a malus of 4 points.
        [2] [SA] Non innermost loop (Outermost) - Collapse loop with innermost ones. This issue costs 2 points.
     Inefficient Vectorization: 2
        [2] [SA] Presence of special instructions executing on a single port (INSERT/EXTRACT, SHUFFLE/PERM) - Simplify
            data access and try to get stride 1 access. There are 2 issues (= instructions) costing 1 point each.

   + exec - 22  :
     analysis: Execution Time: 0 % - Vectorization Ratio: 28.13 % - Vector Length Use: 17.77 %
     Loop Computation Issues: 6
        [4] [SA] Less than 10% of the FP ADD/SUB/MUL arithmetic operations are performed using FMA - Reorganize
            arithmetic expressions to exhibit potential for FMA. This issue costs 4 points.
        [2] [SA] Presence of a large number of scalar integer instructions - Simplify loop structure, perform loop
            splitting or perform unroll and jam. This issue costs 2 points.
     Control Flow Issues: 16
        [14] [SA] Too many paths (10 paths) - Simplify control structure. There are 10 issues ( = paths) costing 1
            point each with a malus of 4 points.
        [2] [SA] Non innermost loop (Outermost) - Collapse loop with innermost ones. This issue costs 2 points.
     Data Access Issues: 5
        [3] [SA] Presence of special instructions executing on a single port (INSERT/EXTRACT, SHUFFLE/PERM, BROADCAST)
            - Simplify data access and try to get stride 1 access. There are 3 issues (= instructions) costing 1
            point each.
        [2] [SA] More than 20% of the loads are accessing the stack - Perform loop splitting to decrease pressure on
            registers. This issue costs 2 points.
     Vectorization Roadblocks: 16
        [14] [SA] Too many paths (10 paths) - Simplify control structure. There are 10 issues ( = paths) costing 1
            point each with a malus of 4 points.
        [2] [SA] Non innermost loop (Outermost) - Collapse loop with innermost ones. This issue costs 2 points.
     Inefficient Vectorization: 3
        [3] [SA] Presence of special instructions executing on a single port (INSERT/EXTRACT, SHUFFLE/PERM, BROADCAST)
            - Simplify data access and try to get stride 1 access. There are 3 issues (= instructions) costing 1
            point each.



+====================================================================================================================+
+                                                 3  -  APPLICATION                                                  +
+====================================================================================================================+


+--------------------------------------------------------------------------------------------------------------------+
+                                               3.1  -  Categorization                                               +
+--------------------------------------------------------------------------------------------------------------------+

   Category | IO     | Exe    | System  | Others  | Memory | String | MPI   | TBB   | OMP   | Pthread | Math  |
  ----------+--------+--------+---------+---------+--------+--------+-------+-------+-------+---------+-------+
   Time (%) | 0.00   | 54.55  | 0.41    | 0.64    | 0.00   | 0.08   | 1.65  | 0.00  | 42.65 | 0.02    | 0.00  |




+--------------------------------------------------------------------------------------------------------------------+
+                                          3.2  -  Function Based Profiling                                          +
+--------------------------------------------------------------------------------------------------------------------+

   Buckets                    | Nb Functions              | Coverage                  | Cumulated Coverage        |
  ----------------------------+---------------------------+---------------------------+---------------------------+
   > 8%                       | 4                         | 84.50                     | 84.50                     |
   4% to 8%                   | 1                         | 7.76                      | 92.27                     |
   2% to 4%                   | 1                         | 2.24                      | 94.51                     |
   1% to 2%                   | 0                         | 0.00                      | 94.51                     |
   0.5% to 1%                 | 1                         | 0.92                      | 95.43                     |
   0.25% to 0.5%              | 3                         | 0.88                      | 96.31                     |
   0.125% to 0.25%            | 9                         | 1.57                      | 97.88                     |
   < 0.125%                   | 170                       | 2.12                      | 100.00                    |




+--------------------------------------------------------------------------------------------------------------------+
+                                            3.3  -  Loop Based Profiling                                            +
+--------------------------------------------------------------------------------------------------------------------+

   Buckets                    | Nb Loops                  | Coverage                  | Cumulated Coverage        |
  ----------------------------+---------------------------+---------------------------+---------------------------+
   > 8%                       | 2                         | 44.85                     | 44.85                     |
   4% to 8%                   | 1                         | 7.62                      | 52.47                     |
   2% to 4%                   | 0                         | 0.00                      | 52.47                     |
   1% to 2%                   | 0                         | 0.00                      | 52.47                     |
   0.5% to 1%                 | 0                         | 0.00                      | 52.47                     |
   0.25% to 0.5%              | 0                         | 0.00                      | 52.47                     |
   0.125% to 0.25%            | 0                         | 0.00                      | 52.47                     |
   < 0.125%                   | 31                        | 0.56                      | 53.03                     |


+====================================================================================================================+
+                                                  4  -  FUNCTIONS                                                   +
+====================================================================================================================+


+--------------------------------------------------------------------------------------------------------------------+
+                                              4.1  -  Top 10 Functions                                              +
+--------------------------------------------------------------------------------------------------------------------+

   Function                                               | Module              | Coverage (%)   | Time (s)       |
  --------------------------------------------------------+---------------------+----------------+----------------+
   cg_calc_w(int, int, int, double*, double const*, do... | exec                | 26.89          | 3.04           |
   __kmp_hardware_timestamp                               | libomp.so           | 21.19          | 2.40           |
   cg_calc_ur(int, int, int, double, double*, double*,... | exec                | 18.53          | 2.10           |
   __kmp_hyper_barrier_release(barrier_type, kmp_info*... | libomp.so           | 17.90          | 2.03           |
   cg_calc_p(int, int, int, double, double*, double co... | exec                | 7.76           | 0.88           |
   __kmp_hyper_barrier_gather(barrier_type, kmp_info*,... | libomp.so           | 2.24           | 0.25           |
   mca_part_persist_progress                              | libmpi.so.40.40.7   | 0.92           | 2.49           |
   unknown_kernel_region                                  | kernel              | 0.38           | 0.04           |
   uct_mm_iface_progress                                  | libuct.so.0.0.0     | 0.25           | 0.69           |
   hmca_bcol_basesmuma_allreduce_intra_fanin_fanout_pr... | hmca_bcol_basesm... | 0.25           | 0.69           |


+====================================================================================================================+
+                                                    5  -  LOOPS                                                     +
+====================================================================================================================+


+--------------------------------------------------------------------------------------------------------------------+
+                                                5.1  -  Top 10 Loops                                                +
+--------------------------------------------------------------------------------------------------------------------+

   Loop Id        | Module              | Source Location                                        | Coverage (%)   |
  ----------------+---------------------+--------------------------------------------------------+----------------+
   19             | exec                | cg.cpp:88-90                                           | 26.59          |
   23             | exec                | cg.cpp:111-113                                         | 18.26          |
   26             | exec                | cg.cpp:131-131                                         | 7.62           |
   18             | exec                | cg.cpp:83-86                                           | 0.22           |
   22             | exec                | cg.cpp:107-108                                         | 0.18           |
   96             | exec                | pack_halos.cpp:71-71                                   | 0.06           |
   93             | exec                | pack_halos.cpp:53-53                                   | 0.06           |
   97             | exec                | pack_halos.cpp:86-88                                   | 0.05           |
   25             | exec                | cg.cpp:127-128,cg.cpp:131-131                          | 0.05           |
   15             | exec                | cg.cpp:64-68                                           | 0.05           |





+====================================================================================================================+
+                                                     6  -  CQA                                                      +
+====================================================================================================================+


+--------------------------------------------------------------------------------------------------------------------+
+                                                   6.1  -  Loops                                                    +
+--------------------------------------------------------------------------------------------------------------------+





      6.1.1  -  Loop 19 from exec
  ==========================================================================================================

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/178-663-0018/intel/TeaLeaf/build/TeaLeaf/src/omp/cg.cpp:88-90.

It is main loop of related source loop which is unrolled by 8 (including vectorization).

      6.1.1.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

41% of peak computational performance is used (20.00 out of 48.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.1.1.1  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is vectorized, but using only 256 out of 512 bits (AVX/AVX2 instructions on AVX-512 processors).
<<image_4x64_512>>

Details
All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).


Workaround
Read the "512-bits vectorization" report at "Potential" confidence level.


      6.1.1.1.2  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck).

By removing all these bottlenecks, you can lower the cost of an iteration from 6.00 to 5.50 cycles (1.09x speedup).


Workaround
Reduce the number of FP multiply/FMA instructions




      6.1.1.1.3  -  512-bits vectorization
  ----------------------------------------------------------------------------------------------------------

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.


Workaround
Recompile with -mprefer-vector-width=512


      6.1.1.1.4  -  FMA
  ----------------------------------------------------------------------------------------------------------

Detected 40 FMA (fused multiply-add) operations.
Presence of both ADD/SUB and MUL operations.

Workaround
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible.
For instance a + b*c is a valid FMA (MUL then ADD).
However (a+b)* c cannot be translated into an FMA (ADD then MUL).




      6.1.1.1.5  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

20 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).



      6.1.1.1.6  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 120 FP arithmetical operations:
 - 72: addition or subtraction (40 inside FMA instructions)
 - 48: multiply (40 inside FMA instructions)
The binary loop is loading 640 bytes (80 double precision FP elements).
The binary loop is storing 64 bytes (8 double precision FP elements).


      6.1.1.1.7  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.17 FP operations per loaded or stored byte.







      6.1.2  -  Loop 23 from exec
  ==========================================================================================================

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/178-663-0018/intel/TeaLeaf/build/TeaLeaf/src/omp/cg.cpp:111-113.

It is main loop of related source loop which is unrolled by 16 (including vectorization).

      6.1.2.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

33% of peak computational performance is used (16.00 out of 48.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.2.1.1  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is vectorized, but using only 256 out of 512 bits (AVX/AVX2 instructions on AVX-512 processors).
<<image_4x64_512>>

Details
All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).


Workaround
Read the "512-bits vectorization" report at "Potential" confidence level.


      6.1.2.1.2  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Performance is limited by:
 - execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck)
 - reading data from caches/RAM (load units are a bottleneck)
 - writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 6.00 to 4.00 cycles (1.50x speedup).


Workaround
 - Reduce the number of FP multiply/FMA instructions
 - Read less array elements
 - Write less array elements
 - Provide more information to your compiler:
  * hardcode the bounds of the corresponding 'for' loop





      6.1.2.1.3  -  512-bits vectorization
  ----------------------------------------------------------------------------------------------------------

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.


Workaround
Recompile with -mprefer-vector-width=512


      6.1.2.1.4  -  FMA
  ----------------------------------------------------------------------------------------------------------

Detected 48 FMA (fused multiply-add) operations.




      6.1.2.1.5  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

12 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).



      6.1.2.1.6  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 96 FP arithmetical operations:
 - 48: addition or subtraction (all inside FMA instructions)
 - 48: multiply (all inside FMA instructions)
The binary loop is loading 512 bytes (64 double precision FP elements).
The binary loop is storing 256 bytes (32 double precision FP elements).


      6.1.2.1.7  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.12 FP operations per loaded or stored byte.







      6.1.3  -  Loop 26 from exec
  ==========================================================================================================

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/178-663-0018/intel/TeaLeaf/build/TeaLeaf/src/omp/cg.cpp:131.

It is main loop of related source loop which is unrolled by 16 (including vectorization).

      6.1.3.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

22% of peak computational performance is used (10.67 out of 48.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.3.1.1  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is vectorized, but using only 256 out of 512 bits (AVX/AVX2 instructions on AVX-512 processors).
<<image_4x64_512>>

Details
All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).


Workaround
Read the "512-bits vectorization" report at "Potential" confidence level.


      6.1.3.1.2  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Performance is limited by:
 - reading data from caches/RAM (load units are a bottleneck)
 - writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 3.00 to 2.00 cycles (1.50x speedup).


Workaround
 - Read less array elements
 - Write less array elements
 - Provide more information to your compiler:
  * hardcode the bounds of the corresponding 'for' loop





      6.1.3.1.3  -  512-bits vectorization
  ----------------------------------------------------------------------------------------------------------

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.


Workaround
Recompile with -mprefer-vector-width=512


      6.1.3.1.4  -  FMA
  ----------------------------------------------------------------------------------------------------------

Detected 16 FMA (fused multiply-add) operations.




      6.1.3.1.5  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

4 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).



      6.1.3.1.6  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 32 FP arithmetical operations:
 - 16: addition or subtraction (all inside FMA instructions)
 - 16: multiply (all inside FMA instructions)
The binary loop is loading 256 bytes (32 double precision FP elements).
The binary loop is storing 128 bytes (16 double precision FP elements).


      6.1.3.1.7  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.







      6.1.4  -  Loop 18 from exec
  ==========================================================================================================

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/178-663-0018/intel/TeaLeaf/build/TeaLeaf/src/omp/cg.cpp:83-90.

Analyzed code is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/178-663-0018/intel/TeaLeaf/build/TeaLeaf/src/omp/cg.cpp:83-86.

Warnings:
 - Non-innermost loop: analyzing only self part (ignoring child loops).
 - Ignoring paths for analysis
 - Too many paths. Rerun with max-paths=9
 - RecMII not computed since number of paths is unknown or > max_paths
 - Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 9 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):
 - hoisting them (moving them outside the loop)
 - turning them into conditional moves, MIN or MAX


Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)


      6.1.4.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

0% of peak computational performance is used (0.40 out of 48.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.4.1.1  -  Code clean check
  ----------------------------------------------------------------------------------------------------------

Detected a slowdown caused by scalar integer instructions (typically used for address computation).
By removing them, you can lower the cost of an iteration from 17.38 to 3.00 cycles (5.79x speedup).

Workaround
 - Try to reorganize arrays of structures to structures of arrays
 - Consider to permute loops (see vectorization gain report)



      6.1.4.1.2  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is poorly vectorized.
Only 15% of vector register length is used (average across all SSE/AVX instructions).


Details
20% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):
 - 0% of SSE/AVX loads are used in vector version.
 - 0% of SSE/AVX stores are used in vector version.
 - 50% of SSE/AVX addition or subtraction instructions are used in vector version.
 - 16% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.


Workaround
Read the "512-bits vectorization" report at "Potential" confidence level.


      6.1.4.1.3  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Found no such bottlenecks but see expert reports for more complex bottlenecks.




      6.1.4.1.4  -  512-bits vectorization
  ----------------------------------------------------------------------------------------------------------

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.


Workaround
Recompile with -mprefer-vector-width=512




      6.1.4.1.5  -  Vector unaligned load/store instructions
  ----------------------------------------------------------------------------------------------------------

Detected 1 suboptimal vector unaligned load/store instructions.


Details
 - VEXTRACTF128: 1 occurrences<<list_path_1_vec_align_1>>


Workaround
 - Pass to your compiler a micro-architecture specialization option:
  * use march=native
 - Use vector aligned instructions:
  1) align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
  2) inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.
<<image_vec_align>>


      6.1.4.1.6  -  Conversion instructions
  ----------------------------------------------------------------------------------------------------------

Detected expensive conversion instructions.

Details
 - MOVZX: 3 occurrences<<list_path_1_cvt_1>>


Workaround
Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.


      6.1.4.1.7  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).
1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).
1 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).



      6.1.4.1.8  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 7 FP arithmetical operations:
 - 7: addition or subtraction
The binary loop is loading 326 bytes (40 double precision FP elements).
The binary loop is storing 33 bytes (4 double precision FP elements).


      6.1.4.1.9  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.02 FP operations per loaded or stored byte.







      6.1.5  -  Loop 22 from exec
  ==========================================================================================================

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/178-663-0018/intel/TeaLeaf/build/TeaLeaf/src/omp/cg.cpp:107-113.

Analyzed code is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/178-663-0018/intel/TeaLeaf/build/TeaLeaf/src/omp/cg.cpp:107-108.

Warnings:
 - Non-innermost loop: analyzing only self part (ignoring child loops).
 - Ignoring paths for analysis
 - Too many paths. Rerun with max-paths=10
 - RecMII not computed since number of paths is unknown or > max_paths
 - Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 10 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):
 - hoisting them (moving them outside the loop)
 - turning them into conditional moves, MIN or MAX


Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)


      6.1.5.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

2% of peak computational performance is used (0.99 out of 48.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.5.1.1  -  Code clean check
  ----------------------------------------------------------------------------------------------------------

Detected a slowdown caused by scalar integer instructions (typically used for address computation).
By removing them, you can lower the cost of an iteration from 15.13 to 3.33 cycles (4.54x speedup).

Workaround
 - Try to reorganize arrays of structures to structures of arrays
 - Consider to permute loops (see vectorization gain report)



      6.1.5.1.2  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is poorly vectorized.
Only 17% of vector register length is used (average across all SSE/AVX instructions).


Details
28% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):
 - 0% of SSE/AVX loads are used in vector version.
 - 0% of SSE/AVX stores are used in vector version.
 - 57% of SSE/AVX addition or subtraction instructions are used in vector version.
 - 21% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.


Workaround
Read the "512-bits vectorization" report at "Potential" confidence level.


      6.1.5.1.3  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Found no such bottlenecks but see expert reports for more complex bottlenecks.




      6.1.5.1.4  -  512-bits vectorization
  ----------------------------------------------------------------------------------------------------------

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.


Workaround
Recompile with -mprefer-vector-width=512




      6.1.5.1.5  -  Vector unaligned load/store instructions
  ----------------------------------------------------------------------------------------------------------

Detected 1 suboptimal vector unaligned load/store instructions.


Details
 - VEXTRACTF128: 1 occurrences<<list_path_1_vec_align_1>>


Workaround
 - Pass to your compiler a micro-architecture specialization option:
  * use march=native
 - Use vector aligned instructions:
  1) align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
  2) inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.
<<image_vec_align>>


      6.1.5.1.6  -  Conversion instructions
  ----------------------------------------------------------------------------------------------------------

Detected expensive conversion instructions.

Details
 - MOVZX: 3 occurrences<<list_path_1_cvt_1>>


Workaround
Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.


      6.1.5.1.7  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).
1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).
3 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).



      6.1.5.1.8  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 15 FP arithmetical operations:
 - 15: addition or subtraction
The binary loop is loading 251 bytes (31 double precision FP elements).
The binary loop is storing 27 bytes (3 double precision FP elements).


      6.1.5.1.9  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.05 FP operations per loaded or stored byte.







      6.1.6  -  Loop 96 from exec
  ==========================================================================================================

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/178-663-0018/intel/TeaLeaf/build/TeaLeaf/src/omp/pack_halos.cpp:71.

It is main loop of related source loop which is unrolled by 16 (including vectorization).

      6.1.6.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

0% of peak computational performance is used (0.00 out of 96.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.6.1.1  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is vectorized, but using only 256 out of 512 bits (AVX/AVX2 instructions on AVX-512 processors).


Details
All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).


Workaround
Read the "512-bits vectorization" report at "Potential" confidence level.


      6.1.6.1.2  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Performance is limited by:
 - reading data from caches/RAM (load units are a bottleneck)
 - writing data to caches/RAM (the store unit is a bottleneck)


Workaround
 - Read less array elements
 - Write less array elements
 - Provide more information to your compiler:
  * hardcode the bounds of the corresponding 'for' loop





      6.1.6.1.3  -  512-bits vectorization
  ----------------------------------------------------------------------------------------------------------

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.


Workaround
Recompile with -mprefer-vector-width=512




      6.1.6.1.4  -  Slow data structures access
  ----------------------------------------------------------------------------------------------------------

Detected data structures (typically arrays) that cannot be efficiently read/written

Details
 - Irregular (variable stride) or indirect: 1 occurrence(s)
Non-unit stride (uncontiguous) accesses are not efficiently using data caches


Workaround
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.


      6.1.6.1.5  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.


      6.1.6.1.6  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop does not contain any FP arithmetical operations.
The binary loop is loading 128 bytes.
The binary loop is storing 128 bytes.







      6.1.7  -  Loop 93 from exec
  ==========================================================================================================

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/178-663-0018/intel/TeaLeaf/build/TeaLeaf/src/omp/pack_halos.cpp:53.

It is main loop of related source loop which is unrolled by 16 (including vectorization).

      6.1.7.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

0% of peak computational performance is used (0.00 out of 96.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.7.1.1  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is vectorized, but using only 256 out of 512 bits (AVX/AVX2 instructions on AVX-512 processors).


Details
All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).


Workaround
Read the "512-bits vectorization" report at "Potential" confidence level.


      6.1.7.1.2  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Performance is limited by:
 - reading data from caches/RAM (load units are a bottleneck)
 - writing data to caches/RAM (the store unit is a bottleneck)


Workaround
 - Read less array elements
 - Write less array elements
 - Provide more information to your compiler:
  * hardcode the bounds of the corresponding 'for' loop





      6.1.7.1.3  -  512-bits vectorization
  ----------------------------------------------------------------------------------------------------------

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.


Workaround
Recompile with -mprefer-vector-width=512




      6.1.7.1.4  -  Slow data structures access
  ----------------------------------------------------------------------------------------------------------

Detected data structures (typically arrays) that cannot be efficiently read/written

Details
 - Irregular (variable stride) or indirect: 1 occurrence(s)
Non-unit stride (uncontiguous) accesses are not efficiently using data caches


Workaround
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.


      6.1.7.1.5  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.


      6.1.7.1.6  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop does not contain any FP arithmetical operations.
The binary loop is loading 128 bytes.
The binary loop is storing 128 bytes.







      6.1.8  -  Loop 97 from exec
  ==========================================================================================================

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/178-663-0018/intel/TeaLeaf/build/TeaLeaf/src/omp/pack_halos.cpp:86-88.

It is peel/tail loop of related source loop which is unrolled by 16 (including vectorization).

      6.1.8.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

0% of peak computational performance is used (0.00 out of 96.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.8.1.1  -  Unrolling/vectorization cost
  ----------------------------------------------------------------------------------------------------------

This loop is peel/tail of a unrolled/vectorized loop. If its cost is not negligible compared to the main (unrolled/vectorized) loop, unrolling/vectorization is counterproductive due to low trip count.

Details
The more iterations the main loop is processing, the higher the trip count must be to amortize peel/tail overhead.

Workaround
 - recompile with -fprofile-instr-generate, execute ,merge raw profiles with 'llvm-profdata merge -o default.profdata default.profraw' and recompile with -fprofile-instr-use (profile-guided optimization)
 - hardcode most frequent values of loop bounds by adding specialized paths.:
  *  For instance, replace for (i=0; i<n; i++) foo(i) with:
switch (n) {
  case (4): for (i=0; i<4; i++) foo(i); break;
  case (6): for (i=0; i<6; i++) foo(i); break;
  default : for (i=0; i<n; i++) foo(i); break;
}



      6.1.8.1.2  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is not vectorized.
8 data elements could be processed at once in vector registers.


Details
All SSE/AVX instructions are used in scalar version (process only one data element in vector registers).



      6.1.8.1.3  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Found no such bottlenecks but see expert reports for more complex bottlenecks.



No data for this section



      6.1.8.1.4  -  Slow data structures access
  ----------------------------------------------------------------------------------------------------------

Detected data structures (typically arrays) that cannot be efficiently read/written

Details
 - Irregular (variable stride) or indirect: 1 occurrence(s)
Non-unit stride (uncontiguous) accesses are not efficiently using data caches


Workaround
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.


      6.1.8.1.5  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.


      6.1.8.1.6  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop does not contain any FP arithmetical operations.
The binary loop is loading 8 bytes.
The binary loop is storing 8 bytes.







      6.1.9  -  Loop 25 from exec
  ==========================================================================================================

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/178-663-0018/intel/TeaLeaf/build/TeaLeaf/src/omp/cg.cpp:127-131.

Analyzed code is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/178-663-0018/intel/TeaLeaf/build/TeaLeaf/src/omp/cg.cpp:127-128,131.

Warnings:
 - Non-innermost loop: analyzing only self part (ignoring child loops).
 - Ignoring paths for analysis
 - Too many paths. Rerun with max-paths=5
 - RecMII not computed since number of paths is unknown or > max_paths
 - Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 5 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):
 - hoisting them (moving them outside the loop)
 - turning them into conditional moves, MIN or MAX


Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)


      6.1.9.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

0% of peak computational performance is used (0.00 out of 96.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.9.1.1  -  Code clean check
  ----------------------------------------------------------------------------------------------------------

Detected a slowdown caused by scalar integer instructions (typically used for address computation).
By removing them, you can lower the cost of an iteration from 7.13 to 1.67 cycles (4.28x speedup).

Workaround
 - Try to reorganize arrays of structures to structures of arrays
 - Consider to permute loops (see vectorization gain report)



      6.1.9.1.2  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is not vectorized.
Only 10% of vector register length is used (average across all SSE/AVX instructions).


Details
All SSE/AVX instructions are used in scalar version (process only one data element in vector registers).


Workaround
Read the "512-bits vectorization" report at "Potential" confidence level.


      6.1.9.1.3  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Found no such bottlenecks but see expert reports for more complex bottlenecks.




      6.1.9.1.4  -  512-bits vectorization
  ----------------------------------------------------------------------------------------------------------

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.


Workaround
Recompile with -mprefer-vector-width=512




      6.1.9.1.5  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.


      6.1.9.1.6  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop does not contain any FP arithmetical operations.
The binary loop is loading 121 bytes.
The binary loop is storing 9 bytes.







      6.1.10  -  Loop 15 from exec
  ==========================================================================================================

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/178-663-0018/intel/TeaLeaf/build/TeaLeaf/src/omp/cg.cpp:64-68.

It is main loop of related source loop which is unrolled by 8 (including vectorization).

      6.1.10.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

39% of peak computational performance is used (18.96 out of 48.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.10.1.1  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is vectorized, but using only 256 out of 512 bits (AVX/AVX2 instructions on AVX-512 processors).
<<image_4x64_512>>

Details
All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).


Workaround
Read the "512-bits vectorization" report at "Potential" confidence level.


      6.1.10.1.2  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Performance is limited by:
 - reading data from caches/RAM (load units are a bottleneck)
 - writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 6.75 to 6.00 cycles (1.13x speedup).


Workaround
 - Read less array elements
 - Write less array elements
 - Provide more information to your compiler:
  * hardcode the bounds of the corresponding 'for' loop





      6.1.10.1.3  -  512-bits vectorization
  ----------------------------------------------------------------------------------------------------------

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.


Workaround
Recompile with -mprefer-vector-width=512


      6.1.10.1.4  -  FMA
  ----------------------------------------------------------------------------------------------------------

Detected 40 FMA (fused multiply-add) operations.
Presence of both ADD/SUB and MUL operations.

Workaround
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible.
For instance a + b*c is a valid FMA (MUL then ADD).
However (a+b)* c cannot be translated into an FMA (ADD then MUL).




      6.1.10.1.5  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

22 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).



      6.1.10.1.6  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 128 FP arithmetical operations:
 - 80: addition or subtraction (40 inside FMA instructions)
 - 48: multiply (40 inside FMA instructions)
The binary loop is loading 672 bytes (84 double precision FP elements).
The binary loop is storing 192 bytes (24 double precision FP elements).


      6.1.10.1.7  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.15 FP operations per loaded or stored byte.





[MAQAO] Info: STOP THE REPORT GENERATION
[MAQAO] Info: 
[MAQAO] Info: If your application produces files, they can be found in directory "/beegfs/hackathon/users/eoseret/qaas_runs_test/178-663-0018/intel/TeaLeaf/run/oneview_runs/compilers/aocc_3/oneview_run_1786631552"
[MAQAO] Info: 
