OV - exec - Loop 28

0x403628 ADD	W0, W9, #1

0x40362c ADD	W11, W11, #1

0x403630 ADD	W7, W30, W10

0x403634 CMP	W9, W8

0x403638 ORR	W9, WZR, W0

0x40363c B.EQ	403814

0x403640 SBFM	X30, X7, #0, #31

0x403644 CMP	X5, #10

0x403648 B.CS	4036a4

0x40364c ORR	X26, XZR, X23

0x403650 ADD	X0, X26, X30

0x403654 ADD	X26, X28, X26

0x403658 ADD	X7, X12, X0,LSL #3

0x40365c ADD	X21, X13, X0,LSL #3

0x403660 ADD	X24, X14, X0,LSL #3

0x403664 ADD	X25, X15, X0,LSL #3

  (27) 0x403668 LDR	D1, [X20]

  (27) 0x40366c LDR	D2, [X7], #8

  (27) 0x403670 LDR	D3, [X21]

  (27) 0x403674 ADDS	X26, X26, #1

  (27) 0x403678 FMADD	D1, D2, D1, D3

  (27) 0x40367c STR	D1, [X21], #8

  (27) 0x403680 LDR	D1, [X20]

  (27) 0x403684 LDR	D2, [X24], #8

  (27) 0x403688 LDR	D3, [X25]

  (27) 0x40368c FMSUB	D1, D2, D1, D3

  (27) 0x403690 FMADD	D0, D1, D1, D0

  (27) 0x403694 STR	D1, [X25], #8

  (27) 0x403698 STUR	D0, [X29, #488]

  (27) 0x40369c B.CC	403668

0x4036a0 B	403628

0x4036a4 ADD	W7, W16, W11

0x4036a8 LDR	X0, [SP, #56]

0x4036ac MADD	W7, W10, W7, WZR

0x4036b0 SBFM	X7, X7, #0, #31

0x4036b4 ADD	X21, X10, X7

0x4036b8 ADD	X7, X23, X7

0x4036bc ADD	X26, X0, X21,LSL #3

0x4036c0 LDP	X0, X3, [X29, #976]

0x4036c4 ADD	X25, X14, X7,LSL #3

0x4036c8 ADD	X19, X12, X7,LSL #3

0x4036cc ADD	X1, X15, X7,LSL #3

0x4036d0 ADD	X7, X13, X7,LSL #3

0x4036d4 ADD	X24, X4, X21,LSL #3

0x4036d8 ADD	X0, X0, X21,LSL #3

0x4036dc ADD	X21, X3, X21,LSL #3

0x4036e0 CMP	X7, X0

0x4036e4 CCMP	X1, X21, #2, #3

0x4036e8 CSINC	W3, WZR, WZR, #2

0x4036ec CMP	X7, X18

0x4036f0 CCMP	X17, X21, #2, #3

0x4036f4 CSINC	W3, W3, WZR, #2

0x4036f8 CMP	X7, X2

0x4036fc CCMP	X21, X20, #0, #3

0x403700 CSINC	W3, W3, WZR, #9

0x403704 CMP	X7, X26

0x403708 CCMP	X19, X21, #2, #3

0x40370c CSINC	W3, W3, WZR, #2

0x403710 CMP	X7, X24

0x403714 CCMP	X25, X21, #2, #3

0x403718 CSINC	W3, W3, WZR, #2

0x40371c CMP	X1, X18

0x403720 CCMP	X17, X0, #2, #3

0x403724 CSINC	W3, W3, WZR, #2

0x403728 CMP	X1, X2

0x40372c CCMP	X0, X20, #0, #3

0x403730 CSINC	W3, W3, WZR, #9

0x403734 CMP	X1, X26

0x403738 CCMP	X19, X0, #2, #3

0x40373c CSINC	W7, WZR, WZR, #2

0x403740 CMP	X1, X24

0x403744 CCMP	X25, X0, #2, #3

0x403748 CSINC	W0, WZR, WZR, #2

0x40374c CMP	X17, X26

0x403750 CCMP	X19, X18, #2, #3

0x403754 ORR	W0, W7, W0

0x403758 CSINC	W7, WZR, WZR, #2

0x40375c CMP	X17, X24

0x403760 ORR	W0, W0, W6

0x403764 CCMP	X25, X18, #2, #3

0x403768 ORR	W0, W3, W0

0x40376c CSINC	W21, WZR, WZR, #2

0x403770 TBNZ	W0, #0, 40364c

0x403774 TBNZ	W7, #0, 40364c

0x403778 TBNZ	W21, #0, 40364c

0x40377c LDP	X1, X3, [SP, #32]

0x403780 ADD	X0, X23, X30

0x403784 MOVI	V2.2D, #0

0x403788 MOV	V2.D[0], V0.D[0]

0x40378c MOVI	V1.2D, #0

0x403790 ORR	X7, XZR, X27

0x403794 ADD	X24, X3, X0,LSL #3

0x403798 ADD	X21, X1, X0,LSL #3

0x40379c LDP	X1, X3, [SP, #16]

0x4037a0 ADD	X25, X3, X0,LSL #3

0x4037a4 ADD	X26, X1, X0,LSL #3

  (29) 0x4037a8 LDR	D0, [X20]

  (29) 0x4037ac LDP	Q3, Q4, [X24, #2032]

  (29) 0x4037b0 SUBS	X7, X7, #4

  (29) 0x4037b4 ADD	X24, X24, #32

  (29) 0x4037b8 LDP	Q5, Q6, [X25, #2032]

  (29) 0x4037bc FMLA	V5.2D, V3.2D, V0.D[0]

  (29) 0x4037c0 FMLA	V6.2D, V4.2D, V0.D[0]

  (29) 0x4037c4 LDP	Q3, Q4, [X26, #2032]

  (29) 0x4037c8 ADD	X26, X26, #32

  (29) 0x4037cc STP	Q5, Q6, [X25, #2032]

  (29) 0x4037d0 LDP	Q5, Q6, [X21, #2032]

  (29) 0x4037d4 ADD	X25, X25, #32

  (29) 0x4037d8 LDR	D0, [X20]

  (29) 0x4037dc FMLS	V5.2D, V3.2D, V0.D[0]

  (29) 0x4037e0 FMLS	V6.2D, V4.2D, V0.D[0]

  (29) 0x4037e4 FMLA	V2.2D, V5.2D, V5.2D

  (29) 0x4037e8 FMLA	V1.2D, V6.2D, V6.2D

  (29) 0x4037ec STP	Q5, Q6, [X21, #2032]

  (29) 0x4037f0 ADD	X21, X21, #32

  (29) 0x4037f4 B.NE	4037a8

0x4037f8 FADD	V0.2D, V1.2D, V2.2D

0x4037fc LDR	X26, [SP, #48]

0x403800 FADDP	D0, V0.2D

0x403804 STUR	D0, [X29, #488]

0x403808 CMP	X5, X27

0x40380c B.EQ	403628

0x403810 B	403650

/home/hbollore/qaas/qaas-runs/174-118-5752/intel/TeaLeaf/build/TeaLeaf/src/omp/cg.cpp: 107 - 113

--------------------------------------------------------------------------------

107:   for (int jj = halo_depth; jj < y - halo_depth; ++jj) {

108:     for (int kk = halo_depth; kk < x - halo_depth; ++kk) {

109:       const int index = kk + jj * x;

110:

111:       u[index] += alpha * p[index];

112:       r[index] -= alpha * w[index];

113:       rrn_temp += r[index] * r[index];

Coverage (%)	Name	Source Location	Module
►100.00+	__kmp_invoke_microtask		libomp.so
○	__kmp_fork_call		libomp.so

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	7.78
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.91
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.05
Bottlenecks	P2, P3, P4, P5, P6, P7,
Function	cg_calc_ur(int, int, int, double, double, double, double const, double, double const*) [clone .omp_outlined]
Source	cg.cpp:107-108
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	11.67
CQA cycles if no scalar integer	1.50
CQA cycles if FP arith vectorized	11.67
CQA cycles if fully vectorized	6.09
Front-end cycles	11.13
P0 cycles	4.00
P1 cycles	4.00
P2 cycles	11.67
P3 cycles	11.67
P4 cycles	11.67
P5 cycles	11.67
P6 cycles	11.67
P7 cycles	11.67
P8 cycles	1.50
P9 cycles	1.50
P10 cycles	1.50
P11 cycles	1.50
P12 cycles	2.17
P13 cycles	1.83
P14 cycles	2.00
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	89.00
Nb uops	89.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	0.26
Nb FLOP add-sub	3.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	6.17
Bytes prefetched	0.00
Bytes loaded	64.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	1.25
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	3.70
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	47.81
Vector-efficiency ratio load	80.00
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	25.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	43.48

Metric	Value
CQA speedup if no scalar integer	7.78
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.91
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.05
Bottlenecks	P2, P3, P4, P5, P6, P7,
Function	cg_calc_ur(int, int, int, double, double, double, double const, double, double const*) [clone .omp_outlined]
Source	cg.cpp:107-108
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	11.67
CQA cycles if no scalar integer	1.50
CQA cycles if FP arith vectorized	11.67
CQA cycles if fully vectorized	6.09
Front-end cycles	11.13
P0 cycles	4.00
P1 cycles	4.00
P2 cycles	11.67
P3 cycles	11.67
P4 cycles	11.67
P5 cycles	11.67
P6 cycles	11.67
P7 cycles	11.67
P8 cycles	1.50
P9 cycles	1.50
P10 cycles	1.50
P11 cycles	1.50
P12 cycles	2.17
P13 cycles	1.83
P14 cycles	2.00
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	89.00
Nb uops	89.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	0.26
Nb FLOP add-sub	3.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	6.17
Bytes prefetched	0.00
Bytes loaded	64.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	1.25
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	3.70
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	47.81
Vector-efficiency ratio load	80.00
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	25.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	43.48

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	cg_calc_ur(int, int, int, double, double, double, double const, double, double const*) [clone .omp_outlined]
Source file and lines	cg.cpp:107-113
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/174-118-5752/intel/TeaLeaf/build/TeaLeaf/src/omp/cg.cpp:107-113.

Analyzed code is defined in /home/hbollore/qaas/qaas-runs/174-118-5752/intel/TeaLeaf/build/TeaLeaf/src/omp/cg.cpp:107-108.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=6
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 6 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 11.67 to 1.50 cycles (7.78x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 47% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 11.67 to 6.09 cycles (1.91x speedup).

Details

1% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU loads are used in vector version.
0% of VPU stores are used in vector version.
3% of VPU addition or subtraction instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 3 FP arithmetical operations:

3: addition or subtraction

The binary loop is loading 64 bytes. The binary loop is storing 8 bytes.

Arithmetic intensity

Arithmetic intensity is 0.04 FP operations per loaded or stored byte.

General properties

nb instructions	89
loop length	356
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

11.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	4.00	4.00	11.67	11.67	11.67	11.67	11.67	11.67	1.50	1.50	1.50	1.50	2.17	1.83	2.00	0.00	0.00
cycles	4.00	4.00	11.67	11.67	11.67	11.67	11.67	11.67	1.50	1.50	1.50	1.50	2.17	1.83	2.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	11.13
Overall L1	11.67

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
other	0%

FP

all	50%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	1%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	3%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 11.67 cycles. At this rate:

5% of peak load performance is reached (5.49 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (0.69 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 403640

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
ADD W0, W9, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W11, W11, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W7, W30, W10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W9, W8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
ORR W9, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
B.EQ 403814 <_Z10cg_calc_uriiidPdS_PKdS_S1_.omp_outlined+0x324>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X30, X7, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
CMP X5, #10	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.CS 4036a4 <_Z10cg_calc_uriiidPdS_PKdS_S1_.omp_outlined+0x1b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X26, XZR, X23	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X0, X26, X30	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X26, X28, X26	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X7, X12, X0,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X21, X13, X0,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X24, X14, X0,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X25, X15, X0,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
B 403628 <_Z10cg_calc_uriiidPdS_PKdS_S1_.omp_outlined+0x138>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W7, W16, W11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
LDR X0, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (50.0%)
MADD W7, W10, W7, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
SBFM X7, X7, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
ADD X21, X10, X7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X7, X23, X7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X26, X0, X21,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDP X0, X3, [X29, #976]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (100.0%)
ADD X25, X14, X7,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X19, X12, X7,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X1, X15, X7,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X7, X13, X7,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X24, X4, X21,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X0, X0, X21,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X21, X3, X21,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CMP X7, X0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
CCMP X1, X21, #2, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	1	scal (50.0%)
CSINC W3, WZR, WZR, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP X7, X18	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
CCMP X17, X21, #2, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	1	scal (50.0%)
CSINC W3, W3, WZR, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP X7, X2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
CCMP X21, X20, #0, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	1	scal (50.0%)
CSINC W3, W3, WZR, #9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP X7, X26	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
CCMP X19, X21, #2, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	1	scal (50.0%)
CSINC W3, W3, WZR, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP X7, X24	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
CCMP X25, X21, #2, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	1	scal (50.0%)
CSINC W3, W3, WZR, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP X1, X18	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
CCMP X17, X0, #2, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	1	scal (50.0%)
CSINC W3, W3, WZR, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP X1, X2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
CCMP X0, X20, #0, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	1	scal (50.0%)
CSINC W3, W3, WZR, #9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP X1, X26	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
CCMP X19, X0, #2, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	1	scal (50.0%)
CSINC W7, WZR, WZR, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP X1, X24	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
CCMP X25, X0, #2, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	1	scal (50.0%)
CSINC W0, WZR, WZR, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP X17, X26	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
CCMP X19, X18, #2, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	1	scal (50.0%)
ORR W0, W7, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CSINC W7, WZR, WZR, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP X17, X24	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
ORR W0, W0, W6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CCMP X25, X18, #2, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	1	scal (50.0%)
ORR W0, W3, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CSINC W21, WZR, WZR, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
TBNZ W0, #0, 40364c <_Z10cg_calc_uriiidPdS_PKdS_S1_.omp_outlined+0x15c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
TBNZ W7, #0, 40364c <_Z10cg_calc_uriiidPdS_PKdS_S1_.omp_outlined+0x15c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
TBNZ W21, #0, 40364c <_Z10cg_calc_uriiidPdS_PKdS_S1_.omp_outlined+0x15c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X1, X3, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (100.0%)
ADD X0, X23, X30	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVI V2.2D, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
MOV V2.D[0], V0.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
MOVI V1.2D, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
ORR X7, XZR, X27	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X24, X3, X0,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X21, X1, X0,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDP X1, X3, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (100.0%)
ADD X25, X3, X0,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X26, X1, X0,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
FADD V0.2D, V1.2D, V2.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
LDR X26, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (50.0%)
FADDP D0, V0.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
STUR D0, [X29, #488]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
CMP X5, X27	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 403628 <_Z10cg_calc_uriiidPdS_PKdS_S1_.omp_outlined+0x138>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 403650 <_Z10cg_calc_uriiidPdS_PKdS_S1_.omp_outlined+0x160>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	cg_calc_ur(int, int, int, double, double, double, double const, double, double const*) [clone .omp_outlined]
Source file and lines	cg.cpp:107-113
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/174-118-5752/intel/TeaLeaf/build/TeaLeaf/src/omp/cg.cpp:107-113.

Analyzed code is defined in /home/hbollore/qaas/qaas-runs/174-118-5752/intel/TeaLeaf/build/TeaLeaf/src/omp/cg.cpp:107-108.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=6
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 6 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 11.67 to 1.50 cycles (7.78x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 47% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 11.67 to 6.09 cycles (1.91x speedup).

Details

1% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU loads are used in vector version.
0% of VPU stores are used in vector version.
3% of VPU addition or subtraction instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 3 FP arithmetical operations:

3: addition or subtraction

The binary loop is loading 64 bytes. The binary loop is storing 8 bytes.

Arithmetic intensity

Arithmetic intensity is 0.04 FP operations per loaded or stored byte.

General properties

nb instructions	89
loop length	356
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

11.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	4.00	4.00	11.67	11.67	11.67	11.67	11.67	11.67	1.50	1.50	1.50	1.50	2.17	1.83	2.00	0.00	0.00
cycles	4.00	4.00	11.67	11.67	11.67	11.67	11.67	11.67	1.50	1.50	1.50	1.50	2.17	1.83	2.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	11.13
Overall L1	11.67

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
other	0%

FP

all	50%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	1%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	3%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 11.67 cycles. At this rate:

5% of peak load performance is reached (5.49 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (0.69 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 403640

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
ADD W0, W9, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W11, W11, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W7, W30, W10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W9, W8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
ORR W9, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
B.EQ 403814 <_Z10cg_calc_uriiidPdS_PKdS_S1_.omp_outlined+0x324>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X30, X7, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
CMP X5, #10	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.CS 4036a4 <_Z10cg_calc_uriiidPdS_PKdS_S1_.omp_outlined+0x1b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X26, XZR, X23	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X0, X26, X30	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X26, X28, X26	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X7, X12, X0,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X21, X13, X0,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X24, X14, X0,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X25, X15, X0,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
B 403628 <_Z10cg_calc_uriiidPdS_PKdS_S1_.omp_outlined+0x138>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W7, W16, W11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
LDR X0, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (50.0%)
MADD W7, W10, W7, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
SBFM X7, X7, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
ADD X21, X10, X7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X7, X23, X7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X26, X0, X21,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDP X0, X3, [X29, #976]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (100.0%)
ADD X25, X14, X7,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X19, X12, X7,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X1, X15, X7,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X7, X13, X7,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X24, X4, X21,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X0, X0, X21,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X21, X3, X21,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CMP X7, X0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
CCMP X1, X21, #2, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	1	scal (50.0%)
CSINC W3, WZR, WZR, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP X7, X18	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
CCMP X17, X21, #2, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	1	scal (50.0%)
CSINC W3, W3, WZR, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP X7, X2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
CCMP X21, X20, #0, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	1	scal (50.0%)
CSINC W3, W3, WZR, #9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP X7, X26	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
CCMP X19, X21, #2, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	1	scal (50.0%)
CSINC W3, W3, WZR, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP X7, X24	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
CCMP X25, X21, #2, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	1	scal (50.0%)
CSINC W3, W3, WZR, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP X1, X18	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
CCMP X17, X0, #2, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	1	scal (50.0%)
CSINC W3, W3, WZR, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP X1, X2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
CCMP X0, X20, #0, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	1	scal (50.0%)
CSINC W3, W3, WZR, #9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP X1, X26	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
CCMP X19, X0, #2, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	1	scal (50.0%)
CSINC W7, WZR, WZR, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP X1, X24	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
CCMP X25, X0, #2, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	1	scal (50.0%)
CSINC W0, WZR, WZR, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP X17, X26	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
CCMP X19, X18, #2, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	1	scal (50.0%)
ORR W0, W7, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CSINC W7, WZR, WZR, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP X17, X24	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
ORR W0, W0, W6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CCMP X25, X18, #2, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	1	scal (50.0%)
ORR W0, W3, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CSINC W21, WZR, WZR, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
TBNZ W0, #0, 40364c <_Z10cg_calc_uriiidPdS_PKdS_S1_.omp_outlined+0x15c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
TBNZ W7, #0, 40364c <_Z10cg_calc_uriiidPdS_PKdS_S1_.omp_outlined+0x15c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
TBNZ W21, #0, 40364c <_Z10cg_calc_uriiidPdS_PKdS_S1_.omp_outlined+0x15c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X1, X3, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (100.0%)
ADD X0, X23, X30	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVI V2.2D, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
MOV V2.D[0], V0.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
MOVI V1.2D, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
ORR X7, XZR, X27	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X24, X3, X0,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X21, X1, X0,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDP X1, X3, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (100.0%)
ADD X25, X3, X0,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X26, X1, X0,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
FADD V0.2D, V1.2D, V2.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
LDR X26, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (50.0%)
FADDP D0, V0.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (100.0%)
STUR D0, [X29, #488]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
CMP X5, X27	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 403628 <_Z10cg_calc_uriiidPdS_PKdS_S1_.omp_outlined+0x138>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 403650 <_Z10cg_calc_uriiidPdS_PKdS_S1_.omp_outlined+0x160>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

▶Scalability Runs Description

Run 1x1	Number processes: 1Number nodes: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-118-5752/intel/TeaLeaf/run/oneview_runs/multicore/armclang_3/oneview_run_1741271023OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_NUM_THREADS: 1OMP_PLACES: threads
Run 1x2	Number processes: 1Number nodes: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-118-5752/intel/TeaLeaf/run/oneview_runs/multicore/armclang_3/oneview_run_1741271023OMP_NUM_THREADS: 2OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x4	Number processes: 1Number nodes: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-118-5752/intel/TeaLeaf/run/oneview_runs/multicore/armclang_3/oneview_run_1741271023OMP_NUM_THREADS: 4OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x8	Number processes: 1Number nodes: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-118-5752/intel/TeaLeaf/run/oneview_runs/multicore/armclang_3/oneview_run_1741271023OMP_NUM_THREADS: 8OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x16	Number processes: 1Number nodes: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-118-5752/intel/TeaLeaf/run/oneview_runs/multicore/armclang_3/oneview_run_1741271023OMP_NUM_THREADS: 16OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x24	Number processes: 1Number nodes: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-118-5752/intel/TeaLeaf/run/oneview_runs/multicore/armclang_3/oneview_run_1741271023OMP_NUM_THREADS: 24OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x32	Number processes: 1Number nodes: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-118-5752/intel/TeaLeaf/run/oneview_runs/multicore/armclang_3/oneview_run_1741271023OMP_NUM_THREADS: 32OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x40	Number processes: 1Number nodes: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-118-5752/intel/TeaLeaf/run/oneview_runs/multicore/armclang_3/oneview_run_1741271023OMP_NUM_THREADS: 40OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x48	Number processes: 1Number nodes: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-118-5752/intel/TeaLeaf/run/oneview_runs/multicore/armclang_3/oneview_run_1741271023OMP_NUM_THREADS: 48OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x56	Number processes: 1Number nodes: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-118-5752/intel/TeaLeaf/run/oneview_runs/multicore/armclang_3/oneview_run_1741271023OMP_NUM_THREADS: 56OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x64	Number processes: 1Number nodes: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-118-5752/intel/TeaLeaf/run/oneview_runs/multicore/armclang_3/oneview_run_1741271023OMP_NUM_THREADS: 64OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x72	Number processes: 1Number nodes: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-118-5752/intel/TeaLeaf/run/oneview_runs/multicore/armclang_3/oneview_run_1741271023OMP_NUM_THREADS: 72OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x80	Number processes: 1Number nodes: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-118-5752/intel/TeaLeaf/run/oneview_runs/multicore/armclang_3/oneview_run_1741271023OMP_NUM_THREADS: 80OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x88	Number processes: 1Number nodes: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-118-5752/intel/TeaLeaf/run/oneview_runs/multicore/armclang_3/oneview_run_1741271023OMP_NUM_THREADS: 88OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x96	Number processes: 1Number nodes: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-118-5752/intel/TeaLeaf/run/oneview_runs/multicore/armclang_3/oneview_run_1741271023OMP_NUM_THREADS: 96OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads

(1x1) Efficiency	(1x1) Potential Speed-Up (%)	(1x2) Efficiency	(1x2) Potential Speed-Up (%)	(1x4) Efficiency	(1x4) Potential Speed-Up (%)	(1x8) Efficiency	(1x8) Potential Speed-Up (%)	(1x16) Efficiency	(1x16) Potential Speed-Up (%)	(1x24) Efficiency	(1x24) Potential Speed-Up (%)	(1x32) Efficiency	(1x32) Potential Speed-Up (%)	(1x40) Efficiency	(1x40) Potential Speed-Up (%)	(1x48) Efficiency	(1x48) Potential Speed-Up (%)	(1x56) Efficiency	(1x56) Potential Speed-Up (%)	(1x64) Efficiency	(1x64) Potential Speed-Up (%)	(1x72) Efficiency	(1x72) Potential Speed-Up (%)	(1x80) Efficiency	(1x80) Potential Speed-Up (%)	(1x88) Efficiency	(1x88) Potential Speed-Up (%)	(1x96) Efficiency	(1x96) Potential Speed-Up (%)
1	0	1.1	0	1.22	0	1.38	0	1.06	0	1.06	0	0.86	0.01	0.68	0.01	0.63	0.02	0.6	0.02	0.62	0.01	0.53	0.02	0.52	0.02	0.59	0.01	0.51	0.01

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
1x1	1	1	1	1	2.2249994277954	0.14125892519951
1x2	2	1.1	2.2	2	1.2150001525879	0.12547364830971
1x4	4	1.22	4.87	4	0.625	0.10763992369175
1x8	8	1.38	11.01	8	0.25499996542931	0.072938017547131
1x16	16	1.06	16.93	16	0.18000000715256	0.061144087463617
1x24	24	1.06	25.52	24	0.16999995708466	0.042394496500492
1x32	32	0.86	27.47	32	0.11999998241663	0.040536999702454
1x40	40	0.68	27.17	40	0.14999997615814	0.042762335389853
1x48	48	0.63	30.16	48	0.11999998986721	0.041037768125534
1x56	56	0.6	33.88	56	0.11999997496605	0.038404166698456
1x64	64	0.62	39.82	64	0.10499998927116	0.033737566322088
1x72	72	0.53	38.2	72	0.10500000417233	0.03599888458848
1x80	80	0.52	41.55	80	0.094999998807907	0.033668048679829
1x88	88	0.59	51.86	88	0.089999988675117	0.027317827567458
1x96	95	0.51	48.64	96	0.089999981224537	0.029822785407305

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

▶Scalability Runs Description

▼Columns Filter

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency