OV - exec - Function cg_init(int, int, int, int, double, double, double*, double const*, double const*, double*, double*, double*, double*, double*, double*) [clone .omp

	Function: cg_init(int, int, int, int, double, double, double, double const, double const, double ...	Module: exec	Source: cg.cpp:44-50	Coverage (incl. loops): 0.02% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-118-5752/intel/TeaLeaf/build/TeaLeaf/src/omp/cg.cpp: 44 - 50

--------------------------------------------------------------------------------

44:   #pragma omp parallel for

45: #endif

46:   for (int jj = halo_depth; jj < y - 1; ++jj) {

47:     for (int kk = halo_depth; kk < x - 1; ++kk) {

48:       const int index = kk + jj * x;

49:       kx[index] = rx * (w[index - 1] + w[index]) / (2.0 * w[index - 1] * w[index]);

50:       ky[index] = ry * (w[index - x] + w[index]) / (2.0 * w[index - x] * w[index]);

0x402120 SUB	SP, SP, #192

0x402124 STP	X29, X30, [SP, #96]

0x402128 STP	X28, X27, [SP, #112]

0x40212c STP	X26, X25, [SP, #128]

0x402130 STP	X24, X23, [SP, #144]

0x402134 STP	X22, X21, [SP, #160]

0x402138 STP	X20, X19, [SP, #176]

0x40213c ADD	X29, SP, #96

0x402140 LDR	W8, [X2]

0x402144 LDRSW	X21, [X3]

0x402148 SUB	W8, W8, #1

0x40214c CMP	W21, W8

0x402150 B.GE	402488

0x402154 LDR	W1, [X0]

0x402158 ORN	W9, WZR, W21

0x40215c ORR	X19, XZR, X6

0x402160 ORR	X24, XZR, X4

0x402164 ORR	X22, XZR, X5

0x402168 ORR	X23, XZR, X7

0x40216c ADRP	X0,

0x402170 ADD	X0, X0, #848

0x402174 SUB	X3, X29, #16

0x402178 SUB	X4, X29, #4

0x40217c SUB	X5, X29, #8

0x402180 STR	W1, [SP, #20]

0x402184 ADD	W20, W8, W9

0x402188 MOVZ	W8, #1

0x40218c SUB	X6, X29, #12

0x402190 MOVZ	W2, #34

0x402194 MOVZ	W7, #1

0x402198 STP	W20, WZR, [X29, #504]

0x40219c STP	WZR, W8, [X29, #496]

0x4021a0 STR	W8, [SP]

0x4021a4 BL	401520

0x4021a8 LDP	W8, W9, [X29, #504]

0x4021ac CMP	W8, W20

0x4021b0 CSEL	W8, W8, W20, #3

0x4021b4 ADD	W10, W8, #1

0x4021b8 CMP	W9, W10

0x4021bc B.CS	402478

0x4021c0 LDRSW	X10, [X24]

0x4021c4 SUB	W11, W10, #1

0x4021c8 CMP	W21, W11

0x4021cc B.GE	402478

0x4021d0 LDP	X15, X12, [X29, #96]

0x4021d4 LDR	X14, [X22]

0x4021d8 LDR	X13, [X23]

0x4021dc ADD	W16, W9, W21

0x4021e0 ADD	X0, X19, #8

0x4021e4 SUB	X22, X10, #1

0x4021e8 ORR	W11, WZR, WZR

0x4021ec MADD	W24, W10, W16, WZR

0x4021f0 STUR	W16, [X29, #476]

0x4021f4 SUB	X16, XZR, X10

0x4021f8 STUR	X16, [X29, #488]

0x4021fc LDR	X15, [X15]

0x402200 SUB	X17, X14, #8

0x402204 SUB	X2, X13, #8

0x402208 ADD	X3, X12, #8

0x40220c STR	X17, [SP, #48]

0x402210 SUB	X17, X15, #8

0x402214 STR	X17, [SP, #40]

0x402218 SUB	X17, X21, X10

0x40221c STUR	X17, [X29, #480]

0x402220 ORN	X17, XZR, X21

0x402224 ADD	X4, X17, X10

0x402228 AND	X17, X4, #8127

0x40222c STR	X17, [SP, #32]

0x402230 ADD	X17, X17, X21

0x402234 STR	X17, [SP, #24]

0x402238 B	402258

0x40223c HINT	#0

  (15) 0x402240 ADD	W16, W9, #1

  (15) 0x402244 ADD	W11, W11, #1

  (15) 0x402248 ADD	W24, W23, W10

  (15) 0x40224c CMP	W9, W8

  (15) 0x402250 ORR	W9, WZR, W16

  (15) 0x402254 B.EQ	402478

  (15) 0x402258 SBFM	X23, X24, #0, #31

  (15) 0x40225c ORR	X26, XZR, X21

  (15) 0x402260 CMP	X4, #6

  (15) 0x402264 B.CS	402300

  (15) 0x402268 LDUR	X18, [X29, #488]

  (15) 0x40226c SBFM	X16, X24, #61, #31

  (15) 0x402270 ADD	X17, X26, X23

  (15) 0x402274 SUB	X27, X22, X26

  (15) 0x402278 ORR	X25, XZR, XZR

  (15) 0x40227c ADD	X16, X16, X26,LSL #3

  (15) 0x402280 ADD	X28, X14, X17,LSL #3

  (15) 0x402284 ADD	X30, X15, X17,LSL #3

  (15) 0x402288 ADD	X26, X13, X16

  (15) 0x40228c ADD	X18, X17, X18

  (15) 0x402290 ADD	X24, X13, X18,LSL #3

  (15) 0x402294 HINT	#0

  (15) 0x402298 HINT	#0

  (15) 0x40229c HINT	#0

    (13) 0x4022a0 ADD	X16, X26, X25

    (13) 0x4022a4 LDR	D0, [X19]

    (13) 0x4022a8 SUBS	X27, X27, #1

    (13) 0x4022ac LDP	D1, D2, [X16, #1016]

    (13) 0x4022b0 FADD	D3, D2, D1

    (13) 0x4022b4 FADD	D2, D2, D2

    (13) 0x4022b8 FMUL	D0, D3, D0

    (13) 0x4022bc FMUL	D1, D1, D2

    (13) 0x4022c0 FDIV	D0, D0, D1

    (13) 0x4022c4 STR	D0, [X28, X25]

    (13) 0x4022c8 LDR	D1, [X24, X25]

    (13) 0x4022cc LDR	D2, [X16]

    (13) 0x4022d0 LDR	D0, [X12]

    (13) 0x4022d4 FADD	D3, D2, D1

    (13) 0x4022d8 FADD	D2, D2, D2

    (13) 0x4022dc FMUL	D0, D3, D0

    (13) 0x4022e0 FMUL	D1, D1, D2

    (13) 0x4022e4 FDIV	D0, D0, D1

    (13) 0x4022e8 STR	D0, [X30, X25]

    (13) 0x4022ec ADD	X25, X25, #8

    (13) 0x4022f0 B.NE	4022a0

  (15) 0x4022f4 B	402240

0x4022f8 HINT	#0

0x4022fc HINT	#0

(14) 0x402300 LDUR	W16, [X29, #476]

(14) 0x402304 ADD	W17, W16, W11

(14) 0x402308 LDUR	X16, [X29, #480]

(14) 0x40230c MADD	W17, W10, W17, WZR

(14) 0x402310 SBFM	X18, X17, #0, #31

(14) 0x402314 ADD	X27, X2, W17,SXTW #3

(14) 0x402318 ADD	X17, X16, X18

(14) 0x40231c ADD	X20, X21, X18

(14) 0x402320 ADD	X6, X10, X18

(14) 0x402324 ADD	X28, X13, X17,LSL #3

(14) 0x402328 LDP	X16, X17, [SP, #40]

(14) 0x40232c ADD	X7, X14, X20,LSL #3

(14) 0x402330 ADD	X25, X2, X6,LSL #3

(14) 0x402334 ADD	X26, X2, X20,LSL #3

(14) 0x402338 ADD	X5, X15, X20,LSL #3

(14) 0x40233c CMP	X7, X0

(14) 0x402340 ADD	X1, X17, X6,LSL #3

(14) 0x402344 ADD	X16, X16, X6,LSL #3

(14) 0x402348 CCMP	X1, X19, #0, #3

(14) 0x40234c CSINC	W18, WZR, WZR, #9

(14) 0x402350 CMP	X7, X27

(14) 0x402354 CCMP	X28, X1, #2, #3

(14) 0x402358 CSINC	W17, WZR, WZR, #2

(14) 0x40235c CMP	X7, X25

(14) 0x402360 CCMP	X26, X1, #2, #3

(14) 0x402364 CSINC	W20, WZR, WZR, #2

(14) 0x402368 CMP	X7, X3

(14) 0x40236c CCMP	X1, X12, #0, #3

(14) 0x402370 CSINC	W6, WZR, WZR, #9

(14) 0x402374 CMP	X5, X0

(14) 0x402378 CCMP	X16, X19, #0, #3

(14) 0x40237c CSINC	W30, WZR, WZR, #9

(14) 0x402380 CMP	X5, X27

(14) 0x402384 CCMP	X28, X16, #2, #3

(14) 0x402388 CSINC	W28, WZR, WZR, #2

(14) 0x40238c CMP	X5, X25

(14) 0x402390 CCMP	X26, X16, #2, #3

(14) 0x402394 ORR	X26, XZR, X21

(14) 0x402398 CSINC	W27, WZR, WZR, #2

(14) 0x40239c CMP	X5, X3

(14) 0x4023a0 CCMP	X16, X12, #0, #3

(14) 0x4023a4 CSINC	W25, WZR, WZR, #9

(14) 0x4023a8 CMP	X5, X1

(14) 0x4023ac CCMP	X7, X16, #2, #3

(14) 0x4023b0 B.CC	402268

(14) 0x4023b4 ORR	X26, XZR, X21

(14) 0x4023b8 TBNZ	W18, #0, 402268

(14) 0x4023bc ORR	X26, XZR, X21

(14) 0x4023c0 TBNZ	W17, #0, 402268

(14) 0x4023c4 ORR	X26, XZR, X21

(14) 0x4023c8 TBNZ	W20, #0, 402268

(14) 0x4023cc ORR	X26, XZR, X21

(14) 0x4023d0 TBNZ	W6, #0, 402268

(14) 0x4023d4 ORR	X26, XZR, X21

(14) 0x4023d8 TBNZ	W30, #0, 402268

(14) 0x4023dc ORR	X26, XZR, X21

(14) 0x4023e0 TBNZ	W28, #0, 402268

(14) 0x4023e4 ORR	X26, XZR, X21

(14) 0x4023e8 TBNZ	W27, #0, 402268

(14) 0x4023ec ORR	X26, XZR, X21

(14) 0x4023f0 TBNZ	W25, #0, 402268

(14) 0x4023f4 LDUR	X17, [X29, #480]

(14) 0x4023f8 LDR	X30, [SP, #32]

(14) 0x4023fc ADD	X16, X21, X23

(14) 0x402400 ADD	X25, X15, X16,LSL #3

(14) 0x402404 ADD	X27, X14, X16,LSL #3

(14) 0x402408 ADD	X28, X13, X16,LSL #3

(14) 0x40240c ADD	X17, X17, X23

(14) 0x402410 ADD	X26, X13, X17,LSL #3

(14) 0x402414 HINT	#0

(14) 0x402418 HINT	#0

(14) 0x40241c HINT	#0

  (16) 0x402420 LDUR	Q1, [X28, #504]

  (16) 0x402424 LDR	Q2, [X28], #16

  (16) 0x402428 LDR	D0, [X19]

  (16) 0x40242c SUBS	X30, X30, #2

  (16) 0x402430 FADD	V3.2D, V2.2D, V1.2D

  (16) 0x402434 FMUL	V0.2D, V3.2D, V0.D[0]

  (16) 0x402438 FADD	V3.2D, V2.2D, V2.2D

  (16) 0x40243c FMUL	V1.2D, V1.2D, V3.2D

  (16) 0x402440 FDIV	V0.2D, V0.2D, V1.2D

  (16) 0x402444 LDR	Q1, [X26], #16

  (16) 0x402448 FADD	V2.2D, V2.2D, V1.2D

  (16) 0x40244c FMUL	V1.2D, V1.2D, V3.2D

  (16) 0x402450 STR	Q0, [X27], #16

  (16) 0x402454 LDR	D0, [X12]

  (16) 0x402458 FMUL	V0.2D, V2.2D, V0.D[0]

  (16) 0x40245c FDIV	V0.2D, V0.2D, V1.2D

  (16) 0x402460 STR	Q0, [X25], #16

  (16) 0x402464 B.NE	402420

(14) 0x402468 LDP	X26, X16, [SP, #24]

(14) 0x40246c CMP	X4, X16

(14) 0x402470 B.EQ	402240

(14) 0x402474 B	402268

0x402478 LDR	W1, [SP, #20]

0x40247c ADRP	X0,

0x402480 ADD	X0, X0, #872

0x402484 BL	401750

0x402488 LDP	X20, X19, [SP, #176]

0x40248c LDP	X22, X21, [SP, #160]

0x402490 LDP	X24, X23, [SP, #144]

0x402494 LDP	X26, X25, [SP, #128]

0x402498 LDP	X28, X27, [SP, #112]

0x40249c LDP	X29, X30, [SP, #96]

0x4024a0 ADD	SP, SP, #192

0x4024a4 RET

0x4024a8 HINT	#0

0x4024ac HINT	#0

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run 1x1

Source file and lines	cg.cpp:44-50
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-118-5752/intel/TeaLeaf/build/TeaLeaf/src/omp/cg.cpp:44-50.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 48% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 11.17 to 7.37 cycles (1.51x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 11.17 to 1.00 cycles (11.17x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 164 bytes. The binary function is storing 172 bytes.

General properties

nb instructions	88
loop length	352
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

10.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	3.50	3.50	7.58	7.58	7.50	7.50	7.42	7.42	0.00	0.00	0.00	0.00	11.17	10.83	11.00	8.50	8.50
cycles	3.50	3.50	7.58	7.58	7.50	7.50	7.42	7.42	0.00	0.00	0.00	0.00	11.17	10.83	11.00	8.50	8.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	10.38
Overall L1	11.17

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 11.17 cycles. At this rate:

15% of peak load performance is reached (14.69 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
32% of peak store performance is reached (15.40 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 402120

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
SUB SP, SP, #192	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X29, X30, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X28, X27, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X26, X25, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X24, X23, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X22, X21, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X20, X19, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #96	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR W8, [X2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDRSW X21, [X3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SUB W8, W8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W21, W8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 402488 <_Z7cg_initiiiiddPdPKdS1_S_S_S_S_S_S_.omp_outlined.5+0x368>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W1, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORN W9, WZR, W21	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ORR X19, XZR, X6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X24, XZR, X4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X22, XZR, X5	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X23, XZR, X7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADRP X0, <42f16c>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #848	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X3, X29, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X4, X29, #4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X5, X29, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR W1, [SP, #20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD W20, W8, W9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MOVZ W8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SUB X6, X29, #12	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W2, #34	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W7, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STP W20, WZR, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP WZR, W8, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR W8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 401520 <@plt_start@+0x80>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP W8, W9, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP W8, W20	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CSEL W8, W8, W20, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W10, W8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W9, W10	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.CS 402478 <_Z7cg_initiiiiddPdPKdS1_S_S_S_S_S_S_.omp_outlined.5+0x358>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDRSW X10, [X24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SUB W11, W10, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W21, W11	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 402478 <_Z7cg_initiiiiddPdPKdS1_S_S_S_S_S_S_.omp_outlined.5+0x358>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X15, X12, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X14, [X22]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X13, [X23]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD W16, W9, W21	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD X0, X19, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X22, X10, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR W11, WZR, WZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MADD W24, W10, W16, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
STUR W16, [X29, #476]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
SUB X16, XZR, X10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STUR X16, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X15, [X15]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X17, X14, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X2, X13, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X3, X12, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X17, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
SUB X17, X15, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR X17, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
SUB X17, X21, X10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STUR X17, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORN X17, XZR, X21	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X4, X17, X10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
AND X17, X4, #8127	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR X17, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X17, X17, X21	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR X17, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
B 402258 <_Z7cg_initiiiiddPdPKdS1_S_S_S_S_S_S_.omp_outlined.5+0x138>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
LDR W1, [SP, #20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADRP X0, <42f47c>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #872	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 401750 <@plt_start@+0x2b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X20, X19, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X22, X21, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X24, X23, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X26, X25, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X28, X27, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X29, X30, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
ADD SP, SP, #192	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run 1x1

Source file and lines	cg.cpp:44-50
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-118-5752/intel/TeaLeaf/build/TeaLeaf/src/omp/cg.cpp:44-50.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 11.17 to 1.00 cycles (11.17x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 164 bytes. The binary function is storing 172 bytes.

General properties

nb instructions	88
loop length	352
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

10.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	3.50	3.50	7.58	7.58	7.50	7.50	7.42	7.42	0.00	0.00	0.00	0.00	11.17	10.83	11.00	8.50	8.50
cycles	3.50	3.50	7.58	7.58	7.50	7.50	7.42	7.42	0.00	0.00	0.00	0.00	11.17	10.83	11.00	8.50	8.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	10.38
Overall L1	11.17

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 11.17 cycles. At this rate:

15% of peak load performance is reached (14.69 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
32% of peak store performance is reached (15.40 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 402120

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
SUB SP, SP, #192	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X29, X30, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X28, X27, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X26, X25, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X24, X23, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X22, X21, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X20, X19, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #96	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR W8, [X2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDRSW X21, [X3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SUB W8, W8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W21, W8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 402488 <_Z7cg_initiiiiddPdPKdS1_S_S_S_S_S_S_.omp_outlined.5+0x368>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W1, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORN W9, WZR, W21	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ORR X19, XZR, X6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X24, XZR, X4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X22, XZR, X5	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X23, XZR, X7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADRP X0, <42f16c>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #848	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X3, X29, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X4, X29, #4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X5, X29, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR W1, [SP, #20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD W20, W8, W9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MOVZ W8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SUB X6, X29, #12	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W2, #34	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W7, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STP W20, WZR, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP WZR, W8, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR W8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 401520 <@plt_start@+0x80>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP W8, W9, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP W8, W20	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CSEL W8, W8, W20, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W10, W8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W9, W10	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.CS 402478 <_Z7cg_initiiiiddPdPKdS1_S_S_S_S_S_S_.omp_outlined.5+0x358>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDRSW X10, [X24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SUB W11, W10, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W21, W11	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 402478 <_Z7cg_initiiiiddPdPKdS1_S_S_S_S_S_S_.omp_outlined.5+0x358>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X15, X12, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X14, [X22]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X13, [X23]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD W16, W9, W21	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD X0, X19, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X22, X10, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR W11, WZR, WZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MADD W24, W10, W16, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
STUR W16, [X29, #476]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
SUB X16, XZR, X10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STUR X16, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X15, [X15]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X17, X14, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X2, X13, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X3, X12, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X17, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
SUB X17, X15, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR X17, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
SUB X17, X21, X10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STUR X17, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORN X17, XZR, X21	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X4, X17, X10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
AND X17, X4, #8127	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR X17, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X17, X17, X21	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR X17, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
B 402258 <_Z7cg_initiiiiddPdPKdS1_S_S_S_S_S_S_.omp_outlined.5+0x138>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
LDR W1, [SP, #20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADRP X0, <42f47c>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #872	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 401750 <@plt_start@+0x2b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X20, X19, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X22, X21, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X24, X23, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X26, X25, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X28, X27, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X29, X30, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
ADD SP, SP, #192	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A

▶Scalability Runs Description

Run 1x1	Number processes: 1Number nodes: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-118-5752/intel/TeaLeaf/run/oneview_runs/multicore/armclang_3/oneview_run_1741271023OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_NUM_THREADS: 1OMP_PLACES: threads
Run 1x2	Number processes: 1Number nodes: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-118-5752/intel/TeaLeaf/run/oneview_runs/multicore/armclang_3/oneview_run_1741271023OMP_NUM_THREADS: 2OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x4	Number processes: 1Number nodes: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-118-5752/intel/TeaLeaf/run/oneview_runs/multicore/armclang_3/oneview_run_1741271023OMP_NUM_THREADS: 4OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x8	Number processes: 1Number nodes: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-118-5752/intel/TeaLeaf/run/oneview_runs/multicore/armclang_3/oneview_run_1741271023OMP_NUM_THREADS: 8OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x16	Number processes: 1Number nodes: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-118-5752/intel/TeaLeaf/run/oneview_runs/multicore/armclang_3/oneview_run_1741271023OMP_NUM_THREADS: 16OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x24	Number processes: 1Number nodes: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-118-5752/intel/TeaLeaf/run/oneview_runs/multicore/armclang_3/oneview_run_1741271023OMP_NUM_THREADS: 24OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x32	Number processes: 1Number nodes: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-118-5752/intel/TeaLeaf/run/oneview_runs/multicore/armclang_3/oneview_run_1741271023OMP_NUM_THREADS: 32OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x40	Number processes: 1Number nodes: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-118-5752/intel/TeaLeaf/run/oneview_runs/multicore/armclang_3/oneview_run_1741271023OMP_NUM_THREADS: 40OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x48	Number processes: 1Number nodes: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-118-5752/intel/TeaLeaf/run/oneview_runs/multicore/armclang_3/oneview_run_1741271023OMP_NUM_THREADS: 48OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x56	Number processes: 1Number nodes: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-118-5752/intel/TeaLeaf/run/oneview_runs/multicore/armclang_3/oneview_run_1741271023OMP_NUM_THREADS: 56OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x64	Number processes: 1Number nodes: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-118-5752/intel/TeaLeaf/run/oneview_runs/multicore/armclang_3/oneview_run_1741271023OMP_NUM_THREADS: 64OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x72	Number processes: 1Number nodes: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-118-5752/intel/TeaLeaf/run/oneview_runs/multicore/armclang_3/oneview_run_1741271023OMP_NUM_THREADS: 72OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x80	Number processes: 1Number nodes: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-118-5752/intel/TeaLeaf/run/oneview_runs/multicore/armclang_3/oneview_run_1741271023OMP_NUM_THREADS: 80OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x88	Number processes: 1Number nodes: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-118-5752/intel/TeaLeaf/run/oneview_runs/multicore/armclang_3/oneview_run_1741271023OMP_NUM_THREADS: 88OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x96	Number processes: 1Number nodes: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-118-5752/intel/TeaLeaf/run/oneview_runs/multicore/armclang_3/oneview_run_1741271023OMP_NUM_THREADS: 96OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads

(1x1) Efficiency	(1x1) Potential Speed-Up (%)	(1x2) Efficiency	(1x2) Potential Speed-Up (%)	(1x4) Efficiency	(1x4) Potential Speed-Up (%)	(1x8) Efficiency	(1x8) Potential Speed-Up (%)	(1x16) Efficiency	(1x16) Potential Speed-Up (%)	(1x24) Efficiency	(1x24) Potential Speed-Up (%)	(1x32) Efficiency	(1x32) Potential Speed-Up (%)	(1x40) Efficiency	(1x40) Potential Speed-Up (%)	(1x48) Efficiency	(1x48) Potential Speed-Up (%)	(1x56) Efficiency	(1x56) Potential Speed-Up (%)	(1x64) Efficiency	(1x64) Potential Speed-Up (%)	(1x72) Efficiency	(1x72) Potential Speed-Up (%)	(1x80) Efficiency	(1x80) Potential Speed-Up (%)	(1x88) Efficiency	(1x88) Potential Speed-Up (%)	(1x96) Efficiency	(1x96) Potential Speed-Up (%)
1	0	1	0	1.09	0	1.04	0	0.88	0	1.7	0	0.71	0	0.41	0.01	0.61	0	0.28	0.01	0.19	0.01	0.4	0	0.52	0	0.22	0.01	0.35	0

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
1x1	1	1	1	1	0.28999999165535	0.01841127872467
1x2	2	1	2	2	0.14500002563	0.017969066277146
1x4	4	1.09	4.37	4	0.074999995529652	0.015629906207323
1x8	8	1.04	8.28	8	0.049999997019768	0.012645601294935
1x16	16	0.88	14.01	16	0.024999998509884	0.0096312882378697
1x24	24	1.7	40.8	24	0.014999996870756	0.0034566258545965
1x32	32	0.71	22.58	32	0.019999995827675	0.0064294659532607
1x40	40	0.41	16.42	40	0.01999999769032	0.0092194033786654
1x48	48	0.61	29.22	48	0.024999998509884	0.0055220793001354
1x56	56	0.28	15.79	56	0.024999996647239	0.010740593075752
1x64	64	0.19	11.92	64	0.029999995604157	0.014689108356833
1x72	72	0.4	28.48	72	0.014999998733401	0.0062944157980382
1x80	80	0.52	41.66	80	0.019999999552965	0.0043760575354099
1x88	85	0.22	19.55	88	0.025000000372529	0.0094449939206243
1x96	88	0.35	33.58	96	0.01999999769032	0.0056301597505808

Name	Coverage (%)	Time (s)
▼cg_init(int, int, int, int, double, double, double, double const, double const, double, double, double, double, double, double*) [clone .omp_outlined.5]–	0.02	0.29
▼Loop 14 - cg.cpp:46-50 - exec–	0.00	0.00
○Loop 16 - cg.cpp:47-50 - exec	0.02	0.29
▼Loop 15 - cg.cpp:46-50 - exec–	0.00	0.00
○Loop 13 - cg.cpp:47-50 - exec	0.00	0.00

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

▶Scalability Runs Description

▼Columns Filter

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency