OV - exec - Function calculate_residual(int, int, int, double const*, double const*, double*, double const*, double const*) [clone ._omp

	Function: calculate_residual(int, int, int, double const, double const, double, double const, do ...	Module: exec	Source: solver_methods.cpp:66-72	Coverage (incl. loops): 0.01% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-118-5752/intel/TeaLeaf/build/TeaLeaf/src/omp/solver_methods.cpp: 66 - 72

--------------------------------------------------------------------------------

66:   #pragma omp parallel for

67: #endif

68:   for (int jj = halo_depth; jj < y - halo_depth; ++jj) {

69:     for (int kk = halo_depth; kk < x - halo_depth; ++kk) {

70:       const int index = kk + jj * x;

71:       const double smvp = tealeaf_SMVP(u);

72:       r[index] = u0[index] - smvp;

0x409dc4 STP	X29, X30, [SP, #976]!

0x409dc8 ADD	X29, SP, #0

0x409dcc STP	X19, X20, [SP, #16]

0x409dd0 ORR	X20, XZR, X0

0x409dd4 BL	4016d0

0x409dd8 ORR	W19, WZR, W0

0x409ddc BL	4016e0

0x409de0 ORR	W14, WZR, W0

0x409de4 LDP	W0, W17, [X20, #44]

0x409de8 SUB	W2, W0, W17,LSL #1

0x409dec SDIV	W1, W2, W19

0x409df0 MSUB	W3, W1, W19, W2

0x409df4 CMP	W14, W3

0x409df8 B.LT	409fbc

(201) 0x409dfc MADD	W4, W1, W14, W3

(201) 0x409e00 ADD	W5, W1, W4

(201) 0x409e04 CMP	W4, W5

(201) 0x409e08 B.GE	409fb0

(201) 0x409e0c LDR	W18, [X20, #40]

(201) 0x409e10 ADD	W14, W17, W4

(201) 0x409e14 FMOV	D31, #1.0000000

(201) 0x409e18 ADD	W16, W17, W5

(201) 0x409e1c LDR	X4, [X20, #32]

(201) 0x409e20 STR	X21, [SP, #32]

(201) 0x409e24 SBFM	X21, X17, #0, #31

(201) 0x409e28 LDP	X3, X12, [X20]

(201) 0x409e2c SUB	W6, W18, W17,LSL #1

(201) 0x409e30 SBFM	X13, X18, #61, #31

(201) 0x409e34 SUB	W30, W18, W17

(201) 0x409e38 MADD	W15, W14, W18, WZR

(201) 0x409e3c LDP	X7, X20, [X20, #16]

(201) 0x409e40 ADD	X19, X6, X21

(201) 0x409e44 ADD	X2, X4, X13

(201) 0x409e48 ADD	X11, X3, X13

(201) 0x409e4c SUB	X10, X3, X13

(201) 0x409e50 ADD	X9, X3, #8

(201) 0x409e54 SUB	X8, X3, #8

(201) 0x409e58 ADD	X5, X20, #8

(201) 0x409e5c HINT	#0

  (202) 0x409e60 CMP	W17, W30

  (202) 0x409e64 B.GE	409f9c

  (202) 0x409e68 SBFM	X0, X15, #0, #31

  (202) 0x409e6c ADD	X6, X19, X0

  (202) 0x409e70 ADD	X1, X0, X21

  (202) 0x409e74 UBFM	X13, X6, #61, #60

  (202) 0x409e78 UBFM	X0, X1, #61, #60

  (202) 0x409e7c SUB	X6, X13, X1,LSL #3

  (202) 0x409e80 TBZ	W6, #3, 409ee4

  (202) 0x409e84 LDR	D30, [X5, X0]

  (202) 0x409e88 LDR	D3, [X20, X0]

  (202) 0x409e8c LDR	D4, [X4, X0]

  (202) 0x409e90 LDR	D5, [X2, X0]

  (202) 0x409e94 FADD	D26, D30, D3

  (202) 0x409e98 LDR	D1, [X11, X0]

  (202) 0x409e9c LDR	D23, [X9, X0]

  (202) 0x409ea0 FADD	D25, D5, D4

  (202) 0x409ea4 LDR	D29, [X12, X0]

  (202) 0x409ea8 FADD	D0, D26, D31

  (202) 0x409eac LDR	D21, [X8, X0]

  (202) 0x409eb0 FMUL	D6, D5, D1

  (202) 0x409eb4 LDR	D20, [X10, X0]

  (202) 0x409eb8 LDR	D2, [X3, X0]

  (202) 0x409ebc FMADD	D7, D30, D23, D29

  (202) 0x409ec0 FADD	D16, D0, D25

  (202) 0x409ec4 FMADD	D17, D3, D21, D6

  (202) 0x409ec8 FMADD	D18, D4, D20, D7

  (202) 0x409ecc FMSUB	D19, D16, D2, D17

  (202) 0x409ed0 FADD	D22, D18, D19

  (202) 0x409ed4 STR	D22, [X7, X0]

  (202) 0x409ed8 ADD	X0, X0, #8

  (202) 0x409edc CMP	X13, X0

  (202) 0x409ee0 B.EQ	409f9c

    (203) 0x409ee4 LDR	D28, [X5, X0]

    (203) 0x409ee8 ADD	X1, X0, #8

    (203) 0x409eec LDR	D27, [X20, X0]

    (203) 0x409ef0 LDR	D24, [X4, X0]

    (203) 0x409ef4 LDR	D30, [X2, X0]

    (203) 0x409ef8 FADD	D3, D28, D27

    (203) 0x409efc LDR	D5, [X11, X0]

    (203) 0x409f00 LDR	D26, [X9, X0]

    (203) 0x409f04 FADD	D1, D30, D24

    (203) 0x409f08 LDR	D4, [X12, X0]

    (203) 0x409f0c FADD	D23, D3, D31

    (203) 0x409f10 LDR	D25, [X8, X0]

    (203) 0x409f14 FMUL	D29, D30, D5

    (203) 0x409f18 LDR	D0, [X10, X0]

    (203) 0x409f1c LDR	D21, [X3, X0]

    (203) 0x409f20 FMADD	D6, D28, D26, D4

    (203) 0x409f24 FADD	D20, D23, D1

    (203) 0x409f28 FMADD	D2, D27, D25, D29

    (203) 0x409f2c FMADD	D7, D24, D0, D6

    (203) 0x409f30 FMSUB	D16, D20, D21, D2

    (203) 0x409f34 FADD	D17, D7, D16

    (203) 0x409f38 STR	D17, [X7, X0]

    (203) 0x409f3c ADD	X0, X0, #16

    (203) 0x409f40 LDR	D18, [X5, X1]

    (203) 0x409f44 LDR	D19, [X20, X1]

    (203) 0x409f48 LDR	D22, [X4, X1]

    (203) 0x409f4c LDR	D28, [X2, X1]

    (203) 0x409f50 FADD	D27, D18, D19

    (203) 0x409f54 LDR	D24, [X11, X1]

    (203) 0x409f58 LDR	D30, [X9, X1]

    (203) 0x409f5c FADD	D3, D28, D22

    (203) 0x409f60 LDR	D5, [X12, X1]

    (203) 0x409f64 FADD	D26, D27, D31

    (203) 0x409f68 LDR	D1, [X8, X1]

    (203) 0x409f6c FMUL	D4, D28, D24

    (203) 0x409f70 LDR	D25, [X10, X1]

    (203) 0x409f74 LDR	D0, [X3, X1]

    (203) 0x409f78 FMADD	D21, D18, D30, D5

    (203) 0x409f7c FADD	D29, D26, D3

    (203) 0x409f80 FMADD	D23, D19, D1, D4

    (203) 0x409f84 FMADD	D6, D22, D25, D21

    (203) 0x409f88 FMSUB	D20, D29, D0, D23

    (203) 0x409f8c FADD	D2, D6, D20

    (203) 0x409f90 STR	D2, [X7, X1]

    (203) 0x409f94 CMP	X13, X0

    (203) 0x409f98 B.NE	409ee4

  (202) 0x409f9c ADD	W14, W14, #1

  (202) 0x409fa0 ADD	W15, W15, W18

  (202) 0x409fa4 CMP	W16, W14

  (202) 0x409fa8 B.GT	409e60

(201) 0x409fac LDR	X21, [SP, #32]

(201) 0x409fb0 LDP	X19, X20, [SP, #16]

(201) 0x409fb4 LDP	X29, X30, [SP], #48

(201) 0x409fb8 RET

(201) 0x409fbc ADD	W1, W1, #1

(201) 0x409fc0 MOVZ	W3, #0

(201) 0x409fc4 B	409dfc

Coverage (%)	Name	Source Location	Module
►98.75+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.25+	GOMP_parallel	libgomp.h:980	libgomp.so.1.0.0
○	run_calculate_residual(Chunk*,[...]	solver_methods.cpp:132	exec
○	solve_finished_driver(Chunk*, [...]	solve_finished_driver.cpp:15	exec
○	solve(Chunk*, Settings&, int, [...]	diffuse.cpp:53	exec
○	diffuse(Chunk*, Settings&)	diffuse.cpp:12	exec
○	main	main.cpp:179	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	basic_string.h:809	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_8

Source file and lines	solver_methods.cpp:66-72
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-118-5752/intel/TeaLeaf/build/TeaLeaf/src/omp/solver_methods.cpp:66-72.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 53% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 12.50 to 3.12 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.50 to 1.00 cycles (12.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 8 bytes. The binary function is storing 32 bytes.

General properties

nb instructions	14
loop length	56
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.50	1.50	1.83	1.83	1.83	1.83	2.00	1.67	0.00	0.00	0.00	0.00	1.00	1.00	1.00	1.00	1.00
cycles	1.50	1.50	1.83	1.83	1.83	1.83	2.00	1.67	0.00	0.00	0.00	0.00	1.00	1.00	1.00	1.00	1.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	1.75
Overall L1	5.00-12.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.50 cycles. At this rate:

0% of peak load performance is reached (0.64 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (2.56 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 409dc4

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #976]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
BL 4016d0 <@plt_start@+0x100>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W19, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4016e0 <@plt_start@+0x110>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W14, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDP W0, W17, [X20, #44]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
SUB W2, W0, W17,LSL #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
SDIV W1, W2, W19	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5-12	5-12.50	scal (25.0%)
MSUB W3, W1, W19, W2	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
CMP W14, W3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.LT 409fbc <_Z18calculate_residualiiiPKdS0_PdS0_S0_._omp_fn.0+0x1f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_8

Source file and lines	solver_methods.cpp:66-72
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-118-5752/intel/TeaLeaf/build/TeaLeaf/src/omp/solver_methods.cpp:66-72.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.50 to 1.00 cycles (12.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 8 bytes. The binary function is storing 32 bytes.

General properties

nb instructions	14
loop length	56
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.50	1.50	1.83	1.83	1.83	1.83	2.00	1.67	0.00	0.00	0.00	0.00	1.00	1.00	1.00	1.00	1.00
cycles	1.50	1.50	1.83	1.83	1.83	1.83	2.00	1.67	0.00	0.00	0.00	0.00	1.00	1.00	1.00	1.00	1.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	1.75
Overall L1	5.00-12.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.50 cycles. At this rate:

0% of peak load performance is reached (0.64 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (2.56 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 409dc4

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #976]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
BL 4016d0 <@plt_start@+0x100>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W19, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4016e0 <@plt_start@+0x110>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W14, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDP W0, W17, [X20, #44]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
SUB W2, W0, W17,LSL #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
SDIV W1, W2, W19	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5-12	5-12.50	scal (25.0%)
MSUB W3, W1, W19, W2	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
CMP W14, W3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.LT 409fbc <_Z18calculate_residualiiiPKdS0_PdS0_S0_._omp_fn.0+0x1f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼calculate_residual(int, int, int, double const, double const, double, double const, double const*) [clone ._omp_fn.0]–	0.01	0.02
▼Loop 201 - solver_methods.cpp:66-72 - exec–	0.00	0.00
▼Loop 202 - solver_methods.cpp:69-72 - exec–	0.00	0.00
○Loop 203 - solver_methods.cpp:69-72 - exec	0.01	0.02

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code