OV - exec - Function update_right(int, int, int, int, double*, bool) [clone ._omp

	Function: update_right(int, int, int, int, double*, bool) [clone ._omp_fn.0]	Module: exec	Source: local_halos.cpp:25-30	Coverage (incl. loops): 0.02% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-118-5752/intel/TeaLeaf/build/TeaLeaf/src/omp/local_halos.cpp: 25 - 30

--------------------------------------------------------------------------------

25:   #pragma omp parallel for

26: #endif

27:   for (int jj = halo_depth; jj < y - halo_depth; ++jj) {

28:     for (int kk = 0; kk < depth; ++kk) {

29:       int base = jj * x;

30:       buffer[base + (x - halo_depth + kk)] = buffer[base + (x - halo_depth - 1 - kk)];

0x406b70 STP	X29, X30, [SP, #992]!

0x406b74 ADD	X29, SP, #0

0x406b78 STP	X19, X20, [SP, #16]

0x406b7c ORR	X20, XZR, X0

0x406b80 BL	4016d0

0x406b84 ORR	W19, WZR, W0

0x406b88 BL	4016e0

0x406b8c ORR	W9, WZR, W0

0x406b90 LDP	W0, W3, [X20, #12]

0x406b94 SUB	W1, W0, W3,LSL #1

0x406b98 SDIV	W2, W1, W19

0x406b9c MSUB	W4, W2, W19, W1

0x406ba0 CMP	W9, W4

0x406ba4 B.LT	406e4c

(90) 0x406ba8 MADD	W5, W2, W9, W4

(90) 0x406bac ADD	W6, W2, W5

(90) 0x406bb0 CMP	W5, W6

(90) 0x406bb4 B.GE	406cbc

(90) 0x406bb8 LDR	X12, [X20]

(90) 0x406bbc ADD	W30, W3, W5

(90) 0x406bc0 ADD	W11, W3, W6

(90) 0x406bc4 ORN	W7, WZR, W30

(90) 0x406bc8 LDR	W15, [X20, #8]

(90) 0x406bcc ADD	W8, W7, W11

(90) 0x406bd0 AND	W13, W8, #128

(90) 0x406bd4 LDR	W14, [X20, #20]

(90) 0x406bd8 UBFM	X20, X12, #63, #62

(90) 0x406bdc MADD	W10, W30, W15, WZR

(90) 0x406be0 CMP	W14, #0

(90) 0x406be4 B.GT	406cc8

(90) 0x406be8 ADD	W30, W30, #1

(90) 0x406bec ADD	W10, W10, W15

(90) 0x406bf0 CMP	W11, W30

(90) 0x406bf4 B.LE	406cbc

(90) 0x406bf8 CBZ	W13, 406ca4

(90) 0x406bfc CMP	W13, #1

(90) 0x406c00 B.EQ	406c8c

(90) 0x406c04 CMP	W13, #2

(90) 0x406c08 B.EQ	406c7c

(90) 0x406c0c CMP	W13, #3

(90) 0x406c10 B.EQ	406c6c

(90) 0x406c14 CMP	W13, #4

(90) 0x406c18 B.EQ	406c5c

(90) 0x406c1c CMP	W13, #5

(90) 0x406c20 B.EQ	406c4c

(90) 0x406c24 CMP	W13, #6

(90) 0x406c28 B.EQ	406c3c

(90) 0x406c2c CMP	W14, #0

(90) 0x406c30 B.GT	406cc8

(90) 0x406c34 ADD	W30, W30, #1

(90) 0x406c38 ADD	W10, W10, W15

(90) 0x406c3c CMP	W14, #0

(90) 0x406c40 B.GT	406cc8

(90) 0x406c44 ADD	W30, W30, #1

(90) 0x406c48 ADD	W10, W10, W15

(90) 0x406c4c CMP	W14, #0

(90) 0x406c50 B.GT	406cc8

(90) 0x406c54 ADD	W30, W30, #1

(90) 0x406c58 ADD	W10, W10, W15

(90) 0x406c5c CMP	W14, #0

(90) 0x406c60 B.GT	406cc8

(90) 0x406c64 ADD	W30, W30, #1

(90) 0x406c68 ADD	W10, W10, W15

(90) 0x406c6c CMP	W14, #0

(90) 0x406c70 B.GT	406cc8

(90) 0x406c74 ADD	W30, W30, #1

(90) 0x406c78 ADD	W10, W10, W15

(90) 0x406c7c CMP	W14, #0

(90) 0x406c80 B.GT	406cc8

(90) 0x406c84 ADD	W30, W30, #1

(90) 0x406c88 ADD	W10, W10, W15

(90) 0x406c8c CMP	W14, #0

(90) 0x406c90 B.GT	406cc8

(90) 0x406c94 ADD	W30, W30, #1

(90) 0x406c98 ADD	W10, W10, W15

(90) 0x406c9c CMP	W11, W30

(90) 0x406ca0 B.LE	406cbc

  (91) 0x406ca4 CMP	W14, #0

  (91) 0x406ca8 B.GT	406cc8

  (91) 0x406cac ADD	W30, W30, #8

  (91) 0x406cb0 ADD	W10, W10, W15,LSL #3

  (91) 0x406cb4 CMP	W11, W30

  (91) 0x406cb8 B.GT	406ca4

(90) 0x406cbc LDP	X19, X20, [SP, #16]

(90) 0x406cc0 LDP	X29, X30, [SP], #32

(90) 0x406cc4 RET

(90) 0x406cc8 SUB	W16, W15, W3

(90) 0x406ccc SBFM	X19, X16, #0, #31

(90) 0x406cd0 ADD	X9, X19, W14,SXTW

(90) 0x406cd4 HINT	#0

(90) 0x406cd8 HINT	#0

(90) 0x406cdc HINT	#0

  (89) 0x406ce0 SBFM	X17, X10, #0, #31

  (89) 0x406ce4 ADD	X18, X19, X17

  (89) 0x406ce8 ADD	X0, X9, X17

  (89) 0x406cec ADD	X8, X12, X0,LSL #3

  (89) 0x406cf0 UBFM	X1, X18, #60, #59

  (89) 0x406cf4 UBFM	X2, X18, #61, #60

  (89) 0x406cf8 ADD	X16, X12, X18,LSL #3

  (89) 0x406cfc SUB	X13, X1, #8

  (89) 0x406d00 SUB	X4, X8, X16

  (89) 0x406d04 SUB	X5, X4, #8

  (89) 0x406d08 UBFM	X6, X5, #3, #63

  (89) 0x406d0c ADD	X7, X6, #1

  (89) 0x406d10 ANDS	X3, X7, #4224

  (89) 0x406d14 B.EQ	406da8

  (89) 0x406d18 CMP	X3, #1

  (89) 0x406d1c B.EQ	406d94

  (89) 0x406d20 CMP	X3, #2

  (89) 0x406d24 B.EQ	406d88

  (89) 0x406d28 CMP	X3, #3

  (89) 0x406d2c B.EQ	406d7c

  (89) 0x406d30 CMP	X3, #4

  (89) 0x406d34 B.EQ	406d70

  (89) 0x406d38 CMP	X3, #5

  (89) 0x406d3c B.EQ	406d64

  (89) 0x406d40 CMP	X3, #6

  (89) 0x406d44 B.EQ	406d58

  (89) 0x406d48 SUB	X14, X13, X16

  (89) 0x406d4c ADD	X16, X16, #8

  (89) 0x406d50 LDR	D31, [X14, X20]

  (89) 0x406d54 STR	D31, [X12, X2]

  (89) 0x406d58 SUB	X17, X13, X16

  (89) 0x406d5c LDR	D0, [X17, X20]

  (89) 0x406d60 STR	D0, [X16], #8

  (89) 0x406d64 SUB	X18, X13, X16

  (89) 0x406d68 LDR	D1, [X18, X20]

  (89) 0x406d6c STR	D1, [X16], #8

  (89) 0x406d70 SUB	X0, X13, X16

  (89) 0x406d74 LDR	D2, [X0, X20]

  (89) 0x406d78 STR	D2, [X16], #8

  (89) 0x406d7c SUB	X1, X13, X16

  (89) 0x406d80 LDR	D3, [X1, X20]

  (89) 0x406d84 STR	D3, [X16], #8

  (89) 0x406d88 SUB	X2, X13, X16

  (89) 0x406d8c LDR	D4, [X2, X20]

  (89) 0x406d90 STR	D4, [X16], #8

  (89) 0x406d94 SUB	X4, X13, X16

  (89) 0x406d98 LDR	D5, [X4, X20]

  (89) 0x406d9c STR	D5, [X16], #8

  (89) 0x406da0 CMP	X16, X8

  (89) 0x406da4 B.EQ	406e30

    (88) 0x406da8 SUB	X7, X13, X16

    (88) 0x406dac ORR	X14, XZR, X16

    (88) 0x406db0 ADD	X5, X16, #32

    (88) 0x406db4 ADD	X18, X16, #40

    (88) 0x406db8 LDR	D6, [X7, X20]

    (88) 0x406dbc SUB	X0, X13, X5

    (88) 0x406dc0 SUB	X1, X13, X18

    (88) 0x406dc4 ADD	X6, X16, #24

    (88) 0x406dc8 ADD	X3, X16, #48

    (88) 0x406dcc SUB	X17, X13, X6

    (88) 0x406dd0 SUB	X4, X13, X3

    (88) 0x406dd4 ADD	X2, X16, #56

    (88) 0x406dd8 ADD	X16, X16, #64

    (88) 0x406ddc SUB	X6, X13, X2

    (88) 0x406de0 STR	D6, [X14], #8

    (88) 0x406de4 SUB	X5, X13, X14

    (88) 0x406de8 ADD	X7, X14, #8

    (88) 0x406dec SUB	X18, X13, X7

    (88) 0x406df0 LDR	D7, [X5, X20]

    (88) 0x406df4 STUR	D7, [X16, #456]

    (88) 0x406df8 LDR	D16, [X18, X20]

    (88) 0x406dfc STR	D16, [X14, #8]

    (88) 0x406e00 LDR	D17, [X17, X20]

    (88) 0x406e04 STUR	D17, [X16, #472]

    (88) 0x406e08 LDR	D18, [X0, X20]

    (88) 0x406e0c STUR	D18, [X16, #480]

    (88) 0x406e10 LDR	D19, [X1, X20]

    (88) 0x406e14 STUR	D19, [X16, #488]

    (88) 0x406e18 LDR	D20, [X4, X20]

    (88) 0x406e1c STUR	D20, [X16, #496]

    (88) 0x406e20 LDR	D21, [X6, X20]

    (88) 0x406e24 STUR	D21, [X16, #504]

    (88) 0x406e28 CMP	X16, X8

    (88) 0x406e2c B.NE	406da8

  (89) 0x406e30 ADD	W30, W30, #1

  (89) 0x406e34 ADD	W10, W10, W15

  (89) 0x406e38 CMP	W11, W30

  (89) 0x406e3c B.GT	406ce0

(90) 0x406e40 LDP	X19, X20, [SP, #16]

(90) 0x406e44 LDP	X29, X30, [SP], #32

(90) 0x406e48 RET

(90) 0x406e4c ADD	W2, W2, #1

(90) 0x406e50 MOVZ	W4, #0

(90) 0x406e54 B	406ba8

0x406e58 HINT	#0

0x406e5c HINT	#0

Coverage (%)	Name	Source Location	Module
►98.99+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_8

Source file and lines	local_halos.cpp:25-30
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-118-5752/intel/TeaLeaf/build/TeaLeaf/src/omp/local_halos.cpp:25-30.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 53% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 12.50 to 3.12 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.50 to 1.00 cycles (12.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 8 bytes. The binary function is storing 32 bytes.

General properties

nb instructions	16
loop length	64
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.50	1.50	1.83	1.83	1.83	1.83	2.00	1.67	0.00	0.00	0.00	0.00	1.00	1.00	1.00	1.00	1.00
cycles	1.50	1.50	1.83	1.83	1.83	1.83	2.00	1.67	0.00	0.00	0.00	0.00	1.00	1.00	1.00	1.00	1.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	1.75
Overall L1	5.00-12.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.50 cycles. At this rate:

0% of peak load performance is reached (0.64 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (2.56 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 406b70

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #992]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 4016d0 <@plt_start@+0x100>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W19, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4016e0 <@plt_start@+0x110>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W9, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDP W0, W3, [X20, #12]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
SUB W1, W0, W3,LSL #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SDIV W2, W1, W19	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	scal (25.0%)
MSUB W4, W2, W19, W1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
CMP W9, W4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.LT 406e4c <_Z12update_rightiiiiPdb._omp_fn.0+0x2dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_8

Source file and lines	local_halos.cpp:25-30
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-118-5752/intel/TeaLeaf/build/TeaLeaf/src/omp/local_halos.cpp:25-30.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.50 to 1.00 cycles (12.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 8 bytes. The binary function is storing 32 bytes.

General properties

nb instructions	16
loop length	64
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.50	1.50	1.83	1.83	1.83	1.83	2.00	1.67	0.00	0.00	0.00	0.00	1.00	1.00	1.00	1.00	1.00
cycles	1.50	1.50	1.83	1.83	1.83	1.83	2.00	1.67	0.00	0.00	0.00	0.00	1.00	1.00	1.00	1.00	1.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	1.75
Overall L1	5.00-12.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.50 cycles. At this rate:

0% of peak load performance is reached (0.64 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (2.56 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 406b70

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #992]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 4016d0 <@plt_start@+0x100>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W19, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4016e0 <@plt_start@+0x110>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W9, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDP W0, W3, [X20, #12]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
SUB W1, W0, W3,LSL #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SDIV W2, W1, W19	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	scal (25.0%)
MSUB W4, W2, W19, W1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
CMP W9, W4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.LT 406e4c <_Z12update_rightiiiiPdb._omp_fn.0+0x2dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A

Name	Coverage (%)	Time (s)
▼update_right(int, int, int, int, double*, bool) [clone ._omp_fn.0]–	0.02	0.04
▼Loop 90 - local_halos.cpp:25-30 - exec–	0.00	0.00
▼Loop 89 - local_halos.cpp:25-30 - exec–	0.02	0.03
○Loop 88 - local_halos.cpp:28-30 - exec	0.00	0.00
○Loop 91 - local_halos.cpp:28-28 - exec	0.00	0.00

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Vectorization

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Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

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ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code