OV - exec - Function update_left(int, int, int, int, double*, bool) [clone ._omp

	Function: update_left(int, int, int, int, double*, bool) [clone ._omp_fn.0]	Module: exec	Source: local_halos.cpp:10-15	Coverage (incl. loops): 0.03% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-118-5752/intel/TeaLeaf/build/TeaLeaf/src/omp/local_halos.cpp: 10 - 15

--------------------------------------------------------------------------------

10:   #pragma omp parallel for

11: #endif

12:   for (int jj = halo_depth; jj < y - halo_depth; ++jj) {

13:     for (int kk = 0; kk < depth; ++kk) {

14:       int base = jj * x;

15:       buffer[base + (halo_depth - kk - 1)] = buffer[base + (halo_depth + kk)];

0x406880 STP	X29, X30, [SP, #992]!

0x406884 ADD	X29, SP, #0

0x406888 STP	X19, X20, [SP, #16]

0x40688c ORR	X20, XZR, X0

0x406890 BL	4016d0

0x406894 ORR	W19, WZR, W0

0x406898 BL	4016e0

0x40689c ORR	W10, WZR, W0

0x4068a0 LDP	W0, W14, [X20, #12]

0x4068a4 SUB	W1, W0, W14,LSL #1

0x4068a8 SDIV	W2, W1, W19

0x4068ac MSUB	W3, W2, W19, W1

0x4068b0 CMP	W10, W3

0x4068b4 B.LT	406b64

(86) 0x4068b8 MADD	W4, W2, W10, W3

(86) 0x4068bc ADD	W5, W2, W4

(86) 0x4068c0 CMP	W4, W5

(86) 0x4068c4 B.GE	4069cc

(86) 0x4068c8 LDR	X13, [X20]

(86) 0x4068cc ADD	W30, W14, W4

(86) 0x4068d0 ADD	W12, W14, W5

(86) 0x4068d4 ORN	W6, WZR, W30

(86) 0x4068d8 LDR	W16, [X20, #8]

(86) 0x4068dc ADD	W7, W6, W12

(86) 0x4068e0 AND	W8, W7, #128

(86) 0x4068e4 LDR	W15, [X20, #20]

(86) 0x4068e8 UBFM	X9, X13, #63, #62

(86) 0x4068ec MADD	W11, W30, W16, WZR

(86) 0x4068f0 CMP	W15, #0

(86) 0x4068f4 B.GT	4069d8

(86) 0x4068f8 ADD	W30, W30, #1

(86) 0x4068fc ADD	W11, W11, W16

(86) 0x406900 CMP	W12, W30

(86) 0x406904 B.LE	4069cc

(86) 0x406908 CBZ	W8, 4069b4

(86) 0x40690c CMP	W8, #1

(86) 0x406910 B.EQ	40699c

(86) 0x406914 CMP	W8, #2

(86) 0x406918 B.EQ	40698c

(86) 0x40691c CMP	W8, #3

(86) 0x406920 B.EQ	40697c

(86) 0x406924 CMP	W8, #4

(86) 0x406928 B.EQ	40696c

(86) 0x40692c CMP	W8, #5

(86) 0x406930 B.EQ	40695c

(86) 0x406934 CMP	W8, #6

(86) 0x406938 B.EQ	40694c

(86) 0x40693c CMP	W15, #0

(86) 0x406940 B.GT	4069d8

(86) 0x406944 ADD	W30, W30, #1

(86) 0x406948 ADD	W11, W11, W16

(86) 0x40694c CMP	W15, #0

(86) 0x406950 B.GT	4069d8

(86) 0x406954 ADD	W30, W30, #1

(86) 0x406958 ADD	W11, W11, W16

(86) 0x40695c CMP	W15, #0

(86) 0x406960 B.GT	4069d8

(86) 0x406964 ADD	W30, W30, #1

(86) 0x406968 ADD	W11, W11, W16

(86) 0x40696c CMP	W15, #0

(86) 0x406970 B.GT	4069d8

(86) 0x406974 ADD	W30, W30, #1

(86) 0x406978 ADD	W11, W11, W16

(86) 0x40697c CMP	W15, #0

(86) 0x406980 B.GT	4069d8

(86) 0x406984 ADD	W30, W30, #1

(86) 0x406988 ADD	W11, W11, W16

(86) 0x40698c CMP	W15, #0

(86) 0x406990 B.GT	4069d8

(86) 0x406994 ADD	W30, W30, #1

(86) 0x406998 ADD	W11, W11, W16

(86) 0x40699c CMP	W15, #0

(86) 0x4069a0 B.GT	4069d8

(86) 0x4069a4 ADD	W30, W30, #1

(86) 0x4069a8 ADD	W11, W11, W16

(86) 0x4069ac CMP	W12, W30

(86) 0x4069b0 B.LE	4069cc

  (87) 0x4069b4 CMP	W15, #0

  (87) 0x4069b8 B.GT	4069d8

  (87) 0x4069bc ADD	W30, W30, #8

  (87) 0x4069c0 ADD	W11, W11, W16,LSL #3

  (87) 0x4069c4 CMP	W12, W30

  (87) 0x4069c8 B.GT	4069b4

(86) 0x4069cc LDP	X19, X20, [SP, #16]

(86) 0x4069d0 LDP	X29, X30, [SP], #32

(86) 0x4069d4 RET

(86) 0x4069d8 SBFM	X20, X14, #0, #31

(86) 0x4069dc ADD	X19, X20, W15,SXTW

  (85) 0x4069e0 SBFM	X17, X11, #0, #31

  (85) 0x4069e4 ADD	X10, X17, X20

  (85) 0x4069e8 ADD	X18, X19, X17

  (85) 0x4069ec ADD	X14, X13, X18,LSL #3

  (85) 0x4069f0 UBFM	X1, X10, #60, #59

  (85) 0x4069f4 UBFM	X2, X10, #61, #60

  (85) 0x4069f8 ADD	X0, X13, X10,LSL #3

  (85) 0x4069fc SUB	X15, X1, #8

  (85) 0x406a00 SUB	X3, X14, X0

  (85) 0x406a04 SUB	X4, X3, #8

  (85) 0x406a08 UBFM	X5, X4, #3, #63

  (85) 0x406a0c ADD	X6, X5, #1

  (85) 0x406a10 ANDS	X7, X6, #4224

  (85) 0x406a14 B.EQ	406ac0

  (85) 0x406a18 CMP	X7, #1

  (85) 0x406a1c B.EQ	406aa8

  (85) 0x406a20 CMP	X7, #2

  (85) 0x406a24 B.EQ	406a98

  (85) 0x406a28 CMP	X7, #3

  (85) 0x406a2c B.EQ	406a88

  (85) 0x406a30 CMP	X7, #4

  (85) 0x406a34 B.EQ	406a78

  (85) 0x406a38 CMP	X7, #5

  (85) 0x406a3c B.EQ	406a68

  (85) 0x406a40 CMP	X7, #6

  (85) 0x406a44 B.EQ	406a58

  (85) 0x406a48 LDR	D31, [X13, X2]

  (85) 0x406a4c SUB	X8, X15, X0

  (85) 0x406a50 ADD	X0, X0, #8

  (85) 0x406a54 STR	D31, [X8, X9]

  (85) 0x406a58 LDR	D0, [X0]

  (85) 0x406a5c SUB	X17, X15, X0

  (85) 0x406a60 ADD	X0, X0, #8

  (85) 0x406a64 STR	D0, [X17, X9]

  (85) 0x406a68 LDR	D1, [X0]

  (85) 0x406a6c SUB	X10, X15, X0

  (85) 0x406a70 ADD	X0, X0, #8

  (85) 0x406a74 STR	D1, [X10, X9]

  (85) 0x406a78 LDR	D2, [X0]

  (85) 0x406a7c SUB	X18, X15, X0

  (85) 0x406a80 ADD	X0, X0, #8

  (85) 0x406a84 STR	D2, [X18, X9]

  (85) 0x406a88 LDR	D3, [X0]

  (85) 0x406a8c SUB	X1, X15, X0

  (85) 0x406a90 ADD	X0, X0, #8

  (85) 0x406a94 STR	D3, [X1, X9]

  (85) 0x406a98 LDR	D4, [X0]

  (85) 0x406a9c SUB	X2, X15, X0

  (85) 0x406aa0 ADD	X0, X0, #8

  (85) 0x406aa4 STR	D4, [X2, X9]

  (85) 0x406aa8 LDR	D5, [X0]

  (85) 0x406aac SUB	X3, X15, X0

  (85) 0x406ab0 ADD	X0, X0, #8

  (85) 0x406ab4 STR	D5, [X3, X9]

  (85) 0x406ab8 CMP	X0, X14

  (85) 0x406abc B.EQ	406b48

    (84) 0x406ac0 LDR	D6, [X0]

    (84) 0x406ac4 SUB	X17, X15, X0

    (84) 0x406ac8 ADD	X4, X0, #8

    (84) 0x406acc SUB	X8, X15, X4

    (84) 0x406ad0 ADD	X5, X0, #16

    (84) 0x406ad4 SUB	X7, X15, X5

    (84) 0x406ad8 ADD	X6, X0, #24

    (84) 0x406adc SUB	X10, X15, X6

    (84) 0x406ae0 ADD	X18, X0, #32

    (84) 0x406ae4 SUB	X1, X15, X18

    (84) 0x406ae8 ADD	X2, X0, #40

    (84) 0x406aec SUB	X4, X15, X2

    (84) 0x406af0 ADD	X3, X0, #48

    (84) 0x406af4 STR	D6, [X17, X9]

    (84) 0x406af8 SUB	X5, X15, X3

    (84) 0x406afc ADD	X17, X0, #56

    (84) 0x406b00 LDR	D7, [X0, #8]

    (84) 0x406b04 SUB	X6, X15, X17

    (84) 0x406b08 ADD	X0, X0, #64

    (84) 0x406b0c STR	D7, [X8, X9]

    (84) 0x406b10 LDUR	D16, [X0, #464]

    (84) 0x406b14 STR	D16, [X7, X9]

    (84) 0x406b18 LDUR	D17, [X0, #472]

    (84) 0x406b1c STR	D17, [X10, X9]

    (84) 0x406b20 LDUR	D18, [X0, #480]

    (84) 0x406b24 STR	D18, [X1, X9]

    (84) 0x406b28 LDUR	D19, [X0, #488]

    (84) 0x406b2c STR	D19, [X4, X9]

    (84) 0x406b30 LDUR	D20, [X0, #496]

    (84) 0x406b34 STR	D20, [X5, X9]

    (84) 0x406b38 LDUR	D21, [X0, #504]

    (84) 0x406b3c STR	D21, [X6, X9]

    (84) 0x406b40 CMP	X0, X14

    (84) 0x406b44 B.NE	406ac0

  (85) 0x406b48 ADD	W30, W30, #1

  (85) 0x406b4c ADD	W11, W11, W16

  (85) 0x406b50 CMP	W12, W30

  (85) 0x406b54 B.GT	4069e0

(86) 0x406b58 LDP	X19, X20, [SP, #16]

(86) 0x406b5c LDP	X29, X30, [SP], #32

(86) 0x406b60 RET

(86) 0x406b64 ADD	W2, W2, #1

(86) 0x406b68 MOVZ	W3, #0

(86) 0x406b6c B	4068b8

Coverage (%)	Name	Source Location	Module
►98.88+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_8

Source file and lines	local_halos.cpp:10-15
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-118-5752/intel/TeaLeaf/build/TeaLeaf/src/omp/local_halos.cpp:10-15.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 53% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 12.50 to 3.12 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.50 to 1.00 cycles (12.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 8 bytes. The binary function is storing 32 bytes.

General properties

nb instructions	14
loop length	56
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.50	1.50	1.83	1.83	1.83	1.83	2.00	1.67	0.00	0.00	0.00	0.00	1.00	1.00	1.00	1.00	1.00
cycles	1.50	1.50	1.83	1.83	1.83	1.83	2.00	1.67	0.00	0.00	0.00	0.00	1.00	1.00	1.00	1.00	1.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	1.75
Overall L1	5.00-12.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.50 cycles. At this rate:

0% of peak load performance is reached (0.64 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (2.56 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 406880

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #992]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
BL 4016d0 <@plt_start@+0x100>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W19, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4016e0 <@plt_start@+0x110>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W10, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDP W0, W14, [X20, #12]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
SUB W1, W0, W14,LSL #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
SDIV W2, W1, W19	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5-12	5-12.50	scal (25.0%)
MSUB W3, W2, W19, W1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
CMP W10, W3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.LT 406b64 <_Z11update_leftiiiiPdb._omp_fn.0+0x2e4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_8

Source file and lines	local_halos.cpp:10-15
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-118-5752/intel/TeaLeaf/build/TeaLeaf/src/omp/local_halos.cpp:10-15.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.50 to 1.00 cycles (12.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 8 bytes. The binary function is storing 32 bytes.

General properties

nb instructions	14
loop length	56
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.50	1.50	1.83	1.83	1.83	1.83	2.00	1.67	0.00	0.00	0.00	0.00	1.00	1.00	1.00	1.00	1.00
cycles	1.50	1.50	1.83	1.83	1.83	1.83	2.00	1.67	0.00	0.00	0.00	0.00	1.00	1.00	1.00	1.00	1.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	1.75
Overall L1	5.00-12.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.50 cycles. At this rate:

0% of peak load performance is reached (0.64 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (2.56 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 406880

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #992]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
BL 4016d0 <@plt_start@+0x100>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W19, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4016e0 <@plt_start@+0x110>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W10, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDP W0, W14, [X20, #12]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
SUB W1, W0, W14,LSL #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
SDIV W2, W1, W19	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5-12	5-12.50	scal (25.0%)
MSUB W3, W2, W19, W1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
CMP W10, W3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.LT 406b64 <_Z11update_leftiiiiPdb._omp_fn.0+0x2e4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼update_left(int, int, int, int, double*, bool) [clone ._omp_fn.0]–	0.03	0.05
▼Loop 86 - local_halos.cpp:10-15 - exec–	0.00	0.01
▼Loop 85 - local_halos.cpp:10-15 - exec–	0.03	0.05
○Loop 84 - local_halos.cpp:13-15 - exec	0.00	0.00
○Loop 87 - local_halos.cpp:13-13 - exec	0.00	0.00

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Vectorization

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Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

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ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code