OV - exec - Function cg_calc_p(int, int, int, double, double*, double const*) [clone ._omp

	Function: cg_calc_p(int, int, int, double, double, double const) [clone ._omp_fn.0]	Module: exec	Source: cg.cpp:125-131	Coverage (incl. loops): 16.73% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-118-5752/intel/TeaLeaf/build/TeaLeaf/src/omp/cg.cpp: 125 - 131

--------------------------------------------------------------------------------

125:   #pragma omp parallel for

126: #endif

127:   for (int jj = halo_depth; jj < y - halo_depth; ++jj) {

128:     for (int kk = halo_depth; kk < x - halo_depth; ++kk) {

129:       const int index = kk + jj * x;

130:

131:       p[index] = beta * p[index] + r[index];

0x4031c0 STP	X29, X30, [SP, #992]!

0x4031c4 ADD	X29, SP, #0

0x4031c8 STP	X19, X20, [SP, #16]

0x4031cc ORR	X20, XZR, X0

0x4031d0 BL	4016d0

0x4031d4 ORR	W19, WZR, W0

0x4031d8 BL	4016e0

0x4031dc ORR	W5, WZR, W0

0x4031e0 LDP	W0, W14, [X20, #28]

0x4031e4 SUB	W2, W0, W14,LSL #1

0x4031e8 SDIV	W1, W2, W19

0x4031ec MSUB	W3, W1, W19, W2

0x4031f0 CMP	W5, W3

0x4031f4 B.LT	4033ec

(28) 0x4031f8 MADD	W4, W1, W5, W3

(28) 0x4031fc ADD	W6, W1, W4

(28) 0x403200 CMP	W4, W6

(28) 0x403204 B.GE	4033e0

(28) 0x403208 LDR	W15, [X20, #24]

(28) 0x40320c ADD	W5, W14, W4

(28) 0x403210 SBFM	X18, X14, #0, #31

(28) 0x403214 LDP	X30, X19, [X20, #8]

(28) 0x403218 ADD	W13, W14, W6

(28) 0x40321c LDR	D31, [X20]

(28) 0x403220 SUB	W16, W15, W14,LSL #1

(28) 0x403224 SUB	W17, W15, W14

(28) 0x403228 MADD	W12, W5, W15, WZR

(28) 0x40322c ADD	X1, X16, X18

  (29) 0x403230 CMP	W14, W17

  (29) 0x403234 B.GE	4033d0

  (29) 0x403238 SBFM	X7, X12, #0, #31

  (29) 0x40323c ADD	X8, X1, X7

  (29) 0x403240 ADD	X9, X7, X18

  (29) 0x403244 UBFM	X20, X8, #61, #60

  (29) 0x403248 UBFM	X0, X9, #61, #60

  (29) 0x40324c SUB	X10, X20, X9,LSL #3

  (29) 0x403250 SUB	X11, X10, #8

  (29) 0x403254 UBFM	X2, X11, #3, #63

  (29) 0x403258 ADD	X3, X2, #1

  (29) 0x40325c ANDS	X4, X3, #4224

  (29) 0x403260 B.EQ	403328

  (29) 0x403264 CMP	X4, #1

  (29) 0x403268 B.EQ	40330c

  (29) 0x40326c CMP	X4, #2

  (29) 0x403270 B.EQ	4032f8

  (29) 0x403274 CMP	X4, #3

  (29) 0x403278 B.EQ	4032e4

  (29) 0x40327c CMP	X4, #4

  (29) 0x403280 B.EQ	4032d0

  (29) 0x403284 CMP	X4, #5

  (29) 0x403288 B.EQ	4032bc

  (29) 0x40328c CMP	X4, #6

  (29) 0x403290 B.EQ	4032a8

  (29) 0x403294 LDR	D4, [X30, X0]

  (29) 0x403298 LDR	D3, [X19, X0]

  (29) 0x40329c FMADD	D0, D31, D4, D3

  (29) 0x4032a0 STR	D0, [X30, X0]

  (29) 0x4032a4 ADD	X0, X0, #8

  (29) 0x4032a8 LDR	D2, [X30, X0]

  (29) 0x4032ac LDR	D1, [X19, X0]

  (29) 0x4032b0 FMADD	D5, D31, D2, D1

  (29) 0x4032b4 STR	D5, [X30, X0]

  (29) 0x4032b8 ADD	X0, X0, #8

  (29) 0x4032bc LDR	D6, [X30, X0]

  (29) 0x4032c0 LDR	D29, [X19, X0]

  (29) 0x4032c4 FMADD	D7, D31, D6, D29

  (29) 0x4032c8 STR	D7, [X30, X0]

  (29) 0x4032cc ADD	X0, X0, #8

  (29) 0x4032d0 LDR	D30, [X30, X0]

  (29) 0x4032d4 LDR	D28, [X19, X0]

  (29) 0x4032d8 FMADD	D16, D31, D30, D28

  (29) 0x4032dc STR	D16, [X30, X0]

  (29) 0x4032e0 ADD	X0, X0, #8

  (29) 0x4032e4 LDR	D27, [X30, X0]

  (29) 0x4032e8 LDR	D26, [X19, X0]

  (29) 0x4032ec FMADD	D17, D31, D27, D26

  (29) 0x4032f0 STR	D17, [X30, X0]

  (29) 0x4032f4 ADD	X0, X0, #8

  (29) 0x4032f8 LDR	D25, [X30, X0]

  (29) 0x4032fc LDR	D24, [X19, X0]

  (29) 0x403300 FMADD	D18, D31, D25, D24

  (29) 0x403304 STR	D18, [X30, X0]

  (29) 0x403308 ADD	X0, X0, #8

  (29) 0x40330c LDR	D23, [X30, X0]

  (29) 0x403310 LDR	D22, [X19, X0]

  (29) 0x403314 FMADD	D19, D31, D23, D22

  (29) 0x403318 STR	D19, [X30, X0]

  (29) 0x40331c ADD	X0, X0, #8

  (29) 0x403320 CMP	X20, X0

  (29) 0x403324 B.EQ	4033d0

    (30) 0x403328 LDR	D21, [X30, X0]

    (30) 0x40332c ADD	X16, X0, #8

    (30) 0x403330 ADD	X11, X0, #16

    (30) 0x403334 ADD	X10, X0, #24

    (30) 0x403338 ADD	X9, X0, #32

    (30) 0x40333c LDR	D20, [X19, X0]

    (30) 0x403340 ADD	X8, X0, #40

    (30) 0x403344 ADD	X7, X0, #48

    (30) 0x403348 ADD	X6, X0, #56

    (30) 0x40334c FMADD	D4, D31, D21, D20

    (30) 0x403350 STR	D4, [X30, X0]

    (30) 0x403354 ADD	X0, X0, #64

    (30) 0x403358 LDR	D3, [X30, X16]

    (30) 0x40335c LDR	D0, [X19, X16]

    (30) 0x403360 FMADD	D2, D31, D3, D0

    (30) 0x403364 STR	D2, [X30, X16]

    (30) 0x403368 LDR	D1, [X30, X11]

    (30) 0x40336c LDR	D5, [X19, X11]

    (30) 0x403370 FMADD	D6, D31, D1, D5

    (30) 0x403374 STR	D6, [X30, X11]

    (30) 0x403378 LDR	D29, [X30, X10]

    (30) 0x40337c LDR	D7, [X19, X10]

    (30) 0x403380 FMADD	D30, D31, D29, D7

    (30) 0x403384 STR	D30, [X30, X10]

    (30) 0x403388 LDR	D28, [X30, X9]

    (30) 0x40338c LDR	D16, [X19, X9]

    (30) 0x403390 FMADD	D27, D31, D28, D16

    (30) 0x403394 STR	D27, [X30, X9]

    (30) 0x403398 LDR	D26, [X30, X8]

    (30) 0x40339c LDR	D17, [X19, X8]

    (30) 0x4033a0 FMADD	D25, D31, D26, D17

    (30) 0x4033a4 STR	D25, [X30, X8]

    (30) 0x4033a8 LDR	D24, [X30, X7]

    (30) 0x4033ac LDR	D18, [X19, X7]

    (30) 0x4033b0 FMADD	D23, D31, D24, D18

    (30) 0x4033b4 STR	D23, [X30, X7]

    (30) 0x4033b8 LDR	D22, [X30, X6]

    (30) 0x4033bc LDR	D19, [X19, X6]

    (30) 0x4033c0 FMADD	D21, D31, D22, D19

    (30) 0x4033c4 STR	D21, [X30, X6]

    (30) 0x4033c8 CMP	X20, X0

    (30) 0x4033cc B.NE	403328

  (29) 0x4033d0 ADD	W5, W5, #1

  (29) 0x4033d4 ADD	W12, W12, W15

  (29) 0x4033d8 CMP	W13, W5

  (29) 0x4033dc B.GT	403230

(28) 0x4033e0 LDP	X19, X20, [SP, #16]

(28) 0x4033e4 LDP	X29, X30, [SP], #32

(28) 0x4033e8 RET

(28) 0x4033ec ADD	W1, W1, #1

(28) 0x4033f0 MOVZ	W3, #0

(28) 0x4033f4 B	4031f8

0x4033f8 HINT	#0

0x4033fc HINT	#0

Coverage (%)	Name	Source Location	Module
►98.96+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.04+	GOMP_parallel	libgomp.h:980	libgomp.so.1.0.0
○	run_cg_calc_p(Chunk*, Settings[...]	cg.cpp:159	exec
○	cg_main_step_driver(Chunk*, Se[...]	cg_driver.cpp:88	exec
○	cg_driver(Chunk*, Settings&, d[...]	cg_driver.cpp:18	exec
○	solve(Chunk*, Settings&, int, [...]	diffuse.cpp:51	exec
○	diffuse(Chunk*, Settings&)	diffuse.cpp:12	exec
○	main	main.cpp:179	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	basic_string.h:809	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_8

Source file and lines	cg.cpp:125-131
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-118-5752/intel/TeaLeaf/build/TeaLeaf/src/omp/cg.cpp:125-131.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 53% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 12.50 to 3.12 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.50 to 1.00 cycles (12.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 8 bytes. The binary function is storing 32 bytes.

General properties

nb instructions	16
loop length	64
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.50	1.50	1.83	1.83	1.83	1.83	2.00	1.67	0.00	0.00	0.00	0.00	1.00	1.00	1.00	1.00	1.00
cycles	1.50	1.50	1.83	1.83	1.83	1.83	2.00	1.67	0.00	0.00	0.00	0.00	1.00	1.00	1.00	1.00	1.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	1.75
Overall L1	5.00-12.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.50 cycles. At this rate:

0% of peak load performance is reached (0.64 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (2.56 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4031c0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #992]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 4016d0 <@plt_start@+0x100>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W19, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4016e0 <@plt_start@+0x110>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W5, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDP W0, W14, [X20, #28]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
SUB W2, W0, W14,LSL #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SDIV W1, W2, W19	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	scal (25.0%)
MSUB W3, W1, W19, W2	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
CMP W5, W3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.LT 4033ec <_Z9cg_calc_piiidPdPKd._omp_fn.0+0x22c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_8

Source file and lines	cg.cpp:125-131
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-118-5752/intel/TeaLeaf/build/TeaLeaf/src/omp/cg.cpp:125-131.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.50 to 1.00 cycles (12.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 8 bytes. The binary function is storing 32 bytes.

General properties

nb instructions	16
loop length	64
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.50	1.50	1.83	1.83	1.83	1.83	2.00	1.67	0.00	0.00	0.00	0.00	1.00	1.00	1.00	1.00	1.00
cycles	1.50	1.50	1.83	1.83	1.83	1.83	2.00	1.67	0.00	0.00	0.00	0.00	1.00	1.00	1.00	1.00	1.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	1.75
Overall L1	5.00-12.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.50 cycles. At this rate:

0% of peak load performance is reached (0.64 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (2.56 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4031c0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #992]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 4016d0 <@plt_start@+0x100>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W19, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4016e0 <@plt_start@+0x110>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W5, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDP W0, W14, [X20, #28]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
SUB W2, W0, W14,LSL #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SDIV W1, W2, W19	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	scal (25.0%)
MSUB W3, W1, W19, W2	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
CMP W5, W3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.LT 4033ec <_Z9cg_calc_piiidPdPKd._omp_fn.0+0x22c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A

Name	Coverage (%)	Time (s)
▼cg_calc_p(int, int, int, double, double, double const) [clone ._omp_fn.0]–	16.73	26.87
▼Loop 28 - cg.cpp:125-131 - exec–	0.01	0.01
▼Loop 29 - cg.cpp:128-131 - exec–	0.00	0.01
○Loop 30 - cg.cpp:128-131 - exec	16.72	26.55

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code