OV - exec - Function cg_calc_ur(int, int, int, double, double*, double*, double const*, double*, double const*) [clone ._omp

	Function: cg_calc_ur(int, int, int, double, double, double, double const, double, double const*) ...	Module: exec	Source: cg.cpp:105-113	Coverage (incl. loops): 38.60% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-118-5752/intel/TeaLeaf/build/TeaLeaf/src/omp/cg.cpp: 105 - 113

--------------------------------------------------------------------------------

105:   #pragma omp parallel for reduction(+ : rrn_temp)

106: #endif

107:   for (int jj = halo_depth; jj < y - halo_depth; ++jj) {

108:     for (int kk = halo_depth; kk < x - halo_depth; ++kk) {

109:       const int index = kk + jj * x;

110:

111:       u[index] += alpha * p[index];

112:       r[index] -= alpha * w[index];

113:       rrn_temp += r[index] * r[index];

0x402f80 STP	X29, X30, [SP, #992]!

0x402f84 ADD	X29, SP, #0

0x402f88 STP	X19, X20, [SP, #16]

0x402f8c ORR	X19, XZR, X0

0x402f90 BL	4016d0

0x402f94 ORR	W20, WZR, W0

0x402f98 BL	4016e0

0x402f9c ORR	W10, WZR, W0

0x402fa0 LDP	W0, W12, [X19, #52]

0x402fa4 SUB	W2, W0, W12,LSL #1

0x402fa8 SDIV	W1, W2, W20

0x402fac MSUB	W3, W1, W20, W2

0x402fb0 CMP	W10, W3

0x402fb4 B.LT	4031ac

(25) 0x402fb8 MADD	W4, W1, W10, W3

(25) 0x402fbc MOVI	D31, #0

(25) 0x402fc0 ADD	W5, W1, W4

(25) 0x402fc4 CMP	W4, W5

(25) 0x402fc8 B.GE	40317c

(25) 0x402fcc LDR	W13, [X19, #48]

(25) 0x402fd0 ADD	W10, W12, W4

(25) 0x402fd4 SBFM	X16, X12, #0, #31

(25) 0x402fd8 LDP	X18, X8, [X19, #8]

(25) 0x402fdc ADD	W17, W12, W5

(25) 0x402fe0 LDP	X30, X7, [X19, #24]

(25) 0x402fe4 SUB	W14, W13, W12,LSL #1

(25) 0x402fe8 SUB	W15, W13, W12

(25) 0x402fec MADD	W11, W10, W13, WZR

(25) 0x402ff0 ADD	X20, X14, X16

(25) 0x402ff4 LDR	D30, [X19]

(25) 0x402ff8 HINT	#0

(25) 0x402ffc HINT	#0

  (26) 0x403000 CMP	W12, W15

  (26) 0x403004 B.GE	40316c

  (26) 0x403008 SBFM	X6, X11, #0, #31

  (26) 0x40300c ADD	X9, X20, X6

  (26) 0x403010 ADD	X0, X6, X16

  (26) 0x403014 UBFM	X2, X9, #61, #60

  (26) 0x403018 UBFM	X1, X0, #61, #60

  (26) 0x40301c SUB	X3, X2, X0,LSL #3

  (26) 0x403020 SUB	X4, X3, #8

  (26) 0x403024 UBFM	X5, X4, #3, #63

  (26) 0x403028 ADD	X14, X5, #1

  (26) 0x40302c ANDS	X6, X14, #4160

  (26) 0x403030 B.EQ	4030c4

  (26) 0x403034 CMP	X6, #1

  (26) 0x403038 B.EQ	403094

  (26) 0x40303c CMP	X6, #2

  (26) 0x403040 B.EQ	40306c

  (26) 0x403044 LDR	D28, [X8, X1]

  (26) 0x403048 LDR	D29, [X18, X1]

  (26) 0x40304c FMADD	D0, D30, D28, D29

  (26) 0x403050 STR	D0, [X18, X1]

  (26) 0x403054 LDR	D1, [X7, X1]

  (26) 0x403058 LDR	D2, [X30, X1]

  (26) 0x40305c FMSUB	D3, D30, D1, D2

  (26) 0x403060 FMADD	D31, D3, D3, D31

  (26) 0x403064 STR	D3, [X30, X1]

  (26) 0x403068 ADD	X1, X1, #8

  (26) 0x40306c LDR	D4, [X8, X1]

  (26) 0x403070 LDR	D5, [X18, X1]

  (26) 0x403074 FMADD	D6, D30, D4, D5

  (26) 0x403078 STR	D6, [X18, X1]

  (26) 0x40307c LDR	D7, [X7, X1]

  (26) 0x403080 LDR	D16, [X30, X1]

  (26) 0x403084 FMSUB	D17, D30, D7, D16

  (26) 0x403088 FMADD	D31, D17, D17, D31

  (26) 0x40308c STR	D17, [X30, X1]

  (26) 0x403090 ADD	X1, X1, #8

  (26) 0x403094 LDR	D18, [X8, X1]

  (26) 0x403098 LDR	D19, [X18, X1]

  (26) 0x40309c FMADD	D20, D30, D18, D19

  (26) 0x4030a0 STR	D20, [X18, X1]

  (26) 0x4030a4 LDR	D21, [X7, X1]

  (26) 0x4030a8 LDR	D22, [X30, X1]

  (26) 0x4030ac FMSUB	D23, D30, D21, D22

  (26) 0x4030b0 FMADD	D31, D23, D23, D31

  (26) 0x4030b4 STR	D23, [X30, X1]

  (26) 0x4030b8 ADD	X1, X1, #8

  (26) 0x4030bc CMP	X2, X1

  (26) 0x4030c0 B.EQ	40316c

    (27) 0x4030c4 LDR	D24, [X8, X1]

    (27) 0x4030c8 ADD	X9, X1, #8

    (27) 0x4030cc ADD	X3, X1, #16

    (27) 0x4030d0 ADD	X0, X1, #24

    (27) 0x4030d4 LDR	D25, [X18, X1]

    (27) 0x4030d8 FMADD	D26, D30, D24, D25

    (27) 0x4030dc STR	D26, [X18, X1]

    (27) 0x4030e0 LDR	D27, [X7, X1]

    (27) 0x4030e4 LDR	D28, [X30, X1]

    (27) 0x4030e8 FMSUB	D29, D30, D27, D28

    (27) 0x4030ec FMADD	D0, D29, D29, D31

    (27) 0x4030f0 STR	D29, [X30, X1]

    (27) 0x4030f4 ADD	X1, X1, #32

    (27) 0x4030f8 LDR	D1, [X8, X9]

    (27) 0x4030fc LDR	D2, [X18, X9]

    (27) 0x403100 FMADD	D3, D30, D1, D2

    (27) 0x403104 STR	D3, [X18, X9]

    (27) 0x403108 LDR	D4, [X7, X9]

    (27) 0x40310c LDR	D5, [X30, X9]

    (27) 0x403110 FMSUB	D6, D30, D4, D5

    (27) 0x403114 FMADD	D7, D6, D6, D0

    (27) 0x403118 STR	D6, [X30, X9]

    (27) 0x40311c LDR	D16, [X8, X3]

    (27) 0x403120 LDR	D17, [X18, X3]

    (27) 0x403124 FMADD	D18, D30, D16, D17

    (27) 0x403128 STR	D18, [X18, X3]

    (27) 0x40312c LDR	D19, [X7, X3]

    (27) 0x403130 LDR	D20, [X30, X3]

    (27) 0x403134 FMSUB	D21, D30, D19, D20

    (27) 0x403138 FMADD	D22, D21, D21, D7

    (27) 0x40313c STR	D21, [X30, X3]

    (27) 0x403140 LDR	D31, [X18, X0]

    (27) 0x403144 LDR	D23, [X8, X0]

    (27) 0x403148 FMADD	D24, D30, D23, D31

    (27) 0x40314c STR	D24, [X18, X0]

    (27) 0x403150 LDR	D25, [X7, X0]

    (27) 0x403154 LDR	D26, [X30, X0]

    (27) 0x403158 FMSUB	D27, D30, D25, D26

    (27) 0x40315c FMADD	D31, D27, D27, D22

    (27) 0x403160 STR	D27, [X30, X0]

    (27) 0x403164 CMP	X2, X1

    (27) 0x403168 B.NE	4030c4

  (26) 0x40316c ADD	W10, W10, #1

  (26) 0x403170 ADD	W11, W11, W13

  (26) 0x403174 CMP	W17, W10

  (26) 0x403178 B.GT	403000

(25) 0x40317c ADD	X19, X19, #40

(25) 0x403180 LDR	X1, [X19]

  (24) 0x403184 FMOV	D30, X1

  (24) 0x403188 ORR	X12, XZR, X1

  (24) 0x40318c FADD	D28, D31, D30

  (24) 0x403190 FMOV	X16, D28

  (24) 0x403194 CAS	X12, X16, [X19]

  (24) 0x403198 CMP	X1, X12

  (24) 0x40319c B.NE	4031b8

(25) 0x4031a0 LDP	X19, X20, [SP, #16]

(25) 0x4031a4 LDP	X29, X30, [SP], #32

(25) 0x4031a8 RET

(25) 0x4031ac ADD	W1, W1, #1

(25) 0x4031b0 MOVZ	W3, #0

(25) 0x4031b4 B	402fb8

  (24) 0x4031b8 ORR	X1, XZR, X12

  (24) 0x4031bc B	403184

Coverage (%)	Name	Source Location	Module
►98.90+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.10+	GOMP_parallel	libgomp.h:980	libgomp.so.1.0.0
○	run_cg_calc_ur(Chunk*, Setting[...]	cg.cpp:105	exec
○	cg_main_step_driver(Chunk*, Se[...]	cg_driver.cpp:74	exec
○	cg_driver(Chunk*, Settings&, d[...]	cg_driver.cpp:18	exec
○	solve(Chunk*, Settings&, int, [...]	diffuse.cpp:51	exec
○	diffuse(Chunk*, Settings&)	diffuse.cpp:12	exec
○	main	main.cpp:179	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	basic_string.h:809	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_8

Source file and lines	cg.cpp:105-113
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-118-5752/intel/TeaLeaf/build/TeaLeaf/src/omp/cg.cpp:105-113.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 53% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 12.50 to 3.12 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.50 to 1.00 cycles (12.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 8 bytes. The binary function is storing 32 bytes.

General properties

nb instructions	14
loop length	56
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.50	1.50	1.83	1.83	1.83	1.83	2.00	1.67	0.00	0.00	0.00	0.00	1.00	1.00	1.00	1.00	1.00
cycles	1.50	1.50	1.83	1.83	1.83	1.83	2.00	1.67	0.00	0.00	0.00	0.00	1.00	1.00	1.00	1.00	1.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	1.75
Overall L1	5.00-12.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.50 cycles. At this rate:

0% of peak load performance is reached (0.64 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (2.56 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 402f80

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #992]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X19, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
BL 4016d0 <@plt_start@+0x100>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W20, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4016e0 <@plt_start@+0x110>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W10, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDP W0, W12, [X19, #52]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
SUB W2, W0, W12,LSL #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
SDIV W1, W2, W20	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5-12	5-12.50	scal (25.0%)
MSUB W3, W1, W20, W2	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
CMP W10, W3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.LT 4031ac <_Z10cg_calc_uriiidPdS_PKdS_S1_._omp_fn.0+0x22c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_8

Source file and lines	cg.cpp:105-113
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-118-5752/intel/TeaLeaf/build/TeaLeaf/src/omp/cg.cpp:105-113.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.50 to 1.00 cycles (12.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 8 bytes. The binary function is storing 32 bytes.

General properties

nb instructions	14
loop length	56
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.50	1.50	1.83	1.83	1.83	1.83	2.00	1.67	0.00	0.00	0.00	0.00	1.00	1.00	1.00	1.00	1.00
cycles	1.50	1.50	1.83	1.83	1.83	1.83	2.00	1.67	0.00	0.00	0.00	0.00	1.00	1.00	1.00	1.00	1.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	1.75
Overall L1	5.00-12.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.50 cycles. At this rate:

0% of peak load performance is reached (0.64 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (2.56 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 402f80

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #992]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X19, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
BL 4016d0 <@plt_start@+0x100>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W20, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4016e0 <@plt_start@+0x110>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W10, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDP W0, W12, [X19, #52]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
SUB W2, W0, W12,LSL #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
SDIV W1, W2, W20	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5-12	5-12.50	scal (25.0%)
MSUB W3, W1, W20, W2	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
CMP W10, W3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.LT 4031ac <_Z10cg_calc_uriiidPdS_PKdS_S1_._omp_fn.0+0x22c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼cg_calc_ur(int, int, int, double, double, double, double const, double, double const*) [clone ._omp_fn.0]–	38.60	62.00
▼Loop 25 - cg.cpp:105-113 - exec–	0.01	0.02
○Loop 24 - cg.cpp:105-105 - exec	0.02	0.04
▼Loop 26 - cg.cpp:108-113 - exec–	0.00	0.00
○Loop 27 - cg.cpp:108-113 - exec	38.57	61.23

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code