OV - exec - Function cg_calc_w(int, int, int, double*, double const*, double*, double const*, double const*) [clone ._omp

	Function: cg_calc_w(int, int, int, double, double const, double, double const, double const*) [c ...	Module: exec	Source: cg.cpp:83-90	Coverage (incl. loops): 36.43% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-118-5752/intel/TeaLeaf/build/TeaLeaf/src/omp/cg.cpp: 83 - 90

--------------------------------------------------------------------------------

83:   #pragma omp parallel for reduction(+ : pw_temp)

84: #endif

85:   for (int jj = halo_depth; jj < y - halo_depth; ++jj) {

86:     for (int kk = halo_depth; kk < x - halo_depth; ++kk) {

87:       const int index = kk + jj * x;

88:       const double smvp = tealeaf_SMVP(p);

89:       w[index] = smvp;

90:       pw_temp += w[index] * p[index];

0x402d40 STP	X29, X30, [SP, #992]!

0x402d44 ADD	X29, SP, #0

0x402d48 STP	X19, X20, [SP, #16]

0x402d4c ORR	X19, XZR, X0

0x402d50 BL	4016d0

0x402d54 ORR	W20, WZR, W0

0x402d58 BL	4016e0

0x402d5c ORR	W14, WZR, W0

0x402d60 LDP	W0, W16, [X19, #44]

0x402d64 SUB	W2, W0, W16,LSL #1

0x402d68 SDIV	W1, W2, W20

0x402d6c MSUB	W3, W1, W20, W2

0x402d70 CMP	W14, W3

0x402d74 B.LT	402f68

(21) 0x402d78 MADD	W4, W1, W14, W3

(21) 0x402d7c MOVI	D27, #0

(21) 0x402d80 ADD	W5, W1, W4

(21) 0x402d84 CMP	W4, W5

(21) 0x402d88 B.GE	402f38

(21) 0x402d8c LDR	W17, [X19, #40]

(21) 0x402d90 ADD	W0, W16, W5

(21) 0x402d94 ADD	W14, W16, W4

(21) 0x402d98 FMOV	D24, #1.0000000

(21) 0x402d9c LDP	X3, X12, [X19]

(21) 0x402da0 SBFM	X30, X16, #0, #31

(21) 0x402da4 LDP	X6, X5, [X19, #16]

(21) 0x402da8 SUB	W18, W17, W16,LSL #1

(21) 0x402dac SBFM	X13, X17, #61, #31

(21) 0x402db0 SUB	W20, W17, W16

(21) 0x402db4 MADD	W15, W14, W17, WZR

(21) 0x402db8 ADD	X9, X3, #8

(21) 0x402dbc SUB	X8, X3, #8

(21) 0x402dc0 ADD	X18, X18, X30

(21) 0x402dc4 ADD	X11, X3, X13

(21) 0x402dc8 SUB	X10, X3, X13

(21) 0x402dcc ADD	X7, X6, #8

(21) 0x402dd0 ADD	X4, X5, X13

(21) 0x402dd4 HINT	#0

(21) 0x402dd8 HINT	#0

(21) 0x402ddc HINT	#0

  (22) 0x402de0 CMP	W16, W20

  (22) 0x402de4 B.GE	402f28

  (22) 0x402de8 SBFM	X2, X15, #0, #31

  (22) 0x402dec ADD	X1, X18, X2

  (22) 0x402df0 ADD	X2, X2, X30

  (22) 0x402df4 UBFM	X13, X1, #61, #60

  (22) 0x402df8 UBFM	X1, X2, #61, #60

  (22) 0x402dfc SUB	X2, X13, X2,LSL #3

  (22) 0x402e00 TBZ	W2, #3, 402e68

  (22) 0x402e04 LDR	D26, [X7, X1]

  (22) 0x402e08 LDR	D31, [X6, X1]

  (22) 0x402e0c LDR	D28, [X4, X1]

  (22) 0x402e10 LDR	D30, [X5, X1]

  (22) 0x402e14 FADD	D29, D26, D31

  (22) 0x402e18 LDR	D25, [X8, X1]

  (22) 0x402e1c LDR	D21, [X9, X1]

  (22) 0x402e20 FADD	D22, D28, D30

  (22) 0x402e24 LDR	D20, [X10, X1]

  (22) 0x402e28 FADD	D0, D29, D24

  (22) 0x402e2c FMUL	D1, D31, D25

  (22) 0x402e30 LDR	D2, [X3, X1]

  (22) 0x402e34 LDR	D23, [X11, X1]

  (22) 0x402e38 FMUL	D3, D30, D20

  (22) 0x402e3c FMADD	D4, D26, D21, D1

  (22) 0x402e40 FADD	D5, D0, D22

  (22) 0x402e44 FMADD	D6, D28, D23, D3

  (22) 0x402e48 FNMSUB	D7, D5, D2, D4

  (22) 0x402e4c FSUB	D16, D7, S6

  (22) 0x402e50 STR	D16, [X12, X1]

  (22) 0x402e54 LDR	D17, [X3, X1]

  (22) 0x402e58 ADD	X1, X1, #8

  (22) 0x402e5c FMADD	D27, D16, D17, D27

  (22) 0x402e60 CMP	X13, X1

  (22) 0x402e64 B.EQ	402f28

    (23) 0x402e68 LDR	D18, [X7, X1]

    (23) 0x402e6c ADD	X2, X1, #8

    (23) 0x402e70 LDR	D30, [X6, X1]

    (23) 0x402e74 LDR	D26, [X4, X1]

    (23) 0x402e78 LDR	D29, [X5, X1]

    (23) 0x402e7c FADD	D28, D18, D30

    (23) 0x402e80 LDR	D31, [X8, X1]

    (23) 0x402e84 LDR	D25, [X9, X1]

    (23) 0x402e88 FADD	D21, D26, D29

    (23) 0x402e8c LDR	D19, [X10, X1]

    (23) 0x402e90 FADD	D20, D28, D24

    (23) 0x402e94 FMUL	D0, D30, D31

    (23) 0x402e98 LDR	D1, [X3, X1]

    (23) 0x402e9c LDR	D22, [X11, X1]

    (23) 0x402ea0 FMUL	D2, D29, D19

    (23) 0x402ea4 FMADD	D23, D18, D25, D0

    (23) 0x402ea8 FADD	D3, D20, D21

    (23) 0x402eac FMADD	D4, D26, D22, D2

    (23) 0x402eb0 FNMSUB	D5, D3, D1, D23

    (23) 0x402eb4 FSUB	D6, D5, S4

    (23) 0x402eb8 STR	D6, [X12, X1]

    (23) 0x402ebc LDR	D7, [X7, X2]

    (23) 0x402ec0 LDR	D16, [X6, X2]

    (23) 0x402ec4 LDR	D17, [X4, X2]

    (23) 0x402ec8 LDR	D18, [X5, X2]

    (23) 0x402ecc FADD	D30, D7, D16

    (23) 0x402ed0 LDR	D26, [X8, X2]

    (23) 0x402ed4 LDR	D31, [X9, X2]

    (23) 0x402ed8 FADD	D25, D17, D18

    (23) 0x402edc LDR	D29, [X10, X2]

    (23) 0x402ee0 FADD	D28, D30, D24

    (23) 0x402ee4 FMUL	D19, D16, D26

    (23) 0x402ee8 LDR	D1, [X3, X1]

    (23) 0x402eec ADD	X1, X1, #16

    (23) 0x402ef0 LDR	D20, [X3, X2]

    (23) 0x402ef4 LDR	D21, [X11, X2]

    (23) 0x402ef8 FMUL	D0, D18, D29

    (23) 0x402efc FMADD	D22, D7, D31, D19

    (23) 0x402f00 FADD	D2, D28, D25

    (23) 0x402f04 FMADD	D3, D6, D1, D27

    (23) 0x402f08 FMADD	D23, D17, D21, D0

    (23) 0x402f0c FNMSUB	D27, D2, D20, D22

    (23) 0x402f10 FSUB	D4, D27, S23

    (23) 0x402f14 STR	D4, [X12, X2]

    (23) 0x402f18 LDR	D5, [X3, X2]

    (23) 0x402f1c FMADD	D27, D4, D5, D3

    (23) 0x402f20 CMP	X13, X1

    (23) 0x402f24 B.NE	402e68

  (22) 0x402f28 ADD	W14, W14, #1

  (22) 0x402f2c ADD	W15, W15, W17

  (22) 0x402f30 CMP	W0, W14

  (22) 0x402f34 B.GT	402de0

(21) 0x402f38 ADD	X19, X19, #32

(21) 0x402f3c LDR	X1, [X19]

  (20) 0x402f40 FMOV	D24, X1

  (20) 0x402f44 ORR	X16, XZR, X1

  (20) 0x402f48 FADD	D6, D27, D24

  (20) 0x402f4c FMOV	X30, D6

  (20) 0x402f50 CAS	X16, X30, [X19]

  (20) 0x402f54 CMP	X1, X16

  (20) 0x402f58 B.NE	402f74

(21) 0x402f5c LDP	X19, X20, [SP, #16]

(21) 0x402f60 LDP	X29, X30, [SP], #32

(21) 0x402f64 RET

(21) 0x402f68 ADD	W1, W1, #1

(21) 0x402f6c MOVZ	W3, #0

(21) 0x402f70 B	402d78

  (20) 0x402f74 ORR	X1, XZR, X16

  (20) 0x402f78 B	402f40

0x402f7c HINT	#0

Coverage (%)	Name	Source Location	Module
►98.96+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.04+	GOMP_parallel	libgomp.h:980	libgomp.so.1.0.0
○	run_cg_calc_w(Chunk*, Settings[...]	cg.cpp:83	exec
○	cg_main_step_driver(Chunk*, Se[...]	cg_driver.cpp:59	exec
○	cg_driver(Chunk*, Settings&, d[...]	cg_driver.cpp:18	exec
○	solve(Chunk*, Settings&, int, [...]	diffuse.cpp:51	exec
○	diffuse(Chunk*, Settings&)	diffuse.cpp:12	exec
○	main	main.cpp:179	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	basic_string.h:809	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_8

Source file and lines	cg.cpp:83-90
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-118-5752/intel/TeaLeaf/build/TeaLeaf/src/omp/cg.cpp:83-90.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 53% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 12.50 to 3.12 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.50 to 1.00 cycles (12.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 8 bytes. The binary function is storing 32 bytes.

General properties

nb instructions	15
loop length	60
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.50	1.50	1.83	1.83	1.83	1.83	2.00	1.67	0.00	0.00	0.00	0.00	1.00	1.00	1.00	1.00	1.00
cycles	1.50	1.50	1.83	1.83	1.83	1.83	2.00	1.67	0.00	0.00	0.00	0.00	1.00	1.00	1.00	1.00	1.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	1.75
Overall L1	5.00-12.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.50 cycles. At this rate:

0% of peak load performance is reached (0.64 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (2.56 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 402d40

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #992]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X19, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 4016d0 <@plt_start@+0x100>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W20, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4016e0 <@plt_start@+0x110>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W14, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDP W0, W16, [X19, #44]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
SUB W2, W0, W16,LSL #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SDIV W1, W2, W20	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	scal (25.0%)
MSUB W3, W1, W20, W2	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
CMP W14, W3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.LT 402f68 <_Z9cg_calc_wiiiPdPKdS_S1_S1_._omp_fn.0+0x228>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_8

Source file and lines	cg.cpp:83-90
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-118-5752/intel/TeaLeaf/build/TeaLeaf/src/omp/cg.cpp:83-90.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.50 to 1.00 cycles (12.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 8 bytes. The binary function is storing 32 bytes.

General properties

nb instructions	15
loop length	60
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.50	1.50	1.83	1.83	1.83	1.83	2.00	1.67	0.00	0.00	0.00	0.00	1.00	1.00	1.00	1.00	1.00
cycles	1.50	1.50	1.83	1.83	1.83	1.83	2.00	1.67	0.00	0.00	0.00	0.00	1.00	1.00	1.00	1.00	1.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	1.75
Overall L1	5.00-12.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.50 cycles. At this rate:

0% of peak load performance is reached (0.64 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (2.56 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 402d40

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #992]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X19, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 4016d0 <@plt_start@+0x100>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W20, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4016e0 <@plt_start@+0x110>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W14, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDP W0, W16, [X19, #44]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
SUB W2, W0, W16,LSL #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SDIV W1, W2, W20	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	scal (25.0%)
MSUB W3, W1, W20, W2	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
CMP W14, W3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.LT 402f68 <_Z9cg_calc_wiiiPdPKdS_S1_S1_._omp_fn.0+0x228>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A

Name	Coverage (%)	Time (s)
▼cg_calc_w(int, int, int, double, double const, double, double const, double const*) [clone ._omp_fn.0]–	36.43	58.51
▼Loop 21 - cg.cpp:83-90 - exec–	0.00	0.01
○Loop 20 - cg.cpp:83-83 - exec	0.02	0.03
▼Loop 22 - cg.cpp:86-90 - exec–	0.00	0.01
○Loop 23 - cg.cpp:86-90 - exec	36.41	57.79

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code