OV - exec - Function cg_init(int, int, int, int, double, double, double*, double const*, double const*, double*, double*, double*, double*, double*, double*) [clone ._omp

	Function: cg_init(int, int, int, int, double, double, double, double const, double const, double ...	Module: exec	Source: cg.cpp:59-68	Coverage (incl. loops): 0.01% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-118-5752/intel/TeaLeaf/build/TeaLeaf/src/omp/cg.cpp: 59 - 68

--------------------------------------------------------------------------------

59:   #pragma omp parallel for reduction(+ : rro_temp)

60: #endif

61:   for (int jj = halo_depth; jj < y - halo_depth; ++jj) {

62:     for (int kk = halo_depth; kk < x - halo_depth; ++kk) {

63:       const int index = kk + jj * x;

64:       const double smvp = tealeaf_SMVP(u);

65:       w[index] = smvp;

66:       r[index] = u[index] - w[index];

67:       p[index] = r[index];

68:       rro_temp += r[index] * p[index];

0x402ac0 STP	X29, X30, [SP, #976]!

0x402ac4 ADD	X29, SP, #0

0x402ac8 STP	X19, X20, [SP, #16]

0x402acc ORR	X19, XZR, X0

0x402ad0 BL	4016d0

0x402ad4 ORR	W20, WZR, W0

0x402ad8 BL	4016e0

0x402adc ORR	W16, WZR, W0

0x402ae0 LDP	W0, W18, [X19, #60]

0x402ae4 SUB	W2, W0, W18,LSL #1

0x402ae8 SDIV	W1, W2, W20

0x402aec MSUB	W3, W1, W20, W2

0x402af0 CMP	W16, W3

0x402af4 B.LT	402d24

(17) 0x402af8 MADD	W4, W1, W16, W3

(17) 0x402afc MOVI	D27, #0

(17) 0x402b00 ADD	W5, W1, W4

(17) 0x402b04 CMP	W4, W5

(17) 0x402b08 B.GE	402cf4

(17) 0x402b0c STP	X21, X22, [SP, #32]

(17) 0x402b10 ADD	W0, W18, W5

(17) 0x402b14 ADD	W16, W18, W4

(17) 0x402b18 FMOV	D26, #1.0000000

(17) 0x402b1c SBFM	X21, X18, #0, #31

(17) 0x402b20 LDR	W20, [X19, #56]

(17) 0x402b24 LDP	X3, X14, [X19]

(17) 0x402b28 LDP	X6, X5, [X19, #32]

(17) 0x402b2c SUB	W30, W20, W18,LSL #1

(17) 0x402b30 SBFM	X15, X20, #61, #31

(17) 0x402b34 SUB	W22, W20, W18

(17) 0x402b38 MADD	W17, W16, W20, WZR

(17) 0x402b3c ADD	X11, X3, #8

(17) 0x402b40 SUB	X10, X3, #8

(17) 0x402b44 LDP	X7, X8, [X19, #16]

(17) 0x402b48 ADD	X30, X30, X21

(17) 0x402b4c ADD	X13, X3, X15

(17) 0x402b50 SUB	X12, X3, X15

(17) 0x402b54 ADD	X9, X6, #8

(17) 0x402b58 ADD	X4, X5, X15

(17) 0x402b5c HINT	#0

  (18) 0x402b60 CMP	W18, W22

  (18) 0x402b64 B.GE	402ce0

  (18) 0x402b68 SBFM	X2, X17, #0, #31

  (18) 0x402b6c ADD	X1, X30, X2

  (18) 0x402b70 ADD	X2, X2, X21

  (18) 0x402b74 UBFM	X15, X1, #61, #60

  (18) 0x402b78 UBFM	X1, X2, #61, #60

  (18) 0x402b7c SUB	X2, X15, X2,LSL #3

  (18) 0x402b80 TBZ	W2, #3, 402c00

  (18) 0x402b84 LDR	D30, [X6, X1]

  (18) 0x402b88 LDR	D28, [X5, X1]

  (18) 0x402b8c LDR	D31, [X10, X1]

  (18) 0x402b90 LDR	D29, [X12, X1]

  (18) 0x402b94 LDR	D25, [X9, X1]

  (18) 0x402b98 LDR	D24, [X4, X1]

  (18) 0x402b9c FMUL	D0, D30, D31

  (18) 0x402ba0 LDR	D22, [X11, X1]

  (18) 0x402ba4 FMUL	D1, D28, D29

  (18) 0x402ba8 LDR	D23, [X13, X1]

  (18) 0x402bac FADD	D2, D25, D30

  (18) 0x402bb0 FADD	D5, D24, D28

  (18) 0x402bb4 LDR	D4, [X3, X1]

  (18) 0x402bb8 FMADD	D3, D25, D22, D0

  (18) 0x402bbc FMADD	D6, D24, D23, D1

  (18) 0x402bc0 FADD	D7, D2, D26

  (18) 0x402bc4 FADD	D16, D7, D5

  (18) 0x402bc8 FADD	D17, D3, D6

  (18) 0x402bcc FNMSUB	D18, D16, D4, D17

  (18) 0x402bd0 STR	D18, [X8, X1]

  (18) 0x402bd4 LDR	D19, [X3, X1]

  (18) 0x402bd8 FADD	D20, D17, D19

  (18) 0x402bdc FMSUB	D21, D16, D4, D20

  (18) 0x402be0 FMADD	D27, D21, D21, D27

  (18) 0x402be4 STR	D21, [X7, X1]

  (18) 0x402be8 STR	D21, [X14, X1]

  (18) 0x402bec ADD	X1, X1, #8

  (18) 0x402bf0 CMP	X15, X1

  (18) 0x402bf4 B.EQ	402ce0

  (18) 0x402bf8 HINT	#0

  (18) 0x402bfc HINT	#0

    (19) 0x402c00 LDR	D30, [X6, X1]

    (19) 0x402c04 ADD	X2, X1, #8

    (19) 0x402c08 LDR	D28, [X5, X1]

    (19) 0x402c0c LDR	D31, [X10, X1]

    (19) 0x402c10 LDR	D29, [X12, X1]

    (19) 0x402c14 LDR	D25, [X9, X1]

    (19) 0x402c18 LDR	D24, [X4, X1]

    (19) 0x402c1c FMUL	D0, D30, D31

    (19) 0x402c20 LDR	D22, [X11, X1]

    (19) 0x402c24 FMUL	D1, D28, D29

    (19) 0x402c28 LDR	D23, [X13, X1]

    (19) 0x402c2c FADD	D2, D25, D30

    (19) 0x402c30 FADD	D5, D24, D28

    (19) 0x402c34 LDR	D4, [X3, X1]

    (19) 0x402c38 FMADD	D3, D25, D22, D0

    (19) 0x402c3c FMADD	D6, D24, D23, D1

    (19) 0x402c40 FADD	D7, D2, D26

    (19) 0x402c44 FADD	D16, D7, D5

    (19) 0x402c48 FADD	D17, D3, D6

    (19) 0x402c4c FNMSUB	D18, D16, D4, D17

    (19) 0x402c50 STR	D18, [X8, X1]

    (19) 0x402c54 LDR	D19, [X3, X1]

    (19) 0x402c58 FADD	D20, D17, D19

    (19) 0x402c5c FMSUB	D21, D16, D4, D20

    (19) 0x402c60 FMADD	D27, D21, D21, D27

    (19) 0x402c64 STR	D21, [X7, X1]

    (19) 0x402c68 STR	D21, [X14, X1]

    (19) 0x402c6c ADD	X1, X1, #16

    (19) 0x402c70 LDR	D30, [X6, X2]

    (19) 0x402c74 LDR	D28, [X5, X2]

    (19) 0x402c78 LDR	D31, [X10, X2]

    (19) 0x402c7c LDR	D29, [X12, X2]

    (19) 0x402c80 LDR	D25, [X9, X2]

    (19) 0x402c84 LDR	D24, [X4, X2]

    (19) 0x402c88 FMUL	D0, D30, D31

    (19) 0x402c8c LDR	D22, [X11, X2]

    (19) 0x402c90 FMUL	D1, D28, D29

    (19) 0x402c94 LDR	D23, [X13, X2]

    (19) 0x402c98 FADD	D2, D25, D30

    (19) 0x402c9c FADD	D5, D24, D28

    (19) 0x402ca0 LDR	D4, [X3, X2]

    (19) 0x402ca4 FMADD	D3, D25, D22, D0

    (19) 0x402ca8 FMADD	D6, D24, D23, D1

    (19) 0x402cac FADD	D7, D2, D26

    (19) 0x402cb0 FADD	D16, D7, D5

    (19) 0x402cb4 FADD	D17, D3, D6

    (19) 0x402cb8 FNMSUB	D18, D16, D4, D17

    (19) 0x402cbc STR	D18, [X8, X2]

    (19) 0x402cc0 LDR	D19, [X3, X2]

    (19) 0x402cc4 FADD	D20, D17, D19

    (19) 0x402cc8 FMSUB	D21, D16, D4, D20

    (19) 0x402ccc FMADD	D27, D21, D21, D27

    (19) 0x402cd0 STR	D21, [X7, X2]

    (19) 0x402cd4 STR	D21, [X14, X2]

    (19) 0x402cd8 CMP	X15, X1

    (19) 0x402cdc B.NE	402c00

  (18) 0x402ce0 ADD	W16, W16, #1

  (18) 0x402ce4 ADD	W17, W17, W20

  (18) 0x402ce8 CMP	W0, W16

  (18) 0x402cec B.GT	402b60

(17) 0x402cf0 LDP	X21, X22, [SP, #32]

(17) 0x402cf4 ADD	X19, X19, #48

(17) 0x402cf8 LDR	X1, [X19]

  (16) 0x402cfc ORR	X18, XZR, X1

  (16) 0x402d00 FMOV	D26, X1

  (16) 0x402d04 FADD	D30, D27, D26

  (16) 0x402d08 FMOV	X6, D30

  (16) 0x402d0c CAS	X18, X6, [X19]

  (16) 0x402d10 CMP	X1, X18

  (16) 0x402d14 B.NE	402d30

(17) 0x402d18 LDP	X19, X20, [SP, #16]

(17) 0x402d1c LDP	X29, X30, [SP], #48

(17) 0x402d20 RET

(17) 0x402d24 ADD	W1, W1, #1

(17) 0x402d28 MOVZ	W3, #0

(17) 0x402d2c B	402af8

  (16) 0x402d30 ORR	X1, XZR, X18

  (16) 0x402d34 B	402cfc

0x402d38 HINT	#0

0x402d3c HINT	#0

Coverage (%)	Name	Source Location	Module
►99.12+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_8

Source file and lines	cg.cpp:59-68
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-118-5752/intel/TeaLeaf/build/TeaLeaf/src/omp/cg.cpp:59-68.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 53% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 12.50 to 3.12 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.50 to 1.00 cycles (12.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 8 bytes. The binary function is storing 32 bytes.

General properties

nb instructions	16
loop length	64
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.50	1.50	1.83	1.83	1.83	1.83	2.00	1.67	0.00	0.00	0.00	0.00	1.00	1.00	1.00	1.00	1.00
cycles	1.50	1.50	1.83	1.83	1.83	1.83	2.00	1.67	0.00	0.00	0.00	0.00	1.00	1.00	1.00	1.00	1.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	1.75
Overall L1	5.00-12.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.50 cycles. At this rate:

0% of peak load performance is reached (0.64 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (2.56 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 402ac0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #976]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X19, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 4016d0 <@plt_start@+0x100>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W20, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4016e0 <@plt_start@+0x110>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W16, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDP W0, W18, [X19, #60]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
SUB W2, W0, W18,LSL #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SDIV W1, W2, W20	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	scal (25.0%)
MSUB W3, W1, W20, W2	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
CMP W16, W3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.LT 402d24 <_Z7cg_initiiiiddPdPKdS1_S_S_S_S_S_S_._omp_fn.3+0x264>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_8

Source file and lines	cg.cpp:59-68
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-118-5752/intel/TeaLeaf/build/TeaLeaf/src/omp/cg.cpp:59-68.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.50 to 1.00 cycles (12.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 8 bytes. The binary function is storing 32 bytes.

General properties

nb instructions	16
loop length	64
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.50	1.50	1.83	1.83	1.83	1.83	2.00	1.67	0.00	0.00	0.00	0.00	1.00	1.00	1.00	1.00	1.00
cycles	1.50	1.50	1.83	1.83	1.83	1.83	2.00	1.67	0.00	0.00	0.00	0.00	1.00	1.00	1.00	1.00	1.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	1.75
Overall L1	5.00-12.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.50 cycles. At this rate:

0% of peak load performance is reached (0.64 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (2.56 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 402ac0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #976]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X19, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 4016d0 <@plt_start@+0x100>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W20, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4016e0 <@plt_start@+0x110>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W16, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDP W0, W18, [X19, #60]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
SUB W2, W0, W18,LSL #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SDIV W1, W2, W20	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	scal (25.0%)
MSUB W3, W1, W20, W2	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
CMP W16, W3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.LT 402d24 <_Z7cg_initiiiiddPdPKdS1_S_S_S_S_S_S_._omp_fn.3+0x264>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A

Name	Coverage (%)	Time (s)
▼cg_init(int, int, int, int, double, double, double, double const, double const, double, double, double, double, double, double*) [clone ._omp_fn.3]–	0.01	0.02
▼Loop 17 - cg.cpp:59-68 - exec–	0.00	0.00
▼Loop 18 - cg.cpp:62-68 - exec–	0.00	0.00
○Loop 19 - cg.cpp:62-68 - exec	0.01	0.02
○Loop 16 - cg.cpp:59-59 - exec	0.00	0.00

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code