OV - exec - Function cg_calc_w(int, int, int, double*, double const*, double*, double const*, double const*) [clone .omp

	Function: cg_calc_w(int, int, int, double, double const, double, double const, double const*) [c ...	Module: exec	Source: cg.cpp:83-90	Coverage (incl. loops): 37.33% \| (excl. loops): 0.03%

/home/hbollore/qaas/qaas-runs/174-118-5752/intel/TeaLeaf/build/TeaLeaf/src/omp/cg.cpp: 83 - 90

--------------------------------------------------------------------------------

83:   #pragma omp parallel for reduction(+ : pw_temp)

84: #endif

85:   for (int jj = halo_depth; jj < y - halo_depth; ++jj) {

86:     for (int kk = halo_depth; kk < x - halo_depth; ++kk) {

87:       const int index = kk + jj * x;

88:       const double smvp = tealeaf_SMVP(p);

89:       w[index] = smvp;

90:       pw_temp += w[index] * p[index];

0x402e10 SUB	SP, SP, #336

0x402e14 STP	X29, X30, [SP, #240]

0x402e18 STP	X28, X27, [SP, #256]

0x402e1c STP	X26, X25, [SP, #272]

0x402e20 STP	X24, X23, [SP, #288]

0x402e24 STP	X22, X21, [SP, #304]

0x402e28 STP	X20, X19, [SP, #320]

0x402e2c ADD	X29, SP, #240

0x402e30 LDRSW	X21, [X3]

0x402e34 LDR	W8, [X2]

0x402e38 SUB	W8, W8, W21

0x402e3c CMP	W21, W8

0x402e40 B.GE	403420

0x402e44 LDR	X9, [X29, #104]

0x402e48 LDR	W1, [X0]

0x402e4c ORR	X20, XZR, X4

0x402e50 ORR	X24, XZR, X5

0x402e54 ORR	X23, XZR, X6

0x402e58 ORR	X19, XZR, X7

0x402e5c ADRP	X0,

0x402e60 ADD	X0, X0, #1016

0x402e64 SUB	X3, X29, #24

0x402e68 SUB	X4, X29, #12

0x402e6c SUB	X5, X29, #16

0x402e70 SUB	X6, X29, #20

0x402e74 STUR	XZR, [X29, #480]

0x402e78 STR	X9, [SP, #16]

0x402e7c ORN	W9, WZR, W21

0x402e80 MOVZ	W2, #34

0x402e84 MOVZ	W7, #1

0x402e88 STR	W1, [SP, #12]

0x402e8c ADD	W25, W8, W9

0x402e90 MOVZ	W8, #1

0x402e94 STP	W25, WZR, [X29, #496]

0x402e98 STP	WZR, W8, [X29, #488]

0x402e9c STR	W8, [SP]

0x402ea0 BL	401520

0x402ea4 LDP	W8, W9, [X29, #496]

0x402ea8 CMP	W8, W25

0x402eac CSEL	W17, W8, W25, #3

0x402eb0 ADD	W10, W17, #1

0x402eb4 CMP	W9, W10

0x402eb8 B.CS	403360

0x402ebc LDRSW	X10, [X20]

0x402ec0 SUB	W11, W10, W21

0x402ec4 CMP	W21, W11

0x402ec8 B.GE	403360

0x402ecc LDR	X12, [X29, #96]

0x402ed0 LDR	X8, [X24]

0x402ed4 LDR	X1, [X23]

0x402ed8 ADD	X13, X21, X10

0x402edc MOVZ	W15, #8

0x402ee0 SUB	X18, X29, #32

0x402ee4 UBFM	X2, X10, #60, #59

0x402ee8 ADD	W16, W9, W21

0x402eec MOVI	D2, #0

0x402ef0 FMOV	D0, #1.0000000

0x402ef4 FMOV	V1.2D, #1.0000000

0x402ef8 SUB	X22, X21, X10

0x402efc ORR	W11, WZR, WZR

0x402f00 SUB	X15, X15, X21,LSL #3

0x402f04 LDR	X14, [X19]

0x402f08 ADD	X0, X18, #8

0x402f0c STP	X8, X13, [X29, #936]

0x402f10 STP	W17, W16, [X29, #416]

0x402f14 ADD	X18, X8, X15

0x402f18 LDR	X13, [X12]

0x402f1c SUB	X12, X2, X21,LSL #3

0x402f20 STUR	X18, [X29, #408]

0x402f24 SUB	X18, X1, X21,LSL #3

0x402f28 STUR	X18, [X29, #400]

0x402f2c ADD	X18, X1, X12

0x402f30 ADD	X12, X14, X12

0x402f34 STR	X18, [SP, #120]

0x402f38 SUB	X18, X14, X21,LSL #3

0x402f3c STUR	X13, [X29, #464]

0x402f40 SUB	X13, X13, X21,LSL #3

0x402f44 STR	X18, [SP, #112]

0x402f48 STP	X12, X13, [SP, #96]

0x402f4c SUB	X13, X14, #8

0x402f50 ADD	X12, X14, X15

0x402f54 MADD	W15, W10, W16, WZR

0x402f58 STP	X12, X13, [SP, #80]

0x402f5c SUB	X13, X10, X21,LSL #1

0x402f60 AND	X12, X13, #8062

0x402f64 STP	X12, X13, [SP, #64]

0x402f68 ADD	X12, X12, X21

0x402f6c STR	X12, [SP, #56]

0x402f70 ADD	X12, X8, #16

0x402f74 ADD	X8, X8, #8

0x402f78 STR	X12, [SP, #48]

0x402f7c ADD	X12, X1, #16

0x402f80 STR	X12, [SP, #40]

0x402f84 ADD	X12, X14, #16

0x402f88 STR	X12, [SP, #32]

0x402f8c ADD	X12, X14, X21,LSL #3

0x402f90 STR	X12, [SP, #24]

0x402f94 SUB	X12, XZR, X10

0x402f98 STP	X8, X12, [X29, #952]

0x402f9c B	402fb8

  (24) 0x402fa0 ADD	W8, W9, #1

  (24) 0x402fa4 ADD	W11, W11, #1

  (24) 0x402fa8 ADD	W15, W27, W10

  (24) 0x402fac CMP	W9, W17

  (24) 0x402fb0 ORR	W9, WZR, W8

  (24) 0x402fb4 B.EQ	403360

  (24) 0x402fb8 SBFM	X27, X15, #0, #31

  (24) 0x402fbc SBFM	X16, X15, #61, #31

  (24) 0x402fc0 CMP	X13, #6

  (24) 0x402fc4 B.CS	402fe0

  (24) 0x402fc8 ORR	X6, XZR, X21

  (24) 0x402fcc B	403294

0x402fd0 HINT	#0

0x402fd4 HINT	#0

0x402fd8 HINT	#0

0x402fdc HINT	#0

(23) 0x402fe0 LDUR	W8, [X29, #420]

(23) 0x402fe4 STUR	X16, [X29, #456]

(23) 0x402fe8 ORR	X13, XZR, X21

(23) 0x402fec ORR	X16, XZR, X1

(23) 0x402ff0 ORR	X19, XZR, X22

(23) 0x402ff4 ADD	W12, W8, W11

(23) 0x402ff8 LDR	X8, [SP, #80]

(23) 0x402ffc MADD	W12, W10, W12, WZR

(23) 0x403000 SBFM	X15, X12, #0, #31

(23) 0x403004 SBFM	X12, X12, #61, #31

(23) 0x403008 ADD	X2, X10, X15

(23) 0x40300c ADD	X3, X21, X15

(23) 0x403010 ADD	X17, X8, X2,LSL #3

(23) 0x403014 LDR	X8, [SP, #88]

(23) 0x403018 ADD	X21, X1, X3,LSL #3

(23) 0x40301c ADD	X26, X8, X3,LSL #3

(23) 0x403020 LDR	X8, [SP, #96]

(23) 0x403024 ADD	X23, X8, X12

(23) 0x403028 LDUR	X8, [X29, #432]

(23) 0x40302c ADD	X4, X8, X15

(23) 0x403030 LDR	X8, [SP, #112]

(23) 0x403034 ADD	X15, X22, X15

(23) 0x403038 SUB	X22, X29, #32

(23) 0x40303c ADD	X25, X1, X4,LSL #3

(23) 0x403040 ADD	X30, X14, X4,LSL #3

(23) 0x403044 ADD	X28, X8, X12

(23) 0x403048 ADD	X8, X14, X15,LSL #3

(23) 0x40304c LDR	X15, [SP, #120]

(23) 0x403050 ADD	X12, X15, X12

(23) 0x403054 LDUR	X15, [X29, #400]

(23) 0x403058 ADD	X20, X15, X2,LSL #3

(23) 0x40305c LDUR	X15, [X29, #408]

(23) 0x403060 ADD	X7, X15, X2,LSL #3

(23) 0x403064 LDUR	X15, [X29, #424]

(23) 0x403068 ADD	X24, X15, X3,LSL #3

(23) 0x40306c LDR	X15, [SP, #104]

(23) 0x403070 ADD	X18, X15, X2,LSL #3

(23) 0x403074 LDUR	X15, [X29, #464]

(23) 0x403078 ADD	X1, X15, X3,LSL #3

(23) 0x40307c CMP	X1, X7

(23) 0x403080 CCMP	X24, X18, #2, #3

(23) 0x403084 CSINC	W15, WZR, WZR, #2

(23) 0x403088 CMP	X1, X20

(23) 0x40308c CCMP	X21, X18, #2, #3

(23) 0x403090 CSINC	W2, WZR, WZR, #2

(23) 0x403094 CMP	X1, X12

(23) 0x403098 CCMP	X25, X18, #2, #3

(23) 0x40309c CSINC	W3, WZR, WZR, #2

(23) 0x4030a0 CMP	X1, X28

(23) 0x4030a4 CCMP	X8, X18, #2, #3

(23) 0x4030a8 CSINC	W4, WZR, WZR, #2

(23) 0x4030ac CMP	X1, X23

(23) 0x4030b0 CCMP	X30, X18, #2, #3

(23) 0x4030b4 CSINC	W5, WZR, WZR, #2

(23) 0x4030b8 CMP	X1, X17

(23) 0x4030bc CCMP	X26, X18, #2, #3

(23) 0x4030c0 CSINC	W6, WZR, WZR, #2

(23) 0x4030c4 CMP	X22, X7

(23) 0x4030c8 CCMP	X24, X0, #2, #3

(23) 0x4030cc CSINC	W7, WZR, WZR, #2

(23) 0x4030d0 CMP	X22, X20

(23) 0x4030d4 CCMP	X21, X0, #2, #3

(23) 0x4030d8 CSINC	W20, WZR, WZR, #2

(23) 0x4030dc CMP	X22, X12

(23) 0x4030e0 CCMP	X25, X0, #2, #3

(23) 0x4030e4 CSINC	W25, WZR, WZR, #2

(23) 0x4030e8 CMP	X22, X28

(23) 0x4030ec CCMP	X8, X0, #2, #3

(23) 0x4030f0 CSINC	W28, WZR, WZR, #2

(23) 0x4030f4 CMP	X22, X23

(23) 0x4030f8 CCMP	X30, X0, #2, #3

(23) 0x4030fc CSINC	W23, WZR, WZR, #2

(23) 0x403100 CMP	X22, X17

(23) 0x403104 CCMP	X26, X0, #2, #3

(23) 0x403108 CSINC	W12, WZR, WZR, #2

(23) 0x40310c CMP	X22, X18

(23) 0x403110 CCMP	X1, X0, #2, #3

(23) 0x403114 B.CC	403348

(23) 0x403118 ORR	X1, XZR, X16

(23) 0x40311c ORR	X22, XZR, X19

(23) 0x403120 TBNZ	W15, #0, 403280

(23) 0x403124 TBNZ	W2, #0, 403280

(23) 0x403128 TBNZ	W3, #0, 403280

(23) 0x40312c TBNZ	W4, #0, 403280

(23) 0x403130 TBNZ	W5, #0, 403280

(23) 0x403134 TBNZ	W6, #0, 403280

(23) 0x403138 TBNZ	W7, #0, 403280

(23) 0x40313c TBNZ	W20, #0, 403280

(23) 0x403140 TBNZ	W25, #0, 403280

(23) 0x403144 TBNZ	W28, #0, 403280

(23) 0x403148 TBNZ	W23, #0, 403280

(23) 0x40314c LDUR	W17, [X29, #416]

(23) 0x403150 ORR	X21, XZR, X13

(23) 0x403154 TBNZ	W12, #0, 403278

(23) 0x403158 LDP	X13, X12, [SP, #40]

(23) 0x40315c ADD	X8, X21, X27

(23) 0x403160 ADD	X15, X22, X27

(23) 0x403164 MOVI	V4.2D, #0

(23) 0x403168 MOV	V4.D[0], V2.D[0]

(23) 0x40316c ORR	X2, XZR, XZR

(23) 0x403170 MOVI	V3.2D, #0

(23) 0x403174 ADD	X6, X14, X15,LSL #3

(23) 0x403178 LDR	X15, [SP, #32]

(23) 0x40317c ADD	X3, X12, X8,LSL #3

(23) 0x403180 LDP	X16, X12, [X29, #968]

(23) 0x403184 ADD	X4, X12, X8,LSL #3

(23) 0x403188 LDUR	X12, [X29, #432]

(23) 0x40318c ADD	X12, X12, X27

(23) 0x403190 ADD	X7, X15, X12,LSL #3

(23) 0x403194 ADD	X15, X13, X8,LSL #3

(23) 0x403198 LDR	X8, [SP, #24]

(23) 0x40319c ADD	X5, X13, X12,LSL #3

(23) 0x4031a0 LDP	X25, X13, [SP, #64]

(23) 0x4031a4 ADD	X20, X8, X16

  (25) 0x4031a8 ADD	X8, X3, X2

  (25) 0x4031ac ADD	X12, X7, X2

  (25) 0x4031b0 SUBS	X25, X25, #4

  (25) 0x4031b4 LDUR	Q2, [X8, #504]

  (25) 0x4031b8 LDUR	Q5, [X8, #8]

  (25) 0x4031bc LDP	Q6, Q7, [X8, #2032]

  (25) 0x4031c0 ADD	X8, X5, X2

  (25) 0x4031c4 LDP	Q25, Q26, [X12, #2032]

  (25) 0x4031c8 ADD	X12, X6, X2

  (25) 0x4031cc FADD	V20.2D, V2.2D, V1.2D

  (25) 0x4031d0 FADD	V21.2D, V5.2D, V1.2D

  (25) 0x4031d4 LDP	Q16, Q17, [X8, #2032]

  (25) 0x4031d8 ADD	X8, X15, X2

  (25) 0x4031dc LDP	Q18, Q19, [X8, #2032]

  (25) 0x4031e0 ADD	X8, X20, X2

  (25) 0x4031e4 LDUR	Q24, [X8, #504]

  (25) 0x4031e8 LDP	Q27, Q28, [X12]

  (25) 0x4031ec ADD	X12, X4, X2

  (25) 0x4031f0 ADD	X2, X2, #32

  (25) 0x4031f4 FADD	V22.2D, V6.2D, V16.2D

  (25) 0x4031f8 FADD	V20.2D, V20.2D, V22.2D

  (25) 0x4031fc FADD	V22.2D, V7.2D, V17.2D

  (25) 0x403200 FADD	V21.2D, V21.2D, V22.2D

  (25) 0x403204 LDP	Q22, Q23, [X8]

  (25) 0x403208 FADD	V20.2D, V20.2D, V18.2D

  (25) 0x40320c FADD	V21.2D, V21.2D, V19.2D

  (25) 0x403210 FMUL	V21.2D, V23.2D, V21.2D

  (25) 0x403214 LDUR	Q23, [X8, #24]

  (25) 0x403218 FMUL	V20.2D, V22.2D, V20.2D

  (25) 0x40321c LDUR	Q22, [X8, #8]

  (25) 0x403220 FMUL	V5.2D, V23.2D, V5.2D

  (25) 0x403224 FMUL	V2.2D, V22.2D, V2.2D

  (25) 0x403228 FMLA	V5.2D, V22.2D, V7.2D

  (25) 0x40322c FMLA	V2.2D, V24.2D, V6.2D

  (25) 0x403230 FMLA	V5.2D, V26.2D, V17.2D

  (25) 0x403234 LDP	Q6, Q7, [X8]

  (25) 0x403238 FMLA	V2.2D, V25.2D, V16.2D

  (25) 0x40323c FMLA	V5.2D, V28.2D, V19.2D

  (25) 0x403240 FMLA	V2.2D, V27.2D, V18.2D

  (25) 0x403244 FSUB	V5.2D, V21.2D, V5.2D

  (25) 0x403248 FSUB	V2.2D, V20.2D, V2.2D

  (25) 0x40324c FMLA	V3.2D, V7.2D, V5.2D

  (25) 0x403250 FMLA	V4.2D, V6.2D, V2.2D

  (25) 0x403254 STP	Q2, Q5, [X12]

  (25) 0x403258 B.NE	4031a8

(23) 0x40325c FADD	V2.2D, V3.2D, V4.2D

(23) 0x403260 LDP	X6, X8, [SP, #56]

(23) 0x403264 FADDP	D2, V2.2D

(23) 0x403268 STUR	D2, [X29, #480]

(23) 0x40326c CMP	X13, X8

(23) 0x403270 B.EQ	402fa0

(23) 0x403274 B	403294

(23) 0x403278 ORR	X6, XZR, X21

(23) 0x40327c B	40328c

(23) 0x403280 LDUR	W17, [X29, #416]

(23) 0x403284 ORR	X21, XZR, X13

(23) 0x403288 ORR	X6, XZR, X13

(23) 0x40328c LDR	X13, [SP, #72]

(23) 0x403290 LDUR	X16, [X29, #456]

  (24) 0x403294 LDUR	X12, [X29, #448]

  (24) 0x403298 ADD	X8, X6, X27

  (24) 0x40329c ADD	X5, X22, X6

  (24) 0x4032a0 ORR	X15, XZR, XZR

  (24) 0x4032a4 ADD	X12, X8, X12

  (24) 0x4032a8 ADD	X2, X14, X12,LSL #3

  (24) 0x4032ac ADD	X12, X8, X10

  (24) 0x4032b0 ADD	X3, X1, X12,LSL #3

  (24) 0x4032b4 ADD	X4, X14, X12,LSL #3

  (24) 0x4032b8 ADD	X12, X16, X6,LSL #3

  (24) 0x4032bc LDUR	X16, [X29, #440]

  (24) 0x4032c0 ADD	X6, X1, X12

  (24) 0x4032c4 ADD	X19, X14, X12

  (24) 0x4032c8 LDUR	X12, [X29, #464]

  (24) 0x4032cc ADD	X7, X16, X8,LSL #3

  (24) 0x4032d0 ADD	X20, X12, X8,LSL #3

  (24) 0x4032d4 HINT	#0

  (24) 0x4032d8 HINT	#0

  (24) 0x4032dc HINT	#0

    (21) 0x4032e0 ADD	X8, X7, X15

    (21) 0x4032e4 LDR	D5, [X3, X15]

    (21) 0x4032e8 LDR	D19, [X4, X15]

    (21) 0x4032ec LDR	D6, [X6, X15]

    (21) 0x4032f0 ADDS	X5, X5, #1

    (21) 0x4032f4 LDR	D20, [X2, X15]

    (21) 0x4032f8 LDP	D4, D3, [X8, #1016]

    (21) 0x4032fc ADD	X8, X19, X15

    (21) 0x403300 LDUR	D18, [X8, #504]

    (21) 0x403304 FADD	D7, D3, D0

    (21) 0x403308 FADD	D16, D4, D5

    (21) 0x40330c FADD	D7, D7, D16

    (21) 0x403310 LDP	D17, D16, [X8]

    (21) 0x403314 FADD	D7, D7, D6

    (21) 0x403318 FMUL	D3, D16, D3

    (21) 0x40331c FMADD	D3, D18, D4, D3

    (21) 0x403320 FMADD	D3, D19, D5, D3

    (21) 0x403324 FMADD	D3, D20, D6, D3

    (21) 0x403328 FNMSUB	D3, D17, D7, D3

    (21) 0x40332c STR	D3, [X20, X15]

    (21) 0x403330 ADD	X15, X15, #8

    (21) 0x403334 LDR	D4, [X8]

    (21) 0x403338 FMADD	D2, D4, D3, D2

    (21) 0x40333c STUR	D2, [X29, #480]

    (21) 0x403340 B.CC	4032e0

  (24) 0x403344 B	402fa0

(23) 0x403348 LDUR	W17, [X29, #416]

(23) 0x40334c ORR	X21, XZR, X13

(23) 0x403350 ORR	X6, XZR, X13

(23) 0x403354 ORR	X1, XZR, X16

(23) 0x403358 ORR	X22, XZR, X19

(23) 0x40335c B	40328c

0x403360 LDR	W19, [SP, #12]

0x403364 ADRP	X0,

0x403368 ADD	X0, X0, #1040

0x40336c ORR	W1, WZR, W19

0x403370 BL	401750

0x403374 SUB	X8, X29, #32

0x403378 ADRP	X6,

0x40337c ADRP	X0,

0x403380 ADD	X0, X0, #1064

0x403384 ADRP	X5,

0x403388 ADD	X5, X5, #3568

0x40338c ORR	W1, WZR, W19

0x403390 STUR	X8, [X29, #472]

0x403394 SUB	X4, X29, #40

0x403398 MOVZ	W2, #1

0x40339c MOVZ	W3, #8

0x4033a0 LDR	X6, [X6, #4016]

0x4033a4 BL	401720

0x4033a8 CMP	W0, #2

0x4033ac B.EQ	4033e8

0x4033b0 LDR	X8, [SP, #16]

0x4033b4 CMP	W0, #1

0x4033b8 B.NE	403420

0x4033bc LDR	D0, [X8]

0x4033c0 LDUR	D1, [X29, #480]

0x4033c4 ADRP	X2,

0x4033c8 ADRP	X0,

0x4033cc ADD	X0, X0, #1064

0x4033d0 ORR	W1, WZR, W19

0x4033d4 FADD	D0, D1, D0

0x4033d8 STR	D0, [X8]

0x4033dc LDR	X2, [X2, #4016]

0x4033e0 BL	4015e0

0x4033e4 B	403420

0x4033e8 LDR	X11, [SP, #16]

0x4033ec LDUR	D0, [X29, #480]

0x4033f0 LDR	D1, [X11]

0x4033f4 HINT	#0

0x4033f8 HINT	#0

0x4033fc HINT	#0

(22) 0x403400 FADD	D2, D1, D0

(22) 0x403404 FMOV	X9, D1

(22) 0x403408 ORR	X10, XZR, X9

(22) 0x40340c FMOV	X8, D2

(22) 0x403410 CAS	X10, X8, [X11]

(22) 0x403414 FMOV	D1, X10

(22) 0x403418 CMP	X10, X9

(22) 0x40341c B.NE	403400

0x403420 LDP	X20, X19, [SP, #320]

0x403424 LDP	X22, X21, [SP, #304]

0x403428 LDP	X24, X23, [SP, #288]

0x40342c LDP	X26, X25, [SP, #272]

0x403430 LDP	X28, X27, [SP, #256]

0x403434 LDP	X29, X30, [SP, #240]

0x403438 ADD	SP, SP, #336

0x40343c RET

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.03% of application time for run armclang_3

Source file and lines	cg.cpp:83-90
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-118-5752/intel/TeaLeaf/build/TeaLeaf/src/omp/cg.cpp:83-90.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 18.67 to 1.83 cycles (10.18x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 52% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 18.67 to 13.83 cycles (1.35x speedup).

Details

Store and arithmetical VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 18.67 to 2.00 cycles (9.33x speedup).

Matching between your function (in the source code) and the binary function

The binary function is composed of 1 FP arithmetical operations:

1: addition or subtraction

The binary function is loading 236 bytes. The binary function is storing 320 bytes.

Arithmetic intensity

Arithmetic intensity is 0.00 FP operations per loaded or stored byte.

General properties

nb instructions	152
loop length	608
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

18.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	6.00	6.00	12.83	12.83	12.83	12.83	12.83	12.83	1.25	1.25	1.25	1.25	18.67	18.67	18.67	14.50	14.50
cycles	6.00	6.00	12.83	12.83	12.83	12.83	12.83	12.83	1.25	1.25	1.25	1.25	18.67	18.67	18.67	14.50	14.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	18.13
Overall L1	18.67

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
other	0%

all	33%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

INT+FP

all	1%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 18.67 cycles. At this rate:

13% of peak load performance is reached (12.64 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
35% of peak store performance is reached (17.14 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 402e10

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
SUB SP, SP, #336	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X29, X30, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X28, X27, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X26, X25, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X24, X23, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X22, X21, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X20, X19, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #240	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDRSW X21, [X3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W8, [X2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB W8, W8, W21	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP W21, W8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 403420 <_Z9cg_calc_wiiiPdPKdS_S1_S1_.omp_outlined+0x610>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [X29, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR W1, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X20, XZR, X4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X24, XZR, X5	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X23, XZR, X6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X19, XZR, X7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADRP X0, <42fe5c>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #1016	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X3, X29, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X4, X29, #12	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X5, X29, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X6, X29, #20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STUR XZR, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X9, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORN W9, WZR, W21	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MOVZ W2, #34	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W7, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STR W1, [SP, #12]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD W25, W8, W9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MOVZ W8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP W25, WZR, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP WZR, W8, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR W8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 401520 <@plt_start@+0x80>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP W8, W9, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP W8, W25	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CSEL W17, W8, W25, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W10, W17, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W9, W10	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.CS 403360 <_Z9cg_calc_wiiiPdPKdS_S1_S1_.omp_outlined+0x550>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDRSW X10, [X20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SUB W11, W10, W21	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP W21, W11	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 403360 <_Z9cg_calc_wiiiPdPKdS_S1_S1_.omp_outlined+0x550>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X12, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X1, [X23]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD X13, X21, X10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W15, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SUB X18, X29, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
UBFM X2, X10, #60, #59	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD W16, W9, W21	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MOVI D2, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FMOV D0, #1.0000000	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FMOV V1.2D, #1.0000000	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
SUB X22, X21, X10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR W11, WZR, WZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X15, X15, X21,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X14, [X19]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD X0, X18, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X8, X13, [X29, #936]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP W17, W16, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X18, X8, X15	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X13, [X12]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
SUB X12, X2, X21,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STUR X18, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
SUB X18, X1, X21,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STUR X18, [X29, #400]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X18, X1, X12	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X12, X14, X12	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X18, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
SUB X18, X14, X21,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STUR X13, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
SUB X13, X13, X21,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR X18, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X12, X13, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
SUB X13, X14, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X12, X14, X15	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MADD W15, W10, W16, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
STP X12, X13, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
SUB X13, X10, X21,LSL #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
AND X12, X13, #8062	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X12, X13, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X12, X12, X21	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X12, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X12, X8, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X8, X8, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X12, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X12, X1, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X12, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X12, X14, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X12, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X12, X14, X21,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X12, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
SUB X12, XZR, X10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X8, X12, [X29, #952]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
B 402fb8 <_Z9cg_calc_wiiiPdPKdS_S1_S1_.omp_outlined+0x1a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
LDR W19, [SP, #12]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADRP X0, <42f364>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #1040	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR W1, WZR, W19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 401750 <@plt_start@+0x2b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X8, X29, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADRP X6, <42f378>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X0, <42f37c>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #1064	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADRP X5, <200402384>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (50.0%)
ADD X5, X5, #3568	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR W1, WZR, W19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STUR X8, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
SUB X4, X29, #40	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W2, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W3, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X6, [X6, #4016]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 401720 <@plt_start@+0x280>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W0, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4033e8 <_Z9cg_calc_wiiiPdPKdS_S1_S1_.omp_outlined+0x5d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP W0, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 403420 <_Z9cg_calc_wiiiPdPKdS_S1_S1_.omp_outlined+0x610>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D0, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDUR D1, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
ADRP X2, <42f3c4>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X0, <42f3c8>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #1064	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR W1, WZR, W19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
FADD D0, D1, D0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
STR D0, [X8]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDR X2, [X2, #4016]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 4015e0 <@plt_start@+0x140>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 403420 <_Z9cg_calc_wiiiPdPKdS_S1_S1_.omp_outlined+0x610>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X11, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR D0, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDR D1, [X11]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
LDP X20, X19, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X22, X21, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X24, X23, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X26, X25, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X28, X27, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X29, X30, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
ADD SP, SP, #336	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.03% of application time for run armclang_3

Source file and lines	cg.cpp:83-90
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-118-5752/intel/TeaLeaf/build/TeaLeaf/src/omp/cg.cpp:83-90.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 18.67 to 2.00 cycles (9.33x speedup).

Matching between your function (in the source code) and the binary function

The binary function is composed of 1 FP arithmetical operations:

1: addition or subtraction

The binary function is loading 236 bytes. The binary function is storing 320 bytes.

Arithmetic intensity

Arithmetic intensity is 0.00 FP operations per loaded or stored byte.

General properties

nb instructions	152
loop length	608
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

18.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	6.00	6.00	12.83	12.83	12.83	12.83	12.83	12.83	1.25	1.25	1.25	1.25	18.67	18.67	18.67	14.50	14.50
cycles	6.00	6.00	12.83	12.83	12.83	12.83	12.83	12.83	1.25	1.25	1.25	1.25	18.67	18.67	18.67	14.50	14.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	18.13
Overall L1	18.67

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
other	0%

all	33%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

INT+FP

all	1%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 18.67 cycles. At this rate:

13% of peak load performance is reached (12.64 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
35% of peak store performance is reached (17.14 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 402e10

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
SUB SP, SP, #336	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X29, X30, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X28, X27, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X26, X25, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X24, X23, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X22, X21, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X20, X19, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #240	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDRSW X21, [X3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W8, [X2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB W8, W8, W21	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP W21, W8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 403420 <_Z9cg_calc_wiiiPdPKdS_S1_S1_.omp_outlined+0x610>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [X29, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR W1, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X20, XZR, X4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X24, XZR, X5	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X23, XZR, X6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X19, XZR, X7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADRP X0, <42fe5c>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #1016	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X3, X29, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X4, X29, #12	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X5, X29, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X6, X29, #20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STUR XZR, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X9, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORN W9, WZR, W21	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MOVZ W2, #34	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W7, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STR W1, [SP, #12]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD W25, W8, W9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MOVZ W8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP W25, WZR, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP WZR, W8, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR W8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 401520 <@plt_start@+0x80>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP W8, W9, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP W8, W25	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CSEL W17, W8, W25, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W10, W17, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W9, W10	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.CS 403360 <_Z9cg_calc_wiiiPdPKdS_S1_S1_.omp_outlined+0x550>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDRSW X10, [X20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SUB W11, W10, W21	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP W21, W11	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 403360 <_Z9cg_calc_wiiiPdPKdS_S1_S1_.omp_outlined+0x550>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X12, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X1, [X23]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD X13, X21, X10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W15, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SUB X18, X29, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
UBFM X2, X10, #60, #59	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD W16, W9, W21	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MOVI D2, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FMOV D0, #1.0000000	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FMOV V1.2D, #1.0000000	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
SUB X22, X21, X10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR W11, WZR, WZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X15, X15, X21,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X14, [X19]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD X0, X18, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X8, X13, [X29, #936]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP W17, W16, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X18, X8, X15	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X13, [X12]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
SUB X12, X2, X21,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STUR X18, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
SUB X18, X1, X21,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STUR X18, [X29, #400]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X18, X1, X12	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X12, X14, X12	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X18, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
SUB X18, X14, X21,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STUR X13, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
SUB X13, X13, X21,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR X18, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X12, X13, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
SUB X13, X14, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X12, X14, X15	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MADD W15, W10, W16, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
STP X12, X13, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
SUB X13, X10, X21,LSL #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
AND X12, X13, #8062	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X12, X13, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X12, X12, X21	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X12, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X12, X8, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X8, X8, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X12, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X12, X1, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X12, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X12, X14, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X12, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X12, X14, X21,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X12, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
SUB X12, XZR, X10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X8, X12, [X29, #952]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
B 402fb8 <_Z9cg_calc_wiiiPdPKdS_S1_S1_.omp_outlined+0x1a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
LDR W19, [SP, #12]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADRP X0, <42f364>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #1040	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR W1, WZR, W19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 401750 <@plt_start@+0x2b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X8, X29, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADRP X6, <42f378>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X0, <42f37c>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #1064	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADRP X5, <200402384>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (50.0%)
ADD X5, X5, #3568	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR W1, WZR, W19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STUR X8, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
SUB X4, X29, #40	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W2, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W3, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X6, [X6, #4016]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 401720 <@plt_start@+0x280>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W0, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4033e8 <_Z9cg_calc_wiiiPdPKdS_S1_S1_.omp_outlined+0x5d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP W0, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 403420 <_Z9cg_calc_wiiiPdPKdS_S1_S1_.omp_outlined+0x610>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D0, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDUR D1, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
ADRP X2, <42f3c4>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X0, <42f3c8>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #1064	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR W1, WZR, W19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
FADD D0, D1, D0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
STR D0, [X8]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDR X2, [X2, #4016]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 4015e0 <@plt_start@+0x140>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 403420 <_Z9cg_calc_wiiiPdPKdS_S1_S1_.omp_outlined+0x610>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X11, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR D0, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDR D1, [X11]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
LDP X20, X19, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X22, X21, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X24, X23, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X26, X25, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X28, X27, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X29, X30, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
ADD SP, SP, #336	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼cg_calc_w(int, int, int, double, double const, double, double const, double const*) [clone .omp_outlined]–	37.33	57.21
▼Loop 23 - cg.cpp:85-90 - exec–	0.10	0.15
○Loop 25 - cg.cpp:88-90 - exec	37.20	56.71
▼Loop 24 - cg.cpp:85-90 - exec–	0.00	0.01
○Loop 21 - cg.cpp:86-90 - exec	0.00	0.00
○Loop 22 - cg.cpp:83-83 - exec	0.00	0.00

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