OV - exec - Function cg_init(int, int, int, int, double, double, double*, double const*, double const*, double*, double*, double*, double*, double*, double*) [clone .omp

	Function: cg_init(int, int, int, int, double, double, double, double const, double const, double ...	Module: exec	Source: cg.cpp:59-68	Coverage (incl. loops): 0.01% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-118-5752/intel/TeaLeaf/build/TeaLeaf/src/omp/cg.cpp: 59 - 68

--------------------------------------------------------------------------------

59:   #pragma omp parallel for reduction(+ : rro_temp)

60: #endif

61:   for (int jj = halo_depth; jj < y - halo_depth; ++jj) {

62:     for (int kk = halo_depth; kk < x - halo_depth; ++kk) {

63:       const int index = kk + jj * x;

64:       const double smvp = tealeaf_SMVP(u);

65:       w[index] = smvp;

66:       r[index] = u[index] - w[index];

67:       p[index] = r[index];

68:       rro_temp += r[index] * p[index];

0x4024d0 SUB	SP, SP, #496

0x4024d4 STP	X29, X30, [SP, #400]

0x4024d8 STP	X28, X27, [SP, #416]

0x4024dc STP	X26, X25, [SP, #432]

0x4024e0 STP	X24, X23, [SP, #448]

0x4024e4 STP	X22, X21, [SP, #464]

0x4024e8 STP	X20, X19, [SP, #480]

0x4024ec ADD	X29, SP, #400

0x4024f0 LDRSW	X28, [X3]

0x4024f4 LDR	W8, [X2]

0x4024f8 SUB	W8, W8, W28

0x4024fc CMP	W28, W8

0x402500 B.GE	402d40

0x402504 LDR	X9, [X29, #120]

0x402508 LDR	W1, [X0]

0x40250c ORR	X20, XZR, X4

0x402510 ORR	X22, XZR, X5

0x402514 ORR	X21, XZR, X6

0x402518 ORR	X19, XZR, X7

0x40251c ADRP	X0,

0x402520 ADD	X0, X0, #920

0x402524 SUB	X3, X29, #24

0x402528 SUB	X4, X29, #12

0x40252c SUB	X5, X29, #16

0x402530 SUB	X6, X29, #20

0x402534 STUR	XZR, [X29, #480]

0x402538 STR	X9, [SP, #24]

0x40253c ORN	W9, WZR, W28

0x402540 MOVZ	W2, #34

0x402544 MOVZ	W7, #1

0x402548 STR	W1, [SP, #20]

0x40254c ADD	W23, W8, W9

0x402550 MOVZ	W8, #1

0x402554 STP	W23, WZR, [X29, #496]

0x402558 STP	WZR, W8, [X29, #488]

0x40255c STR	W8, [SP]

0x402560 BL	401520

0x402564 LDP	W8, W3, [X29, #496]

0x402568 CMP	W8, W23

0x40256c CSEL	W2, W8, W23, #3

0x402570 ADD	W8, W2, #1

0x402574 CMP	W3, W8

0x402578 B.CS	402c8c

0x40257c LDRSW	X4, [X20]

0x402580 SUB	W8, W4, W28

0x402584 CMP	W28, W8

0x402588 B.GE	402c8c

0x40258c LDR	X10, [X29, #96]

0x402590 LDP	X9, X8, [X29, #104]

0x402594 LDR	X14, [X22]

0x402598 MOVZ	W12, #8

0x40259c ADD	X13, X28, X4

0x4025a0 ADD	W15, W3, W28

0x4025a4 SUB	X16, X29, #32

0x4025a8 MOVI	D2, #0

0x4025ac FMOV	D0, #1.0000000

0x4025b0 FMOV	V1.2D, #1.0000000

0x4025b4 SUB	X7, X28, X4

0x4025b8 ORR	W11, WZR, WZR

0x4025bc SUB	X12, X12, X28,LSL #3

0x4025c0 LDR	X6, [X21]

0x4025c4 LDR	X5, [X19]

0x4025c8 STUR	X13, [X29, #368]

0x4025cc UBFM	X13, X4, #60, #59

0x4025d0 ADD	X16, X16, #8

0x4025d4 SUB	X13, X13, X28,LSL #3

0x4025d8 STR	X16, [SP, #176]

0x4025dc STR	W15, [SP, #196]

0x4025e0 STUR	X28, [X29, #352]

0x4025e4 STUR	W2, [X29, #348]

0x4025e8 STR	X7, [SP, #184]

0x4025ec LDR	X21, [X10]

0x4025f0 LDR	X22, [X9]

0x4025f4 LDR	X25, [X8]

0x4025f8 ADD	X9, X14, X12

0x4025fc ADD	X8, X6, X13

0x402600 ADD	X10, X14, #16

0x402604 STP	X14, X4, [X29, #840]

0x402608 STUR	X6, [X29, #320]

0x40260c STR	X5, [SP, #200]

0x402610 STR	X9, [SP, #152]

0x402614 SUB	X9, X6, X28,LSL #3

0x402618 STP	X8, X9, [SP, #136]

0x40261c SUB	X9, X5, X28,LSL #3

0x402620 SUB	X8, X21, X28,LSL #3

0x402624 STP	X22, X21, [SP, #160]

0x402628 STUR	X25, [X29, #360]

0x40262c STP	X8, X9, [SP, #120]

0x402630 SUB	X9, X22, X28,LSL #3

0x402634 SUB	X8, X25, X28,LSL #3

0x402638 STP	X8, X9, [SP, #104]

0x40263c ADD	X8, X5, X13

0x402640 SUB	X9, X5, #8

0x402644 STR	X8, [SP, #96]

0x402648 ADD	X8, X5, X12

0x40264c STP	X8, X9, [SP, #80]

0x402650 SUB	X8, X4, X28,LSL #1

0x402654 ADD	X9, X6, #16

0x402658 STUR	X8, [X29, #464]

0x40265c AND	X8, X8, #8062

0x402660 STP	X9, X10, [SP, #48]

0x402664 ADD	X10, X5, #16

0x402668 ADD	X9, X5, X28,LSL #3

0x40266c STR	X8, [SP, #72]

0x402670 ADD	X8, X8, X28

0x402674 STP	X9, X10, [SP, #32]

0x402678 SUB	X9, XZR, X4

0x40267c STR	X8, [SP, #64]

0x402680 MADD	W8, W4, W15, WZR

0x402684 STUR	X9, [X29, #384]

0x402688 ADD	X9, X14, #8

0x40268c STUR	X9, [X29, #376]

0x402690 B	4026b8

0x402694 HINT	#0

0x402698 HINT	#0

0x40269c HINT	#0

(19) 0x4026a0 ADD	W9, W3, #1

(19) 0x4026a4 ADD	W11, W11, #1

(19) 0x4026a8 ADD	W8, W30, W4

(19) 0x4026ac CMP	W3, W2

(19) 0x4026b0 ORR	W3, WZR, W9

(19) 0x4026b4 B.EQ	402c8c

(19) 0x4026b8 SBFM	X30, X8, #0, #31

(19) 0x4026bc SBFM	X16, X8, #61, #31

(19) 0x4026c0 LDUR	X8, [X29, #464]

(19) 0x4026c4 CMP	X8, #12

(19) 0x4026c8 B.CC	402b2c

(19) 0x4026cc LDR	W8, [SP, #196]

(19) 0x4026d0 LDP	X14, X12, [SP, #80]

(19) 0x4026d4 STUR	X16, [X29, #416]

(19) 0x4026d8 ADD	W8, W8, W11

(19) 0x4026dc STUR	X30, [X29, #456]

(19) 0x4026e0 STUR	W3, [X29, #424]

(19) 0x4026e4 MADD	W8, W4, W8, WZR

(19) 0x4026e8 SBFM	X9, X8, #0, #31

(19) 0x4026ec SBFM	X8, X8, #61, #31

(19) 0x4026f0 ADD	X13, X28, X9

(19) 0x4026f4 ADD	X10, X4, X9

(19) 0x4026f8 ADD	X23, X12, X13,LSL #3

(19) 0x4026fc LDR	X12, [SP, #96]

(19) 0x402700 ADD	X20, X14, X10,LSL #3

(19) 0x402704 ADD	X16, X6, X13,LSL #3

(19) 0x402708 ADD	X2, X25, X13,LSL #3

(19) 0x40270c ADD	X30, X21, X13,LSL #3

(19) 0x402710 ADD	X26, X22, X13,LSL #3

(19) 0x402714 ADD	X15, X12, X8

(19) 0x402718 LDUR	X12, [X29, #368]

(19) 0x40271c ADD	X14, X12, X9

(19) 0x402720 ADD	X9, X7, X9

(19) 0x402724 ADD	X24, X5, X9,LSL #3

(19) 0x402728 LDP	X12, X9, [SP, #128]

(19) 0x40272c ADD	X19, X5, X14,LSL #3

(19) 0x402730 ADD	X12, X12, X8

(19) 0x402734 ADD	X4, X9, X8

(19) 0x402738 LDR	X9, [SP, #144]

(19) 0x40273c ADD	X8, X6, X14,LSL #3

(19) 0x402740 SUB	X14, X29, #32

(19) 0x402744 ADD	X5, X9, X10,LSL #3

(19) 0x402748 LDR	X9, [SP, #152]

(19) 0x40274c ADD	X6, X9, X10,LSL #3

(19) 0x402750 LDUR	X9, [X29, #328]

(19) 0x402754 ADD	X0, X9, X13,LSL #3

(19) 0x402758 LDR	X9, [SP, #104]

(19) 0x40275c ADD	X28, X9, X10,LSL #3

(19) 0x402760 LDR	X9, [SP, #112]

(19) 0x402764 CMP	X30, X28

(19) 0x402768 ADD	X25, X9, X10,LSL #3

(19) 0x40276c LDR	X9, [SP, #120]

(19) 0x402770 ADD	X27, X9, X10,LSL #3

(19) 0x402774 CCMP	X2, X27, #2, #3

(19) 0x402778 CSINC	W9, WZR, WZR, #2

(19) 0x40277c STUR	W9, [X29, #452]

(19) 0x402780 LDR	X9, [SP, #176]

(19) 0x402784 CMP	X30, X9

(19) 0x402788 CCMP	X14, X27, #2, #3

(19) 0x40278c CSINC	W10, WZR, WZR, #2

(19) 0x402790 CMP	X30, X6

(19) 0x402794 CCMP	X0, X27, #2, #3

(19) 0x402798 STUR	W10, [X29, #448]

(19) 0x40279c CSINC	W10, WZR, WZR, #2

(19) 0x4027a0 CMP	X30, X5

(19) 0x4027a4 CCMP	X16, X27, #2, #3

(19) 0x4027a8 STUR	W10, [X29, #444]

(19) 0x4027ac CSINC	W10, WZR, WZR, #2

(19) 0x4027b0 CMP	X30, X4

(19) 0x4027b4 CCMP	X8, X27, #2, #3

(19) 0x4027b8 STUR	W10, [X29, #440]

(19) 0x4027bc CSINC	W10, WZR, WZR, #2

(19) 0x4027c0 CMP	X30, X12

(19) 0x4027c4 CCMP	X24, X27, #2, #3

(19) 0x4027c8 STUR	W10, [X29, #436]

(19) 0x4027cc CSINC	W10, WZR, WZR, #2

(19) 0x4027d0 CMP	X30, X15

(19) 0x4027d4 CCMP	X19, X27, #2, #3

(19) 0x4027d8 STUR	W10, [X29, #432]

(19) 0x4027dc CSINC	W10, WZR, WZR, #2

(19) 0x4027e0 CMP	X30, X20

(19) 0x4027e4 CCMP	X23, X27, #2, #3

(19) 0x4027e8 STUR	W10, [X29, #428]

(19) 0x4027ec CSINC	W10, WZR, WZR, #2

(19) 0x4027f0 CMP	X26, X28

(19) 0x4027f4 CCMP	X2, X25, #2, #3

(19) 0x4027f8 STUR	W10, [X29, #412]

(19) 0x4027fc CSINC	W10, WZR, WZR, #2

(19) 0x402800 CMP	X26, X9

(19) 0x402804 CCMP	X14, X25, #2, #3

(19) 0x402808 STUR	W10, [X29, #408]

(19) 0x40280c CSINC	W10, WZR, WZR, #2

(19) 0x402810 CMP	X26, X6

(19) 0x402814 CCMP	X0, X25, #2, #3

(19) 0x402818 STUR	W10, [X29, #404]

(19) 0x40281c CSINC	W10, WZR, WZR, #2

(19) 0x402820 CMP	X26, X5

(19) 0x402824 CCMP	X16, X25, #2, #3

(19) 0x402828 STUR	W10, [X29, #400]

(19) 0x40282c CSINC	W10, WZR, WZR, #2

(19) 0x402830 CMP	X26, X4

(19) 0x402834 CCMP	X8, X25, #2, #3

(19) 0x402838 STUR	W10, [X29, #396]

(19) 0x40283c CSINC	W10, WZR, WZR, #2

(19) 0x402840 CMP	X26, X12

(19) 0x402844 CCMP	X24, X25, #2, #3

(19) 0x402848 STUR	W10, [X29, #392]

(19) 0x40284c CSINC	W17, WZR, WZR, #2

(19) 0x402850 CMP	X26, X15

(19) 0x402854 CCMP	X19, X25, #2, #3

(19) 0x402858 CSINC	W3, WZR, WZR, #2

(19) 0x40285c CMP	X26, X20

(19) 0x402860 CCMP	X23, X25, #2, #3

(19) 0x402864 CSINC	W21, WZR, WZR, #2

(19) 0x402868 CMP	X2, X9

(19) 0x40286c CCMP	X14, X28, #2, #3

(19) 0x402870 CSINC	W18, WZR, WZR, #2

(19) 0x402874 CMP	X2, X6

(19) 0x402878 CCMP	X0, X28, #2, #3

(19) 0x40287c CSINC	W1, WZR, WZR, #2

(19) 0x402880 CMP	X2, X5

(19) 0x402884 CCMP	X16, X28, #2, #3

(19) 0x402888 CSINC	W22, WZR, WZR, #2

(19) 0x40288c CMP	X2, X4

(19) 0x402890 CCMP	X8, X28, #2, #3

(19) 0x402894 CSINC	W7, WZR, WZR, #2

(19) 0x402898 CMP	X2, X12

(19) 0x40289c CCMP	X24, X28, #2, #3

(19) 0x4028a0 CSINC	W13, WZR, WZR, #2

(19) 0x4028a4 CMP	X2, X15

(19) 0x4028a8 CCMP	X19, X28, #2, #3

(19) 0x4028ac CSINC	W10, WZR, WZR, #2

(19) 0x4028b0 CMP	X2, X20

(19) 0x4028b4 CCMP	X23, X28, #2, #3

(19) 0x4028b8 CSINC	W2, WZR, WZR, #2

(19) 0x4028bc CMP	X14, X6

(19) 0x4028c0 CCMP	X0, X9, #2, #3

(19) 0x4028c4 CSINC	W0, WZR, WZR, #2

(19) 0x4028c8 CMP	X14, X5

(19) 0x4028cc CCMP	X16, X9, #2, #3

(19) 0x4028d0 CSINC	W16, WZR, WZR, #2

(19) 0x4028d4 CMP	X14, X4

(19) 0x4028d8 CCMP	X8, X9, #2, #3

(19) 0x4028dc CSINC	W8, WZR, WZR, #2

(19) 0x4028e0 CMP	X14, X12

(19) 0x4028e4 CCMP	X24, X9, #2, #3

(19) 0x4028e8 CSINC	W12, WZR, WZR, #2

(19) 0x4028ec CMP	X14, X15

(19) 0x4028f0 CCMP	X19, X9, #2, #3

(19) 0x4028f4 CSINC	W15, WZR, WZR, #2

(19) 0x4028f8 CMP	X14, X20

(19) 0x4028fc CCMP	X23, X9, #2, #3

(19) 0x402900 CSINC	W4, WZR, WZR, #2

(19) 0x402904 CMP	X26, X27

(19) 0x402908 CCMP	X30, X25, #2, #3

(19) 0x40290c B.CC	402c5c

(19) 0x402910 LDUR	W9, [X29, #452]

(19) 0x402914 TBNZ	W9, #0, 402c5c

(19) 0x402918 LDP	X28, X25, [X29, #864]

(19) 0x40291c LDUR	X30, [X29, #456]

(19) 0x402920 LDUR	W9, [X29, #448]

(19) 0x402924 TBNZ	W9, #0, 402c34

(19) 0x402928 LDUR	W9, [X29, #444]

(19) 0x40292c TBNZ	W9, #0, 402c34

(19) 0x402930 LDUR	W9, [X29, #440]

(19) 0x402934 TBNZ	W9, #0, 402c34

(19) 0x402938 LDUR	W9, [X29, #436]

(19) 0x40293c TBNZ	W9, #0, 402c34

(19) 0x402940 LDUR	W9, [X29, #432]

(19) 0x402944 TBNZ	W9, #0, 402c34

(19) 0x402948 LDUR	W9, [X29, #428]

(19) 0x40294c TBNZ	W9, #0, 402c34

(19) 0x402950 LDUR	W9, [X29, #412]

(19) 0x402954 TBNZ	W9, #0, 402c34

(19) 0x402958 LDUR	W9, [X29, #408]

(19) 0x40295c TBNZ	W9, #0, 402c34

(19) 0x402960 LDUR	W9, [X29, #404]

(19) 0x402964 TBNZ	W9, #0, 402c34

(19) 0x402968 LDUR	W9, [X29, #400]

(19) 0x40296c TBNZ	W9, #0, 402c34

(19) 0x402970 LDUR	W9, [X29, #396]

(19) 0x402974 TBNZ	W9, #0, 402c34

(19) 0x402978 LDUR	W9, [X29, #392]

(19) 0x40297c TBNZ	W9, #0, 402c34

(19) 0x402980 TBNZ	W17, #0, 402c34

(19) 0x402984 TBNZ	W3, #0, 402c34

(19) 0x402988 TBNZ	W21, #0, 402c34

(19) 0x40298c TBNZ	W18, #0, 402c34

(19) 0x402990 TBNZ	W1, #0, 402c34

(19) 0x402994 TBNZ	W22, #0, 402c34

(19) 0x402998 TBNZ	W7, #0, 402c34

(19) 0x40299c LDP	X22, X21, [SP, #160]

(19) 0x4029a0 TBNZ	W13, #0, 402c10

(19) 0x4029a4 LDUR	X6, [X29, #320]

(19) 0x4029a8 LDR	X5, [SP, #200]

(19) 0x4029ac LDR	X7, [SP, #184]

(19) 0x4029b0 TBNZ	W10, #0, 402bf8

(19) 0x4029b4 TBNZ	W2, #0, 402bf8

(19) 0x4029b8 TBNZ	W0, #0, 402bf8

(19) 0x4029bc TBNZ	W16, #0, 402bf8

(19) 0x4029c0 TBNZ	W8, #0, 402bf8

(19) 0x4029c4 LDUR	X16, [X29, #416]

(19) 0x4029c8 TBNZ	W12, #0, 402b20

(19) 0x4029cc TBNZ	W15, #0, 402b20

(19) 0x4029d0 TBNZ	W4, #0, 402b20

(19) 0x4029d4 LDP	X10, X9, [SP, #48]

(19) 0x4029d8 ADD	X8, X28, X30

(19) 0x4029dc LDR	X17, [SP, #72]

(19) 0x4029e0 MOVI	V4.2D, #0

(19) 0x4029e4 MOV	V4.D[0], V2.D[0]

(19) 0x4029e8 ORR	X20, XZR, XZR

(19) 0x4029ec MOVI	V3.2D, #0

(19) 0x4029f0 ADD	X24, X25, X8,LSL #3

(19) 0x4029f4 ADD	X26, X22, X8,LSL #3

(19) 0x4029f8 ADD	X15, X21, X8,LSL #3

(19) 0x4029fc ADD	X23, X9, X8,LSL #3

(19) 0x402a00 LDUR	X9, [X29, #368]

(19) 0x402a04 ADD	X19, X10, X8,LSL #3

(19) 0x402a08 ADD	X8, X7, X30

(19) 0x402a0c ADD	X9, X9, X30

(19) 0x402a10 ADD	X30, X5, X8,LSL #3

(19) 0x402a14 LDP	X8, X12, [SP, #32]

(19) 0x402a18 ADD	X25, X10, X9,LSL #3

(19) 0x402a1c ADD	X27, X12, X9,LSL #3

(19) 0x402a20 ADD	X12, X8, X16

  (20) 0x402a24 ADD	X8, X23, X20

  (20) 0x402a28 ADD	X9, X27, X20

  (20) 0x402a2c SUBS	X17, X17, #4

  (20) 0x402a30 LDUR	Q2, [X8, #504]

  (20) 0x402a34 LDUR	Q5, [X8, #8]

  (20) 0x402a38 LDP	Q6, Q7, [X8, #2032]

  (20) 0x402a3c ADD	X8, X25, X20

  (20) 0x402a40 LDP	Q26, Q27, [X9, #2032]

  (20) 0x402a44 ADD	X9, X30, X20

  (20) 0x402a48 FADD	V20.2D, V2.2D, V1.2D

  (20) 0x402a4c FADD	V21.2D, V5.2D, V1.2D

  (20) 0x402a50 LDP	Q16, Q17, [X8, #2032]

  (20) 0x402a54 ADD	X8, X19, X20

  (20) 0x402a58 LDP	Q18, Q19, [X8, #2032]

  (20) 0x402a5c ADD	X8, X12, X20

  (20) 0x402a60 LDUR	Q24, [X8, #24]

  (20) 0x402a64 LDUR	Q25, [X8, #504]

  (20) 0x402a68 LDP	Q28, Q29, [X9]

  (20) 0x402a6c ADD	X9, X15, X20

  (20) 0x402a70 FADD	V22.2D, V6.2D, V16.2D

  (20) 0x402a74 FADD	V20.2D, V20.2D, V22.2D

  (20) 0x402a78 FADD	V22.2D, V7.2D, V17.2D

  (20) 0x402a7c FMUL	V5.2D, V24.2D, V5.2D

  (20) 0x402a80 FADD	V21.2D, V21.2D, V22.2D

  (20) 0x402a84 LDP	Q22, Q23, [X8]

  (20) 0x402a88 FADD	V20.2D, V20.2D, V18.2D

  (20) 0x402a8c FADD	V21.2D, V21.2D, V19.2D

  (20) 0x402a90 FMUL	V21.2D, V23.2D, V21.2D

  (20) 0x402a94 FMUL	V20.2D, V22.2D, V20.2D

  (20) 0x402a98 LDUR	Q22, [X8, #8]

  (20) 0x402a9c FMUL	V2.2D, V22.2D, V2.2D

  (20) 0x402aa0 FMLA	V5.2D, V22.2D, V7.2D

  (20) 0x402aa4 FMLA	V2.2D, V25.2D, V6.2D

  (20) 0x402aa8 FMLA	V5.2D, V27.2D, V17.2D

  (20) 0x402aac FMLA	V2.2D, V26.2D, V16.2D

  (20) 0x402ab0 LDP	Q6, Q7, [X8]

  (20) 0x402ab4 ADD	X8, X26, X20

  (20) 0x402ab8 FMLA	V5.2D, V29.2D, V19.2D

  (20) 0x402abc FMLA	V2.2D, V28.2D, V18.2D

  (20) 0x402ac0 FSUB	V5.2D, V21.2D, V5.2D

  (20) 0x402ac4 FSUB	V2.2D, V20.2D, V2.2D

  (20) 0x402ac8 STP	Q2, Q5, [X9]

  (20) 0x402acc FSUB	V2.2D, V6.2D, V2.2D

  (20) 0x402ad0 FSUB	V5.2D, V7.2D, V5.2D

  (20) 0x402ad4 FMLA	V4.2D, V2.2D, V2.2D

  (20) 0x402ad8 FMLA	V3.2D, V5.2D, V5.2D

  (20) 0x402adc STP	Q2, Q5, [X8]

  (20) 0x402ae0 ADD	X8, X24, X20

  (20) 0x402ae4 ADD	X20, X20, #32

  (20) 0x402ae8 STP	Q2, Q5, [X8]

  (20) 0x402aec B.NE	402a24

(19) 0x402af0 FADD	V2.2D, V3.2D, V4.2D

(19) 0x402af4 LDP	X8, X10, [SP, #64]

(19) 0x402af8 LDP	X30, X9, [X29, #968]

(19) 0x402afc LDUR	W2, [X29, #348]

(19) 0x402b00 FADDP	D2, V2.2D

(19) 0x402b04 LDUR	W3, [X29, #424]

(19) 0x402b08 LDUR	X4, [X29, #336]

(19) 0x402b0c LDUR	X25, [X29, #360]

(19) 0x402b10 STUR	D2, [X29, #480]

(19) 0x402b14 CMP	X9, X10

(19) 0x402b18 B.EQ	4026a0

(19) 0x402b1c B	402b30

(19) 0x402b20 LDUR	W2, [X29, #348]

(19) 0x402b24 LDUR	W3, [X29, #424]

(19) 0x402b28 LDUR	X4, [X29, #336]

(19) 0x402b2c ORR	X8, XZR, X28

(19) 0x402b30 LDP	X15, X10, [X29, #888]

(19) 0x402b34 ADD	X0, X8, X30

(19) 0x402b38 ADD	X16, X16, X8,LSL #3

(19) 0x402b3c ADD	X14, X7, X8

(19) 0x402b40 ORR	X9, XZR, XZR

(19) 0x402b44 ADD	X13, X0, X4

(19) 0x402b48 ADD	X8, X6, X16

(19) 0x402b4c ADD	X16, X5, X16

(19) 0x402b50 ADD	X17, X21, X0,LSL #3

(19) 0x402b54 ADD	X18, X22, X0,LSL #3

(19) 0x402b58 ADD	X12, X6, X13,LSL #3

(19) 0x402b5c ADD	X13, X5, X13,LSL #3

(19) 0x402b60 ADD	X10, X0, X10

(19) 0x402b64 ADD	X15, X15, X0,LSL #3

(19) 0x402b68 ADD	X0, X25, X0,LSL #3

(19) 0x402b6c ADD	X10, X5, X10,LSL #3

(19) 0x402b70 HINT	#0

(19) 0x402b74 HINT	#0

(19) 0x402b78 HINT	#0

(19) 0x402b7c HINT	#0

  (18) 0x402b80 ADD	X1, X15, X9

  (18) 0x402b84 LDR	D5, [X12, X9]

  (18) 0x402b88 LDR	D19, [X13, X9]

  (18) 0x402b8c LDR	D6, [X8, X9]

  (18) 0x402b90 ADDS	X14, X14, #1

  (18) 0x402b94 LDR	D20, [X10, X9]

  (18) 0x402b98 LDP	D4, D3, [X1, #1016]

  (18) 0x402b9c ADD	X1, X16, X9

  (18) 0x402ba0 LDUR	D18, [X1, #504]

  (18) 0x402ba4 FADD	D7, D3, D0

  (18) 0x402ba8 FADD	D16, D4, D5

  (18) 0x402bac FADD	D7, D7, D16

  (18) 0x402bb0 LDP	D17, D16, [X1]

  (18) 0x402bb4 FADD	D7, D7, D6

  (18) 0x402bb8 FMUL	D3, D16, D3

  (18) 0x402bbc FMADD	D3, D18, D4, D3

  (18) 0x402bc0 FMADD	D3, D19, D5, D3

  (18) 0x402bc4 FMADD	D3, D20, D6, D3

  (18) 0x402bc8 FNMSUB	D3, D17, D7, D3

  (18) 0x402bcc STR	D3, [X17, X9]

  (18) 0x402bd0 LDR	D4, [X1]

  (18) 0x402bd4 FSUB	D3, D4, S3

  (18) 0x402bd8 STR	D3, [X18, X9]

  (18) 0x402bdc STR	D3, [X0, X9]

  (18) 0x402be0 LDR	D4, [X18, X9]

  (18) 0x402be4 ADD	X9, X9, #8

  (18) 0x402be8 FMADD	D2, D4, D3, D2

  (18) 0x402bec STUR	D2, [X29, #480]

  (18) 0x402bf0 B.CC	402b80

(19) 0x402bf4 B	4026a0

(19) 0x402bf8 LDUR	W2, [X29, #348]

(19) 0x402bfc LDUR	W3, [X29, #424]

(19) 0x402c00 LDUR	X4, [X29, #336]

(19) 0x402c04 ORR	X8, XZR, X28

(19) 0x402c08 LDUR	X16, [X29, #416]

(19) 0x402c0c B	402b30

(19) 0x402c10 LDUR	W2, [X29, #348]

(19) 0x402c14 LDUR	W3, [X29, #424]

(19) 0x402c18 LDUR	X4, [X29, #336]

(19) 0x402c1c ORR	X8, XZR, X28

(19) 0x402c20 LDUR	X6, [X29, #320]

(19) 0x402c24 LDR	X5, [SP, #200]

(19) 0x402c28 LDR	X7, [SP, #184]

(19) 0x402c2c LDUR	X16, [X29, #416]

(19) 0x402c30 B	402b30

(19) 0x402c34 LDUR	W2, [X29, #348]

(19) 0x402c38 LDUR	W3, [X29, #424]

(19) 0x402c3c LDUR	X4, [X29, #336]

(19) 0x402c40 ORR	X8, XZR, X28

(19) 0x402c44 LDUR	X6, [X29, #320]

(19) 0x402c48 LDR	X5, [SP, #200]

(19) 0x402c4c LDR	X7, [SP, #184]

(19) 0x402c50 LDP	X22, X21, [SP, #160]

(19) 0x402c54 LDUR	X16, [X29, #416]

(19) 0x402c58 B	402b30

(19) 0x402c5c LDP	X28, X25, [X29, #864]

(19) 0x402c60 LDUR	W2, [X29, #348]

(19) 0x402c64 LDUR	W3, [X29, #424]

(19) 0x402c68 ORR	X8, XZR, X28

(19) 0x402c6c LDUR	X4, [X29, #336]

(19) 0x402c70 LDUR	X6, [X29, #320]

(19) 0x402c74 LDR	X5, [SP, #200]

(19) 0x402c78 LDR	X7, [SP, #184]

(19) 0x402c7c LDP	X22, X21, [SP, #160]

(19) 0x402c80 LDUR	X30, [X29, #456]

(19) 0x402c84 LDUR	X16, [X29, #416]

(19) 0x402c88 B	402b30

0x402c8c LDR	W19, [SP, #20]

0x402c90 ADRP	X0,

0x402c94 ADD	X0, X0, #944

0x402c98 ORR	W1, WZR, W19

0x402c9c BL	401750

0x402ca0 SUB	X8, X29, #32

0x402ca4 ADRP	X6,

0x402ca8 ADRP	X0,

0x402cac ADD	X0, X0, #968

0x402cb0 ADRP	X5, 402cb0

0x402cb4 ADD	X5, X5, #1200

0x402cb8 ORR	W1, WZR, W19

0x402cbc STUR	X8, [X29, #472]

0x402cc0 SUB	X4, X29, #40

0x402cc4 MOVZ	W2, #1

0x402cc8 MOVZ	W3, #8

0x402ccc LDR	X6, [X6, #4016]

0x402cd0 BL	401720

0x402cd4 CMP	W0, #2

0x402cd8 B.EQ	402d14

0x402cdc LDR	X8, [SP, #24]

0x402ce0 CMP	W0, #1

0x402ce4 B.NE	402d40

0x402ce8 LDR	D0, [X8]

0x402cec LDUR	D1, [X29, #480]

0x402cf0 ADRP	X2,

0x402cf4 ADRP	X0,

0x402cf8 ADD	X0, X0, #968

0x402cfc ORR	W1, WZR, W19

0x402d00 FADD	D0, D1, D0

0x402d04 STR	D0, [X8]

0x402d08 LDR	X2, [X2, #4016]

0x402d0c BL	4015e0

0x402d10 B	402d40

0x402d14 LDR	X11, [SP, #24]

0x402d18 LDUR	D0, [X29, #480]

0x402d1c LDR	D1, [X11]

(17) 0x402d20 FADD	D2, D1, D0

(17) 0x402d24 FMOV	X9, D1

(17) 0x402d28 ORR	X10, XZR, X9

(17) 0x402d2c FMOV	X8, D2

(17) 0x402d30 CAS	X10, X8, [X11]

(17) 0x402d34 FMOV	D1, X10

(17) 0x402d38 CMP	X10, X9

(17) 0x402d3c B.NE	402d20

0x402d40 LDP	X20, X19, [SP, #480]

0x402d44 LDP	X22, X21, [SP, #464]

0x402d48 LDP	X24, X23, [SP, #448]

0x402d4c LDP	X26, X25, [SP, #432]

0x402d50 LDP	X28, X27, [SP, #416]

0x402d54 LDP	X29, X30, [SP, #400]

0x402d58 ADD	SP, SP, #496

0x402d5c RET

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run armclang_3

Source file and lines	cg.cpp:59-68
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-118-5752/intel/TeaLeaf/build/TeaLeaf/src/omp/cg.cpp:59-68.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 22.33 to 1.83 cycles (12.18x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 55% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 22.33 to 16.17 cycles (1.38x speedup).

Details

Store and arithmetical VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 22.33 to 2.00 cycles (11.17x speedup).

Matching between your function (in the source code) and the binary function

The binary function is composed of 1 FP arithmetical operations:

1: addition or subtraction

The binary function is loading 268 bytes. The binary function is storing 400 bytes.

Arithmetic intensity

Arithmetic intensity is 0.00 FP operations per loaded or stored byte.

General properties

nb instructions	161
loop length	644
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

19.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	6.00	6.00	13.17	13.17	13.17	13.17	13.17	13.17	1.25	1.25	1.25	1.25	22.33	22.33	22.33	18.50	18.50
cycles	6.00	6.00	13.17	13.17	13.17	13.17	13.17	13.17	1.25	1.25	1.25	1.25	22.33	22.33	22.33	18.50	18.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	19.75
Overall L1	22.33

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	33%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

INT+FP

all	1%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 22.33 cycles. At this rate:

12% of peak load performance is reached (12.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
37% of peak store performance is reached (17.91 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4024d0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
SUB SP, SP, #496	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X29, X30, [SP, #400]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X28, X27, [SP, #416]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X26, X25, [SP, #432]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X24, X23, [SP, #448]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X22, X21, [SP, #464]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X20, X19, [SP, #480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #400	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDRSW X28, [X3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W8, [X2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB W8, W8, W28	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP W28, W8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 402d40 <_Z7cg_initiiiiddPdPKdS1_S_S_S_S_S_S_.omp_outlined.7+0x870>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [X29, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W1, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X20, XZR, X4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X22, XZR, X5	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X21, XZR, X6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X19, XZR, X7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADRP X0, <42f51c>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #920	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X3, X29, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X4, X29, #12	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X5, X29, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X6, X29, #20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STUR XZR, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X9, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORN W9, WZR, W28	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W2, #34	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W7, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STR W1, [SP, #20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD W23, W8, W9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MOVZ W8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP W23, WZR, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP WZR, W8, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR W8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 401520 <@plt_start@+0x80>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP W8, W3, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP W8, W23	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CSEL W2, W8, W23, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD W8, W2, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP W3, W8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.CS 402c8c <_Z7cg_initiiiiddPdPKdS1_S_S_S_S_S_S_.omp_outlined.7+0x7bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDRSW X4, [X20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SUB W8, W4, W28	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP W28, W8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 402c8c <_Z7cg_initiiiiddPdPKdS1_S_S_S_S_S_S_.omp_outlined.7+0x7bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X10, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X9, X8, [X29, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X14, [X22]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
MOVZ W12, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD X13, X28, X4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD W15, W3, W28	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SUB X16, X29, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVI D2, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FMOV D0, #1.0000000	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FMOV V1.2D, #1.0000000	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
SUB X7, X28, X4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR W11, WZR, WZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X12, X12, X28,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X6, [X21]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X5, [X19]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
STUR X13, [X29, #368]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
UBFM X13, X4, #60, #59	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X16, X16, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X13, X13, X28,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR X16, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR W15, [SP, #196]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STUR X28, [X29, #352]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STUR W2, [X29, #348]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X7, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X21, [X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X22, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X25, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD X9, X14, X12	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X8, X6, X13	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X10, X14, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X14, X4, [X29, #840]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STUR X6, [X29, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X5, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X9, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
SUB X9, X6, X28,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X8, X9, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
SUB X9, X5, X28,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X8, X21, X28,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X22, X21, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STUR X25, [X29, #360]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X8, X9, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
SUB X9, X22, X28,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X8, X25, X28,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X8, X9, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X8, X5, X13	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X9, X5, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X8, X5, X12	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X8, X9, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
SUB X8, X4, X28,LSL #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X9, X6, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STUR X8, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
AND X8, X8, #8062	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X9, X10, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X10, X5, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X9, X5, X28,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X8, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X8, X8, X28	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X9, X10, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
SUB X9, XZR, X4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X8, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
MADD W8, W4, W15, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
STUR X9, [X29, #384]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X9, X14, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STUR X9, [X29, #376]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
B 4026b8 <_Z7cg_initiiiiddPdPKdS1_S_S_S_S_S_S_.omp_outlined.7+0x1e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
LDR W19, [SP, #20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADRP X0, <42fc90>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #944	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR W1, WZR, W19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 401750 <@plt_start@+0x2b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X8, X29, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADRP X6, <42fca4>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X0, <42fca8>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #968	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADRP X5, 402cb0 <_Z7cg_initiiiiddPdPKdS1_S_S_S_S_S_S_.omp_outlined.7+0x7e0>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (50.0%)
ADD X5, X5, #1200	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR W1, WZR, W19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STUR X8, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
SUB X4, X29, #40	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W2, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W3, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X6, [X6, #4016]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 401720 <@plt_start@+0x280>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W0, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 402d14 <_Z7cg_initiiiiddPdPKdS1_S_S_S_S_S_S_.omp_outlined.7+0x844>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP W0, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 402d40 <_Z7cg_initiiiiddPdPKdS1_S_S_S_S_S_S_.omp_outlined.7+0x870>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D0, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDUR D1, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
ADRP X2, <42fcf0>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X0, <42fcf4>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #968	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR W1, WZR, W19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
FADD D0, D1, D0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
STR D0, [X8]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDR X2, [X2, #4016]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 4015e0 <@plt_start@+0x140>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 402d40 <_Z7cg_initiiiiddPdPKdS1_S_S_S_S_S_S_.omp_outlined.7+0x870>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X11, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR D0, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDR D1, [X11]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDP X20, X19, [SP, #480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X22, X21, [SP, #464]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X24, X23, [SP, #448]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X26, X25, [SP, #432]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X28, X27, [SP, #416]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X29, X30, [SP, #400]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
ADD SP, SP, #496	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run armclang_3

Source file and lines	cg.cpp:59-68
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-118-5752/intel/TeaLeaf/build/TeaLeaf/src/omp/cg.cpp:59-68.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 22.33 to 2.00 cycles (11.17x speedup).

Matching between your function (in the source code) and the binary function

The binary function is composed of 1 FP arithmetical operations:

1: addition or subtraction

The binary function is loading 268 bytes. The binary function is storing 400 bytes.

Arithmetic intensity

Arithmetic intensity is 0.00 FP operations per loaded or stored byte.

General properties

nb instructions	161
loop length	644
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

19.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	6.00	6.00	13.17	13.17	13.17	13.17	13.17	13.17	1.25	1.25	1.25	1.25	22.33	22.33	22.33	18.50	18.50
cycles	6.00	6.00	13.17	13.17	13.17	13.17	13.17	13.17	1.25	1.25	1.25	1.25	22.33	22.33	22.33	18.50	18.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	19.75
Overall L1	22.33

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	33%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

INT+FP

all	1%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 22.33 cycles. At this rate:

12% of peak load performance is reached (12.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
37% of peak store performance is reached (17.91 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4024d0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
SUB SP, SP, #496	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X29, X30, [SP, #400]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X28, X27, [SP, #416]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X26, X25, [SP, #432]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X24, X23, [SP, #448]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X22, X21, [SP, #464]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X20, X19, [SP, #480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #400	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDRSW X28, [X3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W8, [X2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB W8, W8, W28	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP W28, W8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 402d40 <_Z7cg_initiiiiddPdPKdS1_S_S_S_S_S_S_.omp_outlined.7+0x870>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [X29, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W1, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X20, XZR, X4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X22, XZR, X5	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X21, XZR, X6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X19, XZR, X7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADRP X0, <42f51c>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #920	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X3, X29, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X4, X29, #12	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X5, X29, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X6, X29, #20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STUR XZR, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X9, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORN W9, WZR, W28	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W2, #34	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W7, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STR W1, [SP, #20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD W23, W8, W9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MOVZ W8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP W23, WZR, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP WZR, W8, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR W8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 401520 <@plt_start@+0x80>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP W8, W3, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP W8, W23	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CSEL W2, W8, W23, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD W8, W2, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP W3, W8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.CS 402c8c <_Z7cg_initiiiiddPdPKdS1_S_S_S_S_S_S_.omp_outlined.7+0x7bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDRSW X4, [X20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SUB W8, W4, W28	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP W28, W8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 402c8c <_Z7cg_initiiiiddPdPKdS1_S_S_S_S_S_S_.omp_outlined.7+0x7bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X10, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X9, X8, [X29, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X14, [X22]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
MOVZ W12, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD X13, X28, X4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD W15, W3, W28	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SUB X16, X29, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVI D2, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FMOV D0, #1.0000000	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FMOV V1.2D, #1.0000000	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
SUB X7, X28, X4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR W11, WZR, WZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X12, X12, X28,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X6, [X21]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X5, [X19]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
STUR X13, [X29, #368]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
UBFM X13, X4, #60, #59	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X16, X16, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X13, X13, X28,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR X16, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR W15, [SP, #196]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STUR X28, [X29, #352]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STUR W2, [X29, #348]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X7, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X21, [X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X22, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X25, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD X9, X14, X12	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X8, X6, X13	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X10, X14, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X14, X4, [X29, #840]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STUR X6, [X29, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X5, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X9, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
SUB X9, X6, X28,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X8, X9, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
SUB X9, X5, X28,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X8, X21, X28,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X22, X21, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STUR X25, [X29, #360]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X8, X9, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
SUB X9, X22, X28,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X8, X25, X28,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X8, X9, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X8, X5, X13	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X9, X5, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X8, X5, X12	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X8, X9, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
SUB X8, X4, X28,LSL #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X9, X6, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STUR X8, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
AND X8, X8, #8062	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X9, X10, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X10, X5, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X9, X5, X28,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X8, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X8, X8, X28	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X9, X10, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
SUB X9, XZR, X4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X8, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
MADD W8, W4, W15, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
STUR X9, [X29, #384]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X9, X14, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STUR X9, [X29, #376]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
B 4026b8 <_Z7cg_initiiiiddPdPKdS1_S_S_S_S_S_S_.omp_outlined.7+0x1e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
LDR W19, [SP, #20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADRP X0, <42fc90>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #944	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR W1, WZR, W19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 401750 <@plt_start@+0x2b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X8, X29, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADRP X6, <42fca4>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X0, <42fca8>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #968	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADRP X5, 402cb0 <_Z7cg_initiiiiddPdPKdS1_S_S_S_S_S_S_.omp_outlined.7+0x7e0>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (50.0%)
ADD X5, X5, #1200	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR W1, WZR, W19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STUR X8, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
SUB X4, X29, #40	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W2, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W3, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X6, [X6, #4016]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 401720 <@plt_start@+0x280>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W0, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 402d14 <_Z7cg_initiiiiddPdPKdS1_S_S_S_S_S_S_.omp_outlined.7+0x844>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP W0, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 402d40 <_Z7cg_initiiiiddPdPKdS1_S_S_S_S_S_S_.omp_outlined.7+0x870>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D0, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDUR D1, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
ADRP X2, <42fcf0>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X0, <42fcf4>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #968	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR W1, WZR, W19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
FADD D0, D1, D0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
STR D0, [X8]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDR X2, [X2, #4016]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 4015e0 <@plt_start@+0x140>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 402d40 <_Z7cg_initiiiiddPdPKdS1_S_S_S_S_S_S_.omp_outlined.7+0x870>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X11, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR D0, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDR D1, [X11]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDP X20, X19, [SP, #480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X22, X21, [SP, #464]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X24, X23, [SP, #448]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X26, X25, [SP, #432]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X28, X27, [SP, #416]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X29, X30, [SP, #400]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
ADD SP, SP, #496	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼cg_init(int, int, int, int, double, double, double, double const, double const, double, double, double, double, double, double*) [clone .omp_outlined.7]–	0.01	0.02
○Loop 17 - cg.cpp:59-59 - exec	0.00	0.00
▼Loop 19 - cg.cpp:61-68 - exec–	0.00	0.00
○Loop 20 - cg.cpp:64-68 - exec	0.01	0.02
○Loop 18 - cg.cpp:62-68 - exec	0.00	0.00

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ASM code

Code clean check

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Vectorization

Details

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Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code