OV - exec - Function calculate_residual(int, int, int, double const*, double const*, double*, double const*, double const*) [clone ._omp

	Function: calculate_residual(int, int, int, double const, double const, double, double const, do ...	Module: exec	Source: solver_methods.cpp:66-72	Coverage (incl. loops): 0.01% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-118-5752/intel/TeaLeaf/build/TeaLeaf/src/omp/solver_methods.cpp: 66 - 72

--------------------------------------------------------------------------------

66:   #pragma omp parallel for

67: #endif

68:   for (int jj = halo_depth; jj < y - halo_depth; ++jj) {

69:     for (int kk = halo_depth; kk < x - halo_depth; ++kk) {

70:       const int index = kk + jj * x;

71:       const double smvp = tealeaf_SMVP(u);

72:       r[index] = u0[index] - smvp;

0x408d60 STP	X29, X30, [SP, #848]!

0x408d64 ADD	X29, SP, #0

0x408d68 STP	X19, X20, [SP, #16]

0x408d6c ORR	X20, XZR, X0

0x408d70 BL	401910

0x408d74 ORR	W19, WZR, W0

0x408d78 BL	4018a0

0x408d7c LDP	W1, W2, [X20, #44]

0x408d80 ORR	W15, WZR, W0

0x408d84 SUB	W1, W1, W2,LSL #1

0x408d88 SDIV	W0, W1, W19

0x408d8c MSUB	W1, W0, W19, W1

0x408d90 CMP	W15, W1

0x408d94 B.LT	4090dc

0x408d98 MADD	W15, W0, W15, W1

0x408d9c ADD	W0, W0, W15

0x408da0 CMP	W15, W0

0x408da4 B.GE	409034

0x408da8 STP	X25, X26, [SP, #64]

0x408dac ADD	W15, W2, W15

0x408db0 ADD	W19, W2, W0

0x408db4 LDR	W26, [X20, #40]

0x408db8 LDP	X14, X30, [X20]

0x408dbc LDP	X18, X17, [X20, #16]

0x408dc0 SUB	W4, W26, W2

0x408dc4 LDR	X16, [X20, #32]

0x408dc8 CMP	W2, W4

0x408dcc B.GE	4090e8

0x408dd0 SUB	W3, W4, W2

0x408dd4 MADD	W1, W26, W15, WZR

0x408dd8 STP	X27, X28, [SP, #80]

0x408ddc SBFM	X27, X26, #61, #31

0x408de0 FMOV	V31.2D, #1.0000000

0x408de4 AND	W6, W3, #1951

0x408de8 SBFM	X5, X2, #0, #31

0x408dec SUB	X0, X14, W26,SXTW #3

0x408df0 SUB	W4, W4, W2

0x408df4 ADD	W2, W6, W2

0x408df8 STP	X21, X22, [SP, #32]

0x408dfc ADD	X21, X27, X16

0x408e00 ORR	W25, WZR, W1

0x408e04 ADD	X1, X5, W1,SXTW

0x408e08 ADD	X5, X21, #8

0x408e0c ADD	X20, X27, X14

0x408e10 FMOV	D30, D31

0x408e14 UBFM	W13, W3, #1, #31

0x408e18 UBFM	X1, X1, #61, #60

0x408e1c STR	W2, [SP, #160]

0x408e20 AND	W2, W3, #0

0x408e24 UBFM	X13, X13, #60, #59

0x408e28 STP	X0, X5, [SP, #136]

0x408e2c ADD	X5, X20, #8

0x408e30 ADD	X22, X17, #8

0x408e34 STR	W2, [SP, #132]

0x408e38 ADD	X2, X30, #8

0x408e3c STR	X5, [SP, #120]

0x408e40 ADD	X5, X0, #8

0x408e44 STR	X2, [SP, #96]

0x408e48 ADD	X2, X16, #8

0x408e4c STR	X5, [SP, #112]

0x408e50 UBFM	X5, X4, #61, #60

0x408e54 ORR	X6, XZR, X5

0x408e58 STP	X23, X24, [SP, #48]

0x408e5c ADD	X24, X14, #8

0x408e60 SUB	X23, X14, #8

0x408e64 STR	X2, [SP, #104]

0x408e68 SUB	X2, X18, X14

0x408e6c CMP	X2, #16

0x408e70 CSINC	W2, WZR, WZR, #9

0x408e74 STR	W2, [SP, #128]

    (207) 0x408e78 CMP	W3, #1

    (207) 0x408e7c B.EQ	40904c

  (208) 0x408e80 LDR	X28, [SP, #144]

  (208) 0x408e84 STR	X6, [SP, #152]

  (208) 0x408e88 STR	W3, [SP, #164]

  (208) 0x408e8c STR	X0, [SP, #168]

    (210) 0x408e90 LDR	X0, [SP, #96]

    (210) 0x408e94 ADD	X2, X18, X1

    (210) 0x408e98 ADD	X4, X28, X1

    (210) 0x408e9c LDR	W3, [SP, #128]

    (210) 0x408ea0 ADD	X0, X0, X1

    (210) 0x408ea4 CMP	X0, X2

    (210) 0x408ea8 LDR	X0, [SP, #104]

    (210) 0x408eac ADD	X0, X0, X1

    (210) 0x408eb0 CCMP	X0, X2, #4, #1

    (210) 0x408eb4 CSINC	W5, WZR, WZR, #0

    (210) 0x408eb8 CMP	W3, #0

    (210) 0x408ebc LDP	X0, X3, [SP, #112]

    (210) 0x408ec0 ADD	X0, X0, X1

    (210) 0x408ec4 ADD	X3, X3, X1

    (210) 0x408ec8 CCMP	X0, X2, #4, #1

    (210) 0x408ecc CSINC	W0, WZR, WZR, #0

    (210) 0x408ed0 CMP	X3, X2

    (210) 0x408ed4 ADD	X3, X22, X1

    (210) 0x408ed8 CCMP	X4, X2, #4, #1

    (210) 0x408edc SUB	X4, X2, X3

    (210) 0x408ee0 CCMP	X4, #8, #0, #1

    (210) 0x408ee4 AND	W0, W5, W0

    (210) 0x408ee8 CSINC	W4, WZR, WZR, #9

    (210) 0x408eec ANDS	WZR, W4, W0

    (210) 0x408ef0 B.EQ	409040

    (210) 0x408ef4 LDR	X4, [SP, #136]

    (210) 0x408ef8 MOVZ	X0, #0

    (210) 0x408efc ADD	X12, X17, X1

    (210) 0x408f00 ADD	X11, X21, X1

    (210) 0x408f04 ADD	X10, X16, X1

    (210) 0x408f08 ADD	X9, X14, X1

    (210) 0x408f0c ADD	X8, X24, X1

    (210) 0x408f10 ADD	X7, X23, X1

    (210) 0x408f14 ADD	X6, X20, X1

    (210) 0x408f18 ADD	X5, X4, X1

    (210) 0x408f1c ADD	X4, X30, X1

      (209) 0x408f20 LDR	Q29, [X3, X0]

      (209) 0x408f24 LDR	Q6, [X12, X0]

      (209) 0x408f28 LDR	Q3, [X7, X0]

      (209) 0x408f2c LDR	Q22, [X8, X0]

      (209) 0x408f30 LDR	Q27, [X11, X0]

      (209) 0x408f34 FADD	V5.2D, V29.2D, V6.2D

      (209) 0x408f38 LDR	Q26, [X10, X0]

      (209) 0x408f3c FMUL	V3.2D, V3.2D, V6.2D

      (209) 0x408f40 LDR	Q28, [X5, X0]

      (209) 0x408f44 FADD	V5.2D, V5.2D, V31.2D

      (209) 0x408f48 LDR	Q23, [X9, X0]

      (209) 0x408f4c FMLA	V3.2D, V29.2D, V22.2D

      (209) 0x408f50 LDR	Q2, [X6, X0]

      (209) 0x408f54 FADD	V4.2D, V27.2D, V26.2D

      (209) 0x408f58 LDR	Q1, [X4, X0]

      (209) 0x408f5c FMUL	V28.2D, V28.2D, V26.2D

      (209) 0x408f60 FADD	V4.2D, V5.2D, V4.2D

      (209) 0x408f64 FNEG	V3.2D, V3.2D

      (209) 0x408f68 FMLA	V28.2D, V27.2D, V2.2D

      (209) 0x408f6c FMLA	V3.2D, V4.2D, V23.2D

      (209) 0x408f70 FSUB	V28.2D, V3.2D, V28.2D

      (209) 0x408f74 FSUB	V28.2D, V1.2D, V28.2D

      (209) 0x408f78 STR	Q28, [X2, X0]

      (209) 0x408f7c ADD	X0, X0, #16

      (209) 0x408f80 CMP	X13, X0

      (209) 0x408f84 B.NE	408f20

    (210) 0x408f88 LDR	W0, [SP, #132]

    (210) 0x408f8c CBZ	W0, 409010

    (210) 0x408f90 LDR	W0, [SP, #160]

    (210) 0x408f94 ADD	W3, W0, W25

    (210) 0x408f98 SBFM	X0, X3, #0, #31

    (210) 0x408f9c ADD	W4, W26, W3

    (210) 0x408fa0 ADD	X0, X0, #1

    (210) 0x408fa4 SBFM	X4, X4, #61, #31

    (210) 0x408fa8 UBFM	X0, X0, #61, #60

    (210) 0x408fac SUB	W3, W3, W26

    (210) 0x408fb0 SUB	X2, X0, #8

    (210) 0x408fb4 LDR	D24, [X16, X4]

    (210) 0x408fb8 ADD	X5, X14, X0

    (210) 0x408fbc LDR	D25, [X17, X2]

    (210) 0x408fc0 LDR	D0, [X17, X0]

    (210) 0x408fc4 LDR	D20, [X16, X2]

    (210) 0x408fc8 LDUR	D16, [X5, #496]

    (210) 0x408fcc FADD	D19, D0, D25

    (210) 0x408fd0 LDR	D7, [X14, X0]

    (210) 0x408fd4 FADD	D18, D24, D20

    (210) 0x408fd8 LDR	D6, [X14, X3,SXTW #3]

    (210) 0x408fdc FMUL	D16, D25, D16

    (210) 0x408fe0 LDR	D17, [X14, X2]

    (210) 0x408fe4 FADD	D19, D19, D31

    (210) 0x408fe8 LDR	D5, [X14, X4]

    (210) 0x408fec FMUL	D6, D20, D6

    (210) 0x408ff0 LDR	D4, [X30, X2]

    (210) 0x408ff4 FMADD	D7, D0, D7, D16

    (210) 0x408ff8 FADD	D18, D19, D18

    (210) 0x408ffc FMADD	D5, D24, D5, D6

    (210) 0x409000 FNMSUB	D7, D18, D17, D7

    (210) 0x409004 FSUB	D5, D7, S5

    (210) 0x409008 FSUB	D4, D4, S5

    (210) 0x40900c STR	D4, [X18, X2]

    (210) 0x409010 ADD	W15, W15, #1

    (210) 0x409014 ADD	X1, X1, X27

    (210) 0x409018 ADD	W25, W25, W26

    (210) 0x40901c CMP	W19, W15

    (210) 0x409020 B.GT	408e90

(211) 0x409024 LDP	X21, X22, [SP, #32]

(211) 0x409028 LDP	X23, X24, [SP, #48]

(211) 0x40902c LDP	X25, X26, [SP, #64]

(211) 0x409030 LDP	X27, X28, [SP, #80]

(211) 0x409034 LDP	X19, X20, [SP, #16]

(211) 0x409038 LDP	X29, X30, [SP], #176

(211) 0x40903c RET

  (208) 0x409040 LDR	X6, [SP, #152]

  (208) 0x409044 LDR	X0, [SP, #168]

  (208) 0x409048 LDR	W3, [SP, #164]

    (207) 0x40904c ADD	X4, X6, X1

    (207) 0x409050 ORR	X2, XZR, X1

    (207) 0x409054 HINT	#0

    (207) 0x409058 HINT	#0

    (207) 0x40905c HINT	#0

      (206) 0x409060 LDR	D22, [X22, X2]

      (206) 0x409064 LDR	D21, [X17, X2]

      (206) 0x409068 LDR	D29, [X21, X2]

      (206) 0x40906c LDR	D27, [X16, X2]

      (206) 0x409070 FADD	D3, D22, D21

      (206) 0x409074 LDR	D1, [X23, X2]

      (206) 0x409078 LDR	D28, [X24, X2]

      (206) 0x40907c FADD	D26, D29, D27

      (206) 0x409080 LDR	D0, [X0, X2]

      (206) 0x409084 FADD	D3, D3, D30

      (206) 0x409088 FMUL	D1, D21, D1

      (206) 0x40908c LDR	D2, [X14, X2]

      (206) 0x409090 LDR	D23, [X20, X2]

      (206) 0x409094 FMUL	D0, D27, D0

      (206) 0x409098 LDR	D25, [X30, X2]

      (206) 0x40909c FMADD	D28, D22, D28, D1

      (206) 0x4090a0 FADD	D26, D3, D26

      (206) 0x4090a4 FMADD	D23, D29, D23, D0

      (206) 0x4090a8 FNMSUB	D28, D26, D2, D28

      (206) 0x4090ac FSUB	D23, D28, S23

      (206) 0x4090b0 FSUB	D25, D25, S23

      (206) 0x4090b4 STR	D25, [X18, X2]

      (206) 0x4090b8 ADD	X2, X2, #8

      (206) 0x4090bc CMP	X2, X4

      (206) 0x4090c0 B.NE	409060

    (207) 0x4090c4 ADD	W15, W15, #1

    (207) 0x4090c8 ADD	X1, X1, X27

    (207) 0x4090cc ADD	W25, W25, W26

    (207) 0x4090d0 CMP	W19, W15

    (207) 0x4090d4 B.GT	408e78

(211) 0x4090d8 B	409024

0x4090dc ADD	W0, W0, #1

0x4090e0 MOVZ	W1, #0

0x4090e4 B	408d98

0x4090e8 LDP	X25, X26, [SP, #64]

0x4090ec B	409034

Coverage (%)	Name	Source Location	Module
►100.00+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	solver_methods.cpp:66-72
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-118-5752/intel/TeaLeaf/build/TeaLeaf/src/omp/solver_methods.cpp:66-72.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is probably not vectorized. Only 50% of vector register length is used (average across all VPU instructions).

Details

Store and arithmetical VPU instructions are used in scalar version (process only one data element in vector registers).

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.50 to 1.00 cycles (12.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 68 bytes. The binary function is storing 156 bytes.

General properties

nb instructions	75
loop length	300
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

9.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	3.50	3.50	8.25	8.08	8.17	8.17	8.17	8.17	0.50	0.50	0.50	0.50	7.00	7.00	6.00	7.00	7.00
cycles	3.50	3.50	8.25	8.08	8.17	8.17	8.17	8.17	0.50	0.50	0.50	0.50	7.00	7.00	6.00	7.00	7.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	9.38
Overall L1	9.38-12.50

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
other	0%

all	50%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

INT+FP

all	1%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	5%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.50 cycles. At this rate:

5% of peak load performance is reached (5.44 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
26% of peak store performance is reached (12.48 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 408d60

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #848]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 401910 <@plt_start@+0x300>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W19, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4018a0 <@plt_start@+0x290>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP W1, W2, [X20, #44]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ORR W15, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SUB W1, W1, W2,LSL #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SDIV W0, W1, W19	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	N/A
MSUB W1, W0, W19, W1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
CMP W15, W1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 4090dc <_Z18calculate_residualiiiPKdS0_PdS0_S0_._omp_fn.0+0x37c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W15, W0, W15, W1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD W0, W0, W15	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP W15, W0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 409034 <_Z18calculate_residualiiiPKdS0_PdS0_S0_._omp_fn.0+0x2d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD W15, W2, W15	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W19, W2, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
LDR W26, [X20, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X14, X30, [X20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X18, X17, [X20, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
SUB W4, W26, W2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
LDR X16, [X20, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP W2, W4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 4090e8 <_Z18calculate_residualiiiPKdS0_PdS0_S0_._omp_fn.0+0x388>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W3, W4, W2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MADD W1, W26, W15, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
SBFM X27, X26, #61, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
FMOV V31.2D, #1.0000000	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
AND W6, W3, #1951	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SBFM X5, X2, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
SUB X0, X14, W26,SXTW #3	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
SUB W4, W4, W2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W2, W6, W2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X21, X27, X16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR W25, WZR, W1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD X1, X5, W1,SXTW	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (50.0%)
ADD X5, X21, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X20, X27, X14	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
FMOV D30, D31	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
UBFM W13, W3, #1, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
UBFM X1, X1, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR W2, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
AND W2, W3, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
UBFM X13, X13, #60, #59	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X0, X5, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X5, X20, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X22, X17, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR W2, [SP, #132]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X2, X30, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR X5, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X5, X0, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR X2, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X2, X16, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR X5, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
UBFM X5, X4, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X6, XZR, X5	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X24, X14, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X23, X14, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR X2, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
SUB X2, X18, X14	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CMP X2, #16	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
CSINC W2, WZR, WZR, #9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STR W2, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD W0, W0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W1, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
B 408d98 <_Z18calculate_residualiiiPKdS0_PdS0_S0_._omp_fn.0+0x38>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
B 409034 <_Z18calculate_residualiiiPKdS0_PdS0_S0_._omp_fn.0+0x2d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	solver_methods.cpp:66-72
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-118-5752/intel/TeaLeaf/build/TeaLeaf/src/omp/solver_methods.cpp:66-72.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is probably not vectorized. Only 50% of vector register length is used (average across all VPU instructions).

Details

Store and arithmetical VPU instructions are used in scalar version (process only one data element in vector registers).

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.50 to 1.00 cycles (12.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 68 bytes. The binary function is storing 156 bytes.

General properties

nb instructions	75
loop length	300
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

9.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	3.50	3.50	8.25	8.08	8.17	8.17	8.17	8.17	0.50	0.50	0.50	0.50	7.00	7.00	6.00	7.00	7.00
cycles	3.50	3.50	8.25	8.08	8.17	8.17	8.17	8.17	0.50	0.50	0.50	0.50	7.00	7.00	6.00	7.00	7.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	9.38
Overall L1	9.38-12.50

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
other	0%

all	50%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

INT+FP

all	1%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	5%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.50 cycles. At this rate:

5% of peak load performance is reached (5.44 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
26% of peak store performance is reached (12.48 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 408d60

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #848]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 401910 <@plt_start@+0x300>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W19, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4018a0 <@plt_start@+0x290>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP W1, W2, [X20, #44]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ORR W15, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SUB W1, W1, W2,LSL #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SDIV W0, W1, W19	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	N/A
MSUB W1, W0, W19, W1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
CMP W15, W1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 4090dc <_Z18calculate_residualiiiPKdS0_PdS0_S0_._omp_fn.0+0x37c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W15, W0, W15, W1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD W0, W0, W15	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP W15, W0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 409034 <_Z18calculate_residualiiiPKdS0_PdS0_S0_._omp_fn.0+0x2d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD W15, W2, W15	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W19, W2, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
LDR W26, [X20, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X14, X30, [X20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X18, X17, [X20, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
SUB W4, W26, W2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
LDR X16, [X20, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP W2, W4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 4090e8 <_Z18calculate_residualiiiPKdS0_PdS0_S0_._omp_fn.0+0x388>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W3, W4, W2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MADD W1, W26, W15, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
SBFM X27, X26, #61, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
FMOV V31.2D, #1.0000000	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
AND W6, W3, #1951	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SBFM X5, X2, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
SUB X0, X14, W26,SXTW #3	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
SUB W4, W4, W2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W2, W6, W2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X21, X27, X16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR W25, WZR, W1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD X1, X5, W1,SXTW	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (50.0%)
ADD X5, X21, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X20, X27, X14	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
FMOV D30, D31	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
UBFM W13, W3, #1, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
UBFM X1, X1, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR W2, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
AND W2, W3, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
UBFM X13, X13, #60, #59	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X0, X5, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X5, X20, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X22, X17, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR W2, [SP, #132]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X2, X30, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR X5, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X5, X0, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR X2, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X2, X16, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR X5, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
UBFM X5, X4, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X6, XZR, X5	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X24, X14, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X23, X14, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR X2, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
SUB X2, X18, X14	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CMP X2, #16	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
CSINC W2, WZR, WZR, #9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STR W2, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD W0, W0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W1, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
B 408d98 <_Z18calculate_residualiiiPKdS0_PdS0_S0_._omp_fn.0+0x38>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
B 409034 <_Z18calculate_residualiiiPKdS0_PdS0_S0_._omp_fn.0+0x2d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼calculate_residual(int, int, int, double const, double const, double, double const, double const*) [clone ._omp_fn.0]–	0.01	0.02
▼Loop 211 - solver_methods.cpp:66-72 - exec–	0.00	0.00
▼Loop 208 - solver_methods.cpp:66-72 - exec–	0.00	0.00
▼Loop 210 - solver_methods.cpp:68-72 - exec–	0.00	0.00
○Loop 209 - solver_methods.cpp:69-72 - exec	0.01	0.02
▼Loop 207 - solver_methods.cpp:66-72 - exec–	0.00	0.00
○Loop 206 - solver_methods.cpp:69-72 - exec	0.00	0.00

Report Configuration

Vectorization

Details

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code