OV - exec - Function update_bottom(int, int, int, int, double*, bool) [clone ._omp

	Function: update_bottom(int, int, int, int, double*, bool) [clone ._omp_fn.0]	Module: exec	Source: local_halos.cpp:58-62	Coverage (incl. loops): 0.01% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-118-5752/intel/TeaLeaf/build/TeaLeaf/src/omp/local_halos.cpp: 58 - 62

--------------------------------------------------------------------------------

58:   #pragma omp parallel for

59: #endif

60:     for (int kk = halo_depth; kk < x - halo_depth; ++kk) {

61:       int base = kk;

62:       buffer[base + (halo_depth - jj - 1) * x] = buffer[base + (halo_depth + jj) * x];

0x4068c8 STP	X29, X30, [SP, #976]!

0x4068cc ADD	X29, SP, #0

0x4068d0 STP	X19, X20, [SP, #16]

0x4068d4 ORR	X20, XZR, X0

0x4068d8 STP	X21, X22, [SP, #32]

0x4068dc LDP	W22, W21, [X0, #8]

0x4068e0 BL	401910

0x4068e4 ORR	W19, WZR, W0

0x4068e8 BL	4018a0

0x4068ec ORR	W1, WZR, W0

0x4068f0 SUB	W2, W22, W21,LSL #1

0x4068f4 SDIV	W4, W2, W19

0x4068f8 MSUB	W2, W4, W19, W2

0x4068fc CMP	W0, W2

0x406900 B.LT	406a08

(132) 0x406904 MADD	W1, W4, W1, WZR

(132) 0x406908 ADD	W3, W2, W1

(132) 0x40690c ADD	W6, W4, W3

(132) 0x406910 CMP	W3, W6

(132) 0x406914 B.GE	4069f8

(132) 0x406918 LDR	W0, [X20, #16]

(132) 0x40691c LDR	X9, [X20]

(132) 0x406920 SUB	W5, W21, W0

(132) 0x406924 ADD	W0, W0, W21

(132) 0x406928 SUB	W5, W5, #1

(132) 0x40692c MADD	W0, W0, W22, WZR

(132) 0x406930 MADD	W5, W5, W22, WZR

(132) 0x406934 SBFM	X5, X5, #0, #31

(132) 0x406938 CMP	W4, #1

(132) 0x40693c B.EQ	406a2c

(132) 0x406940 SBFM	X2, X2, #0, #31

(132) 0x406944 ADD	X2, X2, W21,SXTW

(132) 0x406948 ADD	X1, X2, W1,SXTW

(132) 0x40694c ADD	X8, X5, X1

(132) 0x406950 SBFM	X2, X0, #0, #31

(132) 0x406954 SUB	X0, X8, #1

(132) 0x406958 ADD	X1, X2, X1

(132) 0x40695c SUB	X0, X0, X1

(132) 0x406960 UBFM	X0, X0, #61, #60

(132) 0x406964 CMP	X0, #16

(132) 0x406968 B.LS	406a30

(132) 0x40696c SUB	W0, W4, #1

(132) 0x406970 CMP	W0, #2

(132) 0x406974 B.LS	406a5c

(132) 0x406978 ADD	X5, X9, X1,LSL #3

(132) 0x40697c UBFM	W2, W4, #2, #31

(132) 0x406980 MOVZ	X0, #0

(132) 0x406984 ADD	X3, X9, X8,LSL #3

(132) 0x406988 UBFM	X2, X2, #59, #58

(132) 0x40698c ADD	X7, X5, #16

(132) 0x406990 ADD	X6, X3, #16

(132) 0x406994 HINT	#0

(132) 0x406998 HINT	#0

(132) 0x40699c HINT	#0

  (134) 0x4069a0 LDR	Q30, [X5, X0]

  (134) 0x4069a4 LDR	Q31, [X7, X0]

  (134) 0x4069a8 STR	Q30, [X3, X0]

  (134) 0x4069ac STR	Q31, [X6, X0]

  (134) 0x4069b0 ADD	X0, X0, #32

  (134) 0x4069b4 CMP	X0, X2

  (134) 0x4069b8 B.NE	4069a0

(132) 0x4069bc AND	W0, W4, #1886

(132) 0x4069c0 CMP	W4, W0

(132) 0x4069c4 B.EQ	4069f8

(132) 0x4069c8 ORR	W2, WZR, W0

(132) 0x4069cc SUB	W0, W4, W0

(132) 0x4069d0 WHILELO	P7.D, XZR, X0

(132) 0x4069d4 ADD	X8, X8, X2

(132) 0x4069d8 ADD	X1, X1, X2

(132) 0x4069dc LD1D	{Z31.D}, P7/Z, [X9, X1,LSL #3]

(132) 0x4069e0 ADD	X8, X9, X8,LSL #3

(132) 0x4069e4 ST1D	{Z31.D}, P7, [X8, MUL VL]

(132) 0x4069e8 CNTD	X2, ALL

(132) 0x4069ec WHILELO	P7.D, X2, X0

(132) 0x4069f0 ADD	X1, X9, X1,LSL #3

(132) 0x4069f4 B.NE	406a14

(132) 0x4069f8 LDP	X19, X20, [SP, #16]

(132) 0x4069fc LDP	X21, X22, [SP, #32]

(132) 0x406a00 LDP	X29, X30, [SP], #48

(132) 0x406a04 RET

(132) 0x406a08 ADD	W4, W4, #1

(132) 0x406a0c MOVZ	W2, #0

(132) 0x406a10 B	406904

(132) 0x406a14 LD1D	{Z30.D}, P7/Z, [X1, #1, MUL VL]

(132) 0x406a18 ST1D	{Z30.D}, P7, [X8, #1, MUL VL]

(132) 0x406a1c LDP	X19, X20, [SP, #16]

(132) 0x406a20 LDP	X21, X22, [SP, #32]

(132) 0x406a24 LDP	X29, X30, [SP], #48

(132) 0x406a28 RET

(132) 0x406a2c SBFM	X2, X0, #0, #31

(132) 0x406a30 ADD	W0, W21, W3

(132) 0x406a34 ADD	X2, X9, X2,LSL #3

(132) 0x406a38 ADD	W6, W21, W6

(132) 0x406a3c ADD	X5, X9, X5,LSL #3

(132) 0x406a40 SBFM	X0, X0, #0, #31

  (133) 0x406a44 LDR	D31, [X2, X0,LSL #3]

  (133) 0x406a48 STR	D31, [X5, X0,LSL #3]

  (133) 0x406a4c ADD	X0, X0, #1

  (133) 0x406a50 CMP	W6, W0

  (133) 0x406a54 B.GT	406a44

(132) 0x406a58 B	4069f8

(132) 0x406a5c MOVZ	W0, #0

(132) 0x406a60 B	4069c8

Coverage (%)	Name	Source Location	Module
►97.77+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.27+	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	local_halos.cpp:58-62
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-118-5752/intel/TeaLeaf/build/TeaLeaf/src/omp/local_halos.cpp:58-62.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 58% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 12.50 to 3.12 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.50 to 1.00 cycles (12.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 8 bytes. The binary function is storing 48 bytes.

General properties

nb instructions	15
loop length	60
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.50	1.50	1.83	1.83	1.83	1.83	2.00	1.67	0.00	0.00	0.00	0.00	1.50	1.50	1.00	1.50	1.50
cycles	1.50	1.50	1.83	1.83	1.83	1.83	2.00	1.67	0.00	0.00	0.00	0.00	1.50	1.50	1.00	1.50	1.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	1.88
Overall L1	5.00-12.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.50 cycles. At this rate:

0% of peak load performance is reached (0.64 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
8% of peak store performance is reached (3.84 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4068c8

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #976]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP W22, W21, [X0, #8]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
BL 401910 <@plt_start@+0x300>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W19, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4018a0 <@plt_start@+0x290>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W1, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
SUB W2, W22, W21,LSL #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
SDIV W4, W2, W19	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5-12	5-12.50	scal (25.0%)
MSUB W2, W4, W19, W2	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
CMP W0, W2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.LT 406a08 <_Z13update_bottomiiiiPdb._omp_fn.0+0x140>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	local_halos.cpp:58-62
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-118-5752/intel/TeaLeaf/build/TeaLeaf/src/omp/local_halos.cpp:58-62.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.50 to 1.00 cycles (12.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 8 bytes. The binary function is storing 48 bytes.

General properties

nb instructions	15
loop length	60
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.50	1.50	1.83	1.83	1.83	1.83	2.00	1.67	0.00	0.00	0.00	0.00	1.50	1.50	1.00	1.50	1.50
cycles	1.50	1.50	1.83	1.83	1.83	1.83	2.00	1.67	0.00	0.00	0.00	0.00	1.50	1.50	1.00	1.50	1.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	1.88
Overall L1	5.00-12.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.50 cycles. At this rate:

0% of peak load performance is reached (0.64 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
8% of peak store performance is reached (3.84 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4068c8

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #976]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP W22, W21, [X0, #8]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
BL 401910 <@plt_start@+0x300>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W19, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4018a0 <@plt_start@+0x290>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W1, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
SUB W2, W22, W21,LSL #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
SDIV W4, W2, W19	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5-12	5-12.50	scal (25.0%)
MSUB W2, W4, W19, W2	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
CMP W0, W2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.LT 406a08 <_Z13update_bottomiiiiPdb._omp_fn.0+0x140>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼update_bottom(int, int, int, int, double*, bool) [clone ._omp_fn.0]–	0.01	0.02
▼Loop 132 - local_halos.cpp:58-62 - exec–	0.00	0.01
○Loop 134 - local_halos.cpp:62-62 - exec	0.01	0.01
○Loop 133 - local_halos.cpp:62-62 - exec	0.00	0.00

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code