OV - exec - Function update_top(int, int, int, int, double*, bool) [clone ._omp

	Function: update_top(int, int, int, int, double*, bool) [clone ._omp_fn.0]	Module: exec	Source: local_halos.cpp:42-46	Coverage (incl. loops): 0.01% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-118-5752/intel/TeaLeaf/build/TeaLeaf/src/omp/local_halos.cpp: 42 - 46

--------------------------------------------------------------------------------

42:   #pragma omp parallel for

43: #endif

44:     for (int kk = halo_depth; kk < x - halo_depth; ++kk) {

45:       int base = kk;

46:       buffer[base + (y - halo_depth + jj) * x] = buffer[base + (y - halo_depth - 1 - jj) * x];

0x40672c STP	X29, X30, [SP, #976]!

0x406730 ADD	X29, SP, #0

0x406734 STP	X19, X20, [SP, #16]

0x406738 ORR	X20, XZR, X0

0x40673c STP	X21, X22, [SP, #32]

0x406740 LDR	W22, [X0, #8]

0x406744 LDR	W21, [X0, #16]

0x406748 BL	401910

0x40674c ORR	W19, WZR, W0

0x406750 BL	4018a0

0x406754 ORR	W1, WZR, W0

0x406758 SUB	W2, W22, W21,LSL #1

0x40675c SDIV	W4, W2, W19

0x406760 MSUB	W2, W4, W19, W2

0x406764 CMP	W0, W2

0x406768 B.LT	40686c

(129) 0x40676c MADD	W1, W4, W1, WZR

(129) 0x406770 ADD	W3, W2, W1

(129) 0x406774 ADD	W7, W4, W3

(129) 0x406778 CMP	W3, W7

(129) 0x40677c B.GE	40685c

(129) 0x406780 LDR	W6, [X20, #12]

(129) 0x406784 LDR	W0, [X20, #20]

(129) 0x406788 LDR	X9, [X20]

(129) 0x40678c SUB	W6, W6, W21

(129) 0x406790 SUB	W5, W6, #1

(129) 0x406794 SUB	W5, W5, W0

(129) 0x406798 ADD	W0, W0, W6

(129) 0x40679c MADD	W0, W0, W22, WZR

(129) 0x4067a0 MADD	W6, W5, W22, WZR

(129) 0x4067a4 SBFM	X5, X0, #0, #31

(129) 0x4067a8 CMP	W4, #1

(129) 0x4067ac B.EQ	406890

(129) 0x4067b0 SBFM	X2, X2, #0, #31

(129) 0x4067b4 ADD	X2, X2, W21,SXTW

(129) 0x4067b8 ADD	X1, X2, W1,SXTW

(129) 0x4067bc ADD	X8, X5, X1

(129) 0x4067c0 SBFM	X2, X6, #0, #31

(129) 0x4067c4 SUB	X0, X8, #1

(129) 0x4067c8 ADD	X1, X2, X1

(129) 0x4067cc SUB	X0, X0, X1

(129) 0x4067d0 UBFM	X0, X0, #61, #60

(129) 0x4067d4 CMP	X0, #16

(129) 0x4067d8 B.LS	406894

(129) 0x4067dc SUB	W0, W4, #1

(129) 0x4067e0 CMP	W0, #2

(129) 0x4067e4 B.LS	4068c0

(129) 0x4067e8 ADD	X5, X9, X1,LSL #3

(129) 0x4067ec UBFM	W2, W4, #2, #31

(129) 0x4067f0 MOVZ	X0, #0

(129) 0x4067f4 ADD	X3, X9, X8,LSL #3

(129) 0x4067f8 UBFM	X2, X2, #59, #58

(129) 0x4067fc ADD	X7, X5, #16

(129) 0x406800 ADD	X6, X3, #16

  (131) 0x406804 LDR	Q30, [X5, X0]

  (131) 0x406808 LDR	Q31, [X7, X0]

  (131) 0x40680c STR	Q30, [X3, X0]

  (131) 0x406810 STR	Q31, [X6, X0]

  (131) 0x406814 ADD	X0, X0, #32

  (131) 0x406818 CMP	X0, X2

  (131) 0x40681c B.NE	406804

(129) 0x406820 AND	W0, W4, #1886

(129) 0x406824 CMP	W4, W0

(129) 0x406828 B.EQ	40685c

(129) 0x40682c ORR	W2, WZR, W0

(129) 0x406830 SUB	W0, W4, W0

(129) 0x406834 WHILELO	P7.D, XZR, X0

(129) 0x406838 ADD	X8, X8, X2

(129) 0x40683c ADD	X1, X1, X2

(129) 0x406840 LD1D	{Z31.D}, P7/Z, [X9, X1,LSL #3]

(129) 0x406844 ADD	X8, X9, X8,LSL #3

(129) 0x406848 ST1D	{Z31.D}, P7, [X8, MUL VL]

(129) 0x40684c CNTD	X2, ALL

(129) 0x406850 WHILELO	P7.D, X2, X0

(129) 0x406854 ADD	X1, X9, X1,LSL #3

(129) 0x406858 B.NE	406878

(129) 0x40685c LDP	X19, X20, [SP, #16]

(129) 0x406860 LDP	X21, X22, [SP, #32]

(129) 0x406864 LDP	X29, X30, [SP], #48

(129) 0x406868 RET

(129) 0x40686c ADD	W4, W4, #1

(129) 0x406870 MOVZ	W2, #0

(129) 0x406874 B	40676c

(129) 0x406878 LD1D	{Z30.D}, P7/Z, [X1, #1, MUL VL]

(129) 0x40687c ST1D	{Z30.D}, P7, [X8, #1, MUL VL]

(129) 0x406880 LDP	X19, X20, [SP, #16]

(129) 0x406884 LDP	X21, X22, [SP, #32]

(129) 0x406888 LDP	X29, X30, [SP], #48

(129) 0x40688c RET

(129) 0x406890 SBFM	X2, X6, #0, #31

(129) 0x406894 ADD	W0, W21, W3

(129) 0x406898 ADD	X2, X9, X2,LSL #3

(129) 0x40689c ADD	W7, W21, W7

(129) 0x4068a0 ADD	X5, X9, X5,LSL #3

(129) 0x4068a4 SBFM	X0, X0, #0, #31

  (130) 0x4068a8 LDR	D31, [X2, X0,LSL #3]

  (130) 0x4068ac STR	D31, [X5, X0,LSL #3]

  (130) 0x4068b0 ADD	X0, X0, #1

  (130) 0x4068b4 CMP	W7, W0

  (130) 0x4068b8 B.GT	4068a8

(129) 0x4068bc B	40685c

(129) 0x4068c0 MOVZ	W0, #0

(129) 0x4068c4 B	40682c

Coverage (%)	Name	Source Location	Module
►100.00+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	local_halos.cpp:42-46
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-118-5752/intel/TeaLeaf/build/TeaLeaf/src/omp/local_halos.cpp:42-46.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 52% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 12.50 to 3.12 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.50 to 1.00 cycles (12.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 8 bytes. The binary function is storing 48 bytes.

General properties

nb instructions	16
loop length	64
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.50	1.50	1.83	1.83	1.83	1.83	2.00	1.67	0.00	0.00	0.00	0.00	1.83	1.50	1.67	1.50	1.50
cycles	1.50	1.50	1.83	1.83	1.83	1.83	2.00	1.67	0.00	0.00	0.00	0.00	1.83	1.50	1.67	1.50	1.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	2.00
Overall L1	5.00-12.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.50 cycles. At this rate:

0% of peak load performance is reached (0.64 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
8% of peak store performance is reached (3.84 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 40672c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #976]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDR W22, [X0, #8]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W21, [X0, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
BL 401910 <@plt_start@+0x300>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W19, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4018a0 <@plt_start@+0x290>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W1, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
SUB W2, W22, W21,LSL #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
SDIV W4, W2, W19	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5-12	5-12.50	scal (25.0%)
MSUB W2, W4, W19, W2	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
CMP W0, W2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.LT 40686c <_Z10update_topiiiiPdb._omp_fn.0+0x140>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	local_halos.cpp:42-46
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-118-5752/intel/TeaLeaf/build/TeaLeaf/src/omp/local_halos.cpp:42-46.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.50 to 1.00 cycles (12.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 8 bytes. The binary function is storing 48 bytes.

General properties

nb instructions	16
loop length	64
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.50	1.50	1.83	1.83	1.83	1.83	2.00	1.67	0.00	0.00	0.00	0.00	1.83	1.50	1.67	1.50	1.50
cycles	1.50	1.50	1.83	1.83	1.83	1.83	2.00	1.67	0.00	0.00	0.00	0.00	1.83	1.50	1.67	1.50	1.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	2.00
Overall L1	5.00-12.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.50 cycles. At this rate:

0% of peak load performance is reached (0.64 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
8% of peak store performance is reached (3.84 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 40672c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #976]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDR W22, [X0, #8]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W21, [X0, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
BL 401910 <@plt_start@+0x300>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W19, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4018a0 <@plt_start@+0x290>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W1, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
SUB W2, W22, W21,LSL #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
SDIV W4, W2, W19	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5-12	5-12.50	scal (25.0%)
MSUB W2, W4, W19, W2	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
CMP W0, W2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.LT 40686c <_Z10update_topiiiiPdb._omp_fn.0+0x140>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼update_top(int, int, int, int, double*, bool) [clone ._omp_fn.0]–	0.01	0.02
▼Loop 129 - local_halos.cpp:42-46 - exec–	0.00	0.00
○Loop 131 - local_halos.cpp:46-46 - exec	0.01	0.01
○Loop 130 - local_halos.cpp:46-46 - exec	0.00	0.00

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code