OV - exec - Function update_left(int, int, int, int, double*, bool) [clone ._omp

	Function: update_left(int, int, int, int, double*, bool) [clone ._omp_fn.0]	Module: exec	Source: local_halos.cpp:10-15	Coverage (incl. loops): 0.02% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-118-5752/intel/TeaLeaf/build/TeaLeaf/src/omp/local_halos.cpp: 10 - 15

--------------------------------------------------------------------------------

10:   #pragma omp parallel for

11: #endif

12:   for (int jj = halo_depth; jj < y - halo_depth; ++jj) {

13:     for (int kk = 0; kk < depth; ++kk) {

14:       int base = jj * x;

15:       buffer[base + (halo_depth - kk - 1)] = buffer[base + (halo_depth + kk)];

0x406420 STP	X29, X30, [SP, #992]!

0x406424 ADD	X29, SP, #0

0x406428 STP	X19, X20, [SP, #16]

0x40642c ORR	X20, XZR, X0

0x406430 BL	401910

0x406434 ORR	W19, WZR, W0

0x406438 BL	4018a0

0x40643c ORR	W5, WZR, W0

0x406440 LDP	W0, W3, [X20, #12]

0x406444 SUB	W0, W0, W3,LSL #1

0x406448 SDIV	W2, W0, W19

0x40644c MSUB	W1, W2, W19, W0

0x406450 CMP	W5, W1

0x406454 B.LT	40651c

(119) 0x406458 MADD	W5, W2, W5, W1

(119) 0x40645c ADD	W2, W2, W5

(119) 0x406460 CMP	W5, W2

(119) 0x406464 B.GE	406510

(119) 0x406468 LDR	W9, [X20, #20]

(119) 0x40646c ADD	W5, W3, W5

(119) 0x406470 ADD	W6, W3, W2

(119) 0x406474 LDR	X11, [X20]

(119) 0x406478 LDR	W10, [X20, #8]

(119) 0x40647c CMP	W9, #0

(119) 0x406480 B.LE	406510

(119) 0x406484 SUB	W0, W9, #1

(119) 0x406488 CMP	W0, #2

(119) 0x40648c B.LS	406528

(119) 0x406490 AND	W12, W9, #1951

(119) 0x406494 MADD	W7, W10, W5, WZR

(119) 0x406498 SBFM	X2, X3, #0, #31

(119) 0x40649c ADD	X2, X2, W7,SXTW

(119) 0x4064a0 SUB	W14, W3, W12

(119) 0x4064a4 UBFM	W4, W9, #1, #31

(119) 0x4064a8 ADD	X2, X11, X2,LSL #3

(119) 0x4064ac SUB	W14, W14, #1

(119) 0x4064b0 ADD	W8, W3, W12

(119) 0x4064b4 UBFM	X4, X4, #60, #59

(119) 0x4064b8 SBFM	X13, X10, #61, #31

(119) 0x4064bc HINT	#0

  (123) 0x4064c0 SUB	X3, X2, #16

  (123) 0x4064c4 MOVZ	X0, #0

    (122) 0x4064c8 LDR	Q31, [X2, X0]

    (122) 0x4064cc SUB	X1, XZR, X0

    (122) 0x4064d0 ADD	X0, X0, #16

    (122) 0x4064d4 EXT	V31.16B, V31.16B, V31.16B, #8

    (122) 0x4064d8 STR	Q31, [X3, X1]

    (122) 0x4064dc CMP	X0, X4

    (122) 0x4064e0 B.NE	4064c8

  (123) 0x4064e4 CMP	W9, W12

  (123) 0x4064e8 B.EQ	4064fc

  (123) 0x4064ec ADD	W0, W7, W8

  (123) 0x4064f0 ADD	W1, W7, W14

  (123) 0x4064f4 LDR	D31, [X11, X0,SXTW #3]

  (123) 0x4064f8 STR	D31, [X11, X1,SXTW #3]

  (123) 0x4064fc ADD	W5, W5, #1

  (123) 0x406500 ADD	W7, W7, W10

  (123) 0x406504 ADD	X2, X2, X13

  (123) 0x406508 CMP	W6, W5

  (123) 0x40650c B.GT	4064c0

(119) 0x406510 LDP	X19, X20, [SP, #16]

(119) 0x406514 LDP	X29, X30, [SP], #32

(119) 0x406518 RET

(119) 0x40651c ADD	W2, W2, #1

(119) 0x406520 MOVZ	W1, #0

(119) 0x406524 B	406458

(119) 0x406528 MADD	W0, W10, W5, WZR

(119) 0x40652c SBFM	X7, X9, #0, #31

(119) 0x406530 SBFM	X3, X3, #0, #31

(119) 0x406534 ADD	X2, X3, X7

(119) 0x406538 SUB	X7, XZR, X7,LSL #3

(119) 0x40653c SBFM	X9, X10, #60, #31

(119) 0x406540 UBFM	X4, X11, #63, #62

(119) 0x406544 SBFM	X10, X10, #61, #31

(119) 0x406548 SBFM	X0, X0, #0, #31

(119) 0x40654c ADD	X2, X2, X0

(119) 0x406550 ADD	X0, X0, X3

(119) 0x406554 ADD	X2, X11, X2,LSL #3

(119) 0x406558 UBFM	X8, X0, #60, #59

(119) 0x40655c HINT	#0

  (121) 0x406560 ADD	X0, X2, X7

  (121) 0x406564 SUB	X3, X8, #8

    (120) 0x406568 LDR	D31, [X0]

    (120) 0x40656c SUB	X1, X3, X0

    (120) 0x406570 ADD	X0, X0, #8

    (120) 0x406574 STR	D31, [X1, X4]

    (120) 0x406578 CMP	X0, X2

    (120) 0x40657c B.NE	406568

  (121) 0x406580 ADD	W5, W5, #1

  (121) 0x406584 ADD	X8, X8, X9

  (121) 0x406588 ADD	X2, X2, X10

  (121) 0x40658c CMP	W6, W5

  (121) 0x406590 B.GT	406560

(119) 0x406594 B	406510

0x406598 HINT	#0

0x40659c HINT	#0

Coverage (%)	Name	Source Location	Module
►98.79+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	local_halos.cpp:10-15
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-118-5752/intel/TeaLeaf/build/TeaLeaf/src/omp/local_halos.cpp:10-15.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 53% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 12.50 to 3.12 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.50 to 1.00 cycles (12.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 8 bytes. The binary function is storing 32 bytes.

General properties

nb instructions	16
loop length	64
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.50	1.50	1.83	1.83	1.83	1.83	2.00	1.67	0.00	0.00	0.00	0.00	1.00	1.00	1.00	1.00	1.00
cycles	1.50	1.50	1.83	1.83	1.83	1.83	2.00	1.67	0.00	0.00	0.00	0.00	1.00	1.00	1.00	1.00	1.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	1.75
Overall L1	5.00-12.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.50 cycles. At this rate:

0% of peak load performance is reached (0.64 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (2.56 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 406420

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #992]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 401910 <@plt_start@+0x300>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W19, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4018a0 <@plt_start@+0x290>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W5, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDP W0, W3, [X20, #12]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
SUB W0, W0, W3,LSL #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SDIV W2, W0, W19	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	scal (25.0%)
MSUB W1, W2, W19, W0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
CMP W5, W1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.LT 40651c <_Z11update_leftiiiiPdb._omp_fn.0+0xfc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	local_halos.cpp:10-15
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-118-5752/intel/TeaLeaf/build/TeaLeaf/src/omp/local_halos.cpp:10-15.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.50 to 1.00 cycles (12.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 8 bytes. The binary function is storing 32 bytes.

General properties

nb instructions	16
loop length	64
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.50	1.50	1.83	1.83	1.83	1.83	2.00	1.67	0.00	0.00	0.00	0.00	1.00	1.00	1.00	1.00	1.00
cycles	1.50	1.50	1.83	1.83	1.83	1.83	2.00	1.67	0.00	0.00	0.00	0.00	1.00	1.00	1.00	1.00	1.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	1.75
Overall L1	5.00-12.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.50 cycles. At this rate:

0% of peak load performance is reached (0.64 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (2.56 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 406420

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #992]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 401910 <@plt_start@+0x300>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W19, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4018a0 <@plt_start@+0x290>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W5, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDP W0, W3, [X20, #12]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
SUB W0, W0, W3,LSL #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SDIV W2, W0, W19	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	scal (25.0%)
MSUB W1, W2, W19, W0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
CMP W5, W1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.LT 40651c <_Z11update_leftiiiiPdb._omp_fn.0+0xfc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A

Name	Coverage (%)	Time (s)
▼update_left(int, int, int, int, double*, bool) [clone ._omp_fn.0]–	0.02	0.03
▼Loop 119 - local_halos.cpp:10-15 - exec–	0.00	0.01
▼Loop 121 - local_halos.cpp:13-15 - exec–	0.00	0.01
○Loop 120 - local_halos.cpp:13-15 - exec	0.02	0.03
▼Loop 123 - local_halos.cpp:12-15 - exec–	0.00	0.00
○Loop 122 - local_halos.cpp:13-15 - exec	0.00	0.00

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code