OV - exec - Function cg_calc_ur(int, int, int, double, double*, double*, double const*, double*, double const*) [clone ._omp

	Function: cg_calc_ur(int, int, int, double, double, double, double const, double, double const*) ...	Module: exec	Source: cg.cpp:105-113	Coverage (incl. loops): 38.72% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-118-5752/intel/TeaLeaf/build/TeaLeaf/src/omp/cg.cpp: 105 - 113

--------------------------------------------------------------------------------

105:   #pragma omp parallel for reduction(+ : rrn_temp)

106: #endif

107:   for (int jj = halo_depth; jj < y - halo_depth; ++jj) {

108:     for (int kk = halo_depth; kk < x - halo_depth; ++kk) {

109:       const int index = kk + jj * x;

110:

111:       u[index] += alpha * p[index];

112:       r[index] -= alpha * w[index];

113:       rrn_temp += r[index] * r[index];

0x402cac STP	X29, X30, [SP, #944]!

0x402cb0 ADD	X29, SP, #0

0x402cb4 STP	X19, X20, [SP, #16]

0x402cb8 ORR	X19, XZR, X0

0x402cbc BL	401910

0x402cc0 ORR	W20, WZR, W0

0x402cc4 BL	4018a0

0x402cc8 ORR	W10, WZR, W0

0x402ccc LDP	W0, W15, [X19, #52]

0x402cd0 SUB	W0, W0, W15,LSL #1

0x402cd4 SDIV	W1, W0, W20

0x402cd8 MSUB	W0, W1, W20, W0

0x402cdc CMP	W10, W0

0x402ce0 B.LT	402ef0

0x402ce4 MADD	W10, W1, W10, W0

0x402ce8 MOVI	D30, #0

0x402cec ADD	W1, W1, W10

0x402cf0 CMP	W10, W1

0x402cf4 B.GE	402e68

0x402cf8 STP	X21, X22, [SP, #32]

0x402cfc ADD	W10, W15, W10

0x402d00 ADD	W0, W15, W1

0x402d04 SBFM	X18, X15, #0, #31

0x402d08 STP	X23, X24, [SP, #48]

0x402d0c STP	X25, X26, [SP, #64]

0x402d10 LDR	D27, [X19]

0x402d14 LDP	X9, X13, [X19, #8]

0x402d18 LDP	X8, X12, [X19, #24]

0x402d1c DUP	V28.2D, V27.D[0]

0x402d20 LDR	W17, [X19, #48]

0x402d24 SUB	W22, W17, W15,LSL #1

0x402d28 SUB	W20, W17, W15

0x402d2c MADD	W14, W10, W17, WZR

0x402d30 UBFM	W7, W22, #1, #31

0x402d34 AND	W30, W22, #1951

0x402d38 UBFM	X7, X7, #60, #59

0x402d3c ADD	W30, W30, W15

0x402d40 SUB	W21, W22, #1

0x402d44 AND	W16, W22, #0

    (36) 0x402d48 CMP	W15, W20

    (36) 0x402d4c B.GE	402edc

  (37) 0x402d50 SBFM	X24, X14, #0, #31

  (37) 0x402d54 SBFM	X4, X15, #0, #31

  (37) 0x402d58 CMP	W21, #3

  (37) 0x402d5c B.LS	402e98

  (37) 0x402d60 ORR	X4, XZR, X18

    (39) 0x402d64 SBFM	X24, X14, #0, #31

    (39) 0x402d68 ADD	X2, X24, X18

    (39) 0x402d6c UBFM	X5, X2, #61, #60

    (39) 0x402d70 ADD	X2, X8, X2,LSL #3

    (39) 0x402d74 ADD	X1, X5, #16

    (39) 0x402d78 ADD	X3, X9, X5

    (39) 0x402d7c ADD	X6, X12, X1

    (39) 0x402d80 ADD	X25, X9, X1

    (39) 0x402d84 CMP	X6, X3

    (39) 0x402d88 ADD	X6, X12, X5

    (39) 0x402d8c ADD	X11, X8, X1

    (39) 0x402d90 CCMP	X25, X6, #0, #8

    (39) 0x402d94 CSINC	W23, WZR, WZR, #8

    (39) 0x402d98 ADD	X1, X5, #8

    (39) 0x402d9c CMP	X3, X11

    (39) 0x402da0 ADD	X26, X12, X1

    (39) 0x402da4 CCMP	X2, X25, #2, #3

    (39) 0x402da8 CSINC	W11, WZR, WZR, #3

    (39) 0x402dac ADD	X1, X13, X1

    (39) 0x402db0 CMP	X26, X2

    (39) 0x402db4 CCMP	X2, X1, #4, #1

    (39) 0x402db8 AND	W11, W23, W11

    (39) 0x402dbc CCMP	X3, X1, #4, #1

    (39) 0x402dc0 CSINC	W1, WZR, WZR, #0

    (39) 0x402dc4 ANDS	WZR, W1, W11

    (39) 0x402dc8 B.EQ	402e98

    (39) 0x402dcc MOVZ	X1, #0

    (39) 0x402dd0 ADD	X5, X13, X5

    (39) 0x402dd4 HINT	#0

    (39) 0x402dd8 HINT	#0

    (39) 0x402ddc HINT	#0

      (38) 0x402de0 LDR	Q29, [X5, X1]

      (38) 0x402de4 LDR	Q31, [X3, X1]

      (38) 0x402de8 FMLA	V31.2D, V29.2D, V28.2D

      (38) 0x402dec STR	Q31, [X3, X1]

      (38) 0x402df0 LDR	Q29, [X6, X1]

      (38) 0x402df4 LDR	Q31, [X2, X1]

      (38) 0x402df8 FMLS	V31.2D, V28.2D, V29.2D

      (38) 0x402dfc FMUL	V29.2D, V31.2D, V31.2D

      (38) 0x402e00 STR	Q31, [X2, X1]

      (38) 0x402e04 ADD	X1, X1, #16

      (38) 0x402e08 FADD	D30, D30, D29

      (38) 0x402e0c MOV	D31, V29.D[1]

      (38) 0x402e10 FADD	D30, D31, D30

      (38) 0x402e14 CMP	X7, X1

      (38) 0x402e18 B.NE	402de0

    (39) 0x402e1c CBZ	W16, 402e4c

    (39) 0x402e20 ADD	W1, W30, W14

    (39) 0x402e24 SBFM	X1, X1, #61, #31

    (39) 0x402e28 LDR	D29, [X13, X1]

    (39) 0x402e2c LDR	D31, [X9, X1]

    (39) 0x402e30 FMADD	D31, D27, D29, D31

    (39) 0x402e34 STR	D31, [X9, X1]

    (39) 0x402e38 LDR	D29, [X12, X1]

    (39) 0x402e3c LDR	D31, [X8, X1]

    (39) 0x402e40 FMSUB	D31, D27, D29, D31

    (39) 0x402e44 FMADD	D30, D31, D31, D30

    (39) 0x402e48 STR	D31, [X8, X1]

    (39) 0x402e4c ADD	W10, W10, #1

    (39) 0x402e50 ADD	W14, W14, W17

    (39) 0x402e54 CMP	W0, W10

    (39) 0x402e58 B.GT	402d64

(40) 0x402e5c LDP	X21, X22, [SP, #32]

(40) 0x402e60 LDP	X23, X24, [SP, #48]

(40) 0x402e64 LDP	X25, X26, [SP, #64]

(40) 0x402e68 ADD	X19, X19, #40

(40) 0x402e6c LDR	X0, [X19]

  (34) 0x402e70 ORR	X1, XZR, X0

  (34) 0x402e74 FMOV	D31, X0

  (34) 0x402e78 FADD	D31, D30, D31

  (34) 0x402e7c FMOV	X2, D31

  (34) 0x402e80 CAS	X1, X2, [X19]

  (34) 0x402e84 CMP	X0, X1

  (34) 0x402e88 B.NE	402efc

(40) 0x402e8c LDP	X19, X20, [SP, #16]

(40) 0x402e90 LDP	X29, X30, [SP], #80

(40) 0x402e94 RET

  (37) 0x402e98 ADD	X2, X22, X4

  (37) 0x402e9c ADD	X1, X24, X4

  (37) 0x402ea0 ADD	X2, X2, X24

  (37) 0x402ea4 UBFM	X1, X1, #61, #60

  (37) 0x402ea8 UBFM	X2, X2, #61, #60

    (35) 0x402eac LDR	D29, [X13, X1]

    (35) 0x402eb0 LDR	D31, [X9, X1]

    (35) 0x402eb4 FMADD	D31, D27, D29, D31

    (35) 0x402eb8 STR	D31, [X9, X1]

    (35) 0x402ebc LDR	D29, [X12, X1]

    (35) 0x402ec0 LDR	D31, [X8, X1]

    (35) 0x402ec4 FMSUB	D31, D27, D29, D31

    (35) 0x402ec8 FMADD	D30, D31, D31, D30

    (35) 0x402ecc STR	D31, [X8, X1]

    (35) 0x402ed0 ADD	X1, X1, #8

    (35) 0x402ed4 CMP	X2, X1

    (35) 0x402ed8 B.NE	402eac

    (36) 0x402edc ADD	W10, W10, #1

    (36) 0x402ee0 ADD	W14, W14, W17

    (36) 0x402ee4 CMP	W0, W10

    (36) 0x402ee8 B.GT	402d48

(40) 0x402eec B	402e5c

0x402ef0 ADD	W1, W1, #1

0x402ef4 MOVZ	W0, #0

0x402ef8 B	402ce4

  (34) 0x402efc ORR	X0, XZR, X1

  (34) 0x402f00 B	402e70

Coverage (%)	Name	Source Location	Module
►98.90+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.10+	GOMP_parallel	libgomp.h:980	libgomp.so.1.0.0
○	run_cg_calc_ur(Chunk*, Setting[...]	cg.cpp:117	exec
○	cg_main_step_driver(Chunk*, Se[...]	cg_driver.cpp:69	exec
○	cg_driver(Chunk*, Settings&, d[...]	cg_driver.cpp:18	exec
○	solve(Chunk*, Settings&, int, [...]	diffuse.cpp:51	exec
○	diffuse(Chunk*, Settings&)	diffuse.cpp:12	exec
○	main	main.cpp:179	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	new_allocator.h:104	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	cg.cpp:105-113
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-118-5752/intel/TeaLeaf/build/TeaLeaf/src/omp/cg.cpp:105-113.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is probably not vectorized. Only 49% of vector register length is used (average across all VPU instructions).

Details

Store and arithmetical VPU instructions are used in scalar version (process only one data element in vector registers).

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.50 to 1.00 cycles (12.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 52 bytes. The binary function is storing 80 bytes.

General properties

nb instructions	42
loop length	168
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

5.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	2.50	2.50	4.67	4.75	4.67	4.67	4.67	4.58	0.50	0.50	0.50	0.50	3.50	3.17	3.33	2.50	2.50
cycles	2.50	2.50	4.67	4.75	4.67	4.67	4.67	4.58	0.50	0.50	0.50	0.50	3.50	3.17	3.33	2.50	2.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	5.25
Overall L1	5.25-12.50

Vectorization ratios

all	3%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.50 cycles. At this rate:

4% of peak load performance is reached (4.16 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
13% of peak store performance is reached (6.40 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 402cac

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #944]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X19, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 401910 <@plt_start@+0x300>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W20, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4018a0 <@plt_start@+0x290>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W10, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
LDP W0, W15, [X19, #52]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
SUB W0, W0, W15,LSL #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SDIV W1, W0, W20	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	N/A
MSUB W0, W1, W20, W0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
CMP W10, W0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 402ef0 <_Z10cg_calc_uriiidPdS_PKdS_S1_._omp_fn.0+0x244>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W10, W1, W10, W0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
MOVI D30, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADD W1, W1, W10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP W10, W1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 402e68 <_Z10cg_calc_uriiidPdS_PKdS_S1_._omp_fn.0+0x1bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD W10, W15, W10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W0, W15, W1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SBFM X18, X15, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDR D27, [X19]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDP X9, X13, [X19, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X8, X12, [X19, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
DUP V28.2D, V27.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
LDR W17, [X19, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SUB W22, W17, W15,LSL #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SUB W20, W17, W15	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MADD W14, W10, W17, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
UBFM W7, W22, #1, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
AND W30, W22, #1951	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
UBFM X7, X7, #60, #59	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD W30, W30, W15	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SUB W21, W22, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
AND W16, W22, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W1, W1, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W0, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
B 402ce4 <_Z10cg_calc_uriiidPdS_PKdS_S1_._omp_fn.0+0x38>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	cg.cpp:105-113
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-118-5752/intel/TeaLeaf/build/TeaLeaf/src/omp/cg.cpp:105-113.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is probably not vectorized. Only 49% of vector register length is used (average across all VPU instructions).

Details

Store and arithmetical VPU instructions are used in scalar version (process only one data element in vector registers).

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.50 to 1.00 cycles (12.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 52 bytes. The binary function is storing 80 bytes.

General properties

nb instructions	42
loop length	168
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

5.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	2.50	2.50	4.67	4.75	4.67	4.67	4.67	4.58	0.50	0.50	0.50	0.50	3.50	3.17	3.33	2.50	2.50
cycles	2.50	2.50	4.67	4.75	4.67	4.67	4.67	4.58	0.50	0.50	0.50	0.50	3.50	3.17	3.33	2.50	2.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	5.25
Overall L1	5.25-12.50

Vectorization ratios

all	3%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.50 cycles. At this rate:

4% of peak load performance is reached (4.16 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
13% of peak store performance is reached (6.40 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 402cac

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #944]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X19, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 401910 <@plt_start@+0x300>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W20, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4018a0 <@plt_start@+0x290>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W10, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
LDP W0, W15, [X19, #52]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
SUB W0, W0, W15,LSL #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SDIV W1, W0, W20	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	N/A
MSUB W0, W1, W20, W0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
CMP W10, W0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 402ef0 <_Z10cg_calc_uriiidPdS_PKdS_S1_._omp_fn.0+0x244>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W10, W1, W10, W0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
MOVI D30, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADD W1, W1, W10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP W10, W1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 402e68 <_Z10cg_calc_uriiidPdS_PKdS_S1_._omp_fn.0+0x1bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD W10, W15, W10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W0, W15, W1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SBFM X18, X15, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDR D27, [X19]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDP X9, X13, [X19, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X8, X12, [X19, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
DUP V28.2D, V27.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
LDR W17, [X19, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SUB W22, W17, W15,LSL #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SUB W20, W17, W15	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MADD W14, W10, W17, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
UBFM W7, W22, #1, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
AND W30, W22, #1951	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
UBFM X7, X7, #60, #59	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD W30, W30, W15	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SUB W21, W22, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
AND W16, W22, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W1, W1, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W0, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
B 402ce4 <_Z10cg_calc_uriiidPdS_PKdS_S1_._omp_fn.0+0x38>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼cg_calc_ur(int, int, int, double, double, double, double const, double, double const*) [clone ._omp_fn.0]–	38.72	62.27
▼Loop 40 - cg.cpp:105-113 - exec–	0.02	0.04
○Loop 34 - cg.cpp:105-105 - exec	0.01	0.02
▼Loop 37 - cg.cpp:105-113 - exec–	0.00	0.00
▼Loop 39 - cg.cpp:105-113 - exec–	0.01	0.01
○Loop 38 - cg.cpp:108-113 - exec	38.68	61.54
○Loop 36 - cg.cpp:108-108 - exec	0.00	0.00
○Loop 35 - cg.cpp:108-113 - exec	0.00	0.00

Report Configuration

Vectorization

Details

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code