OV - exec - Function cg_calc_w(int, int, int, double*, double const*, double*, double const*, double const*) [clone ._omp

	Function: cg_calc_w(int, int, int, double, double const, double, double const, double const*) [c ...	Module: exec	Source: cg.cpp:83-90	Coverage (incl. loops): 36.95% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-118-5752/intel/TeaLeaf/build/TeaLeaf/src/omp/cg.cpp: 83 - 90

--------------------------------------------------------------------------------

83:   #pragma omp parallel for reduction(+ : pw_temp)

84: #endif

85:   for (int jj = halo_depth; jj < y - halo_depth; ++jj) {

86:     for (int kk = halo_depth; kk < x - halo_depth; ++kk) {

87:       const int index = kk + jj * x;

88:       const double smvp = tealeaf_SMVP(p);

89:       w[index] = smvp;

90:       pw_temp += w[index] * p[index];

0x402908 STP	X29, X30, [SP, #880]!

0x40290c ADD	X29, SP, #0

0x402910 STP	X19, X20, [SP, #16]

0x402914 STP	X21, X22, [SP, #32]

0x402918 STP	X23, X24, [SP, #48]

0x40291c ORR	X24, XZR, X0

0x402920 BL	401910

0x402924 ORR	W19, WZR, W0

0x402928 BL	4018a0

0x40292c ORR	W15, WZR, W0

0x402930 LDP	W0, W21, [X24, #44]

0x402934 SUB	W0, W0, W21,LSL #1

0x402938 SDIV	W1, W0, W19

0x40293c MSUB	W0, W1, W19, W0

0x402940 CMP	W15, W0

0x402944 B.LT	402c98

0x402948 MADD	W15, W1, W15, W0

0x40294c MOVI	D30, #0

0x402950 ADD	W1, W1, W15

0x402954 CMP	W15, W1

0x402958 B.GE	402bb8

0x40295c STP	X25, X26, [SP, #64]

0x402960 ADD	W15, W21, W15

0x402964 FMOV	D21, #1.0000000

0x402968 FMOV	V22.2D, #1.0000000

0x40296c ADD	W19, W21, W1

0x402970 SBFM	X22, X21, #0, #31

0x402974 STP	X27, X28, [SP, #80]

0x402978 LDR	W30, [X24, #40]

0x40297c LDP	X5, X17, [X24]

0x402980 LDP	X16, X14, [X24, #16]

0x402984 SUB	W7, W30, W21,LSL #1

0x402988 SBFM	X0, X30, #61, #31

0x40298c SUB	W3, W30, W21

0x402990 MADD	W18, W15, W30, WZR

0x402994 ADD	X12, X5, X0

0x402998 SUB	X11, X5, X0

0x40299c UBFM	W13, W7, #1, #31

0x4029a0 AND	W1, W7, #1951

0x4029a4 SUB	W4, W30, W21,LSL #1

0x4029a8 ORR	W8, WZR, W3

0x4029ac ADD	X10, X5, #8

0x4029b0 SUB	X9, X5, #8

0x4029b4 ADD	X6, X16, #8

0x4029b8 SBFM	X20, X30, #0, #31

0x4029bc UBFM	X13, X13, #60, #59

0x4029c0 ADD	W28, W1, W21

0x4029c4 AND	W27, W7, #0

0x4029c8 ADD	X0, X14, X0

0x4029cc ORR	W3, WZR, W7

      (28) 0x4029d0 CMP	W21, W8

      (28) 0x4029d4 B.GE	402c84

    (29) 0x4029d8 SBFM	X1, X18, #0, #31

    (29) 0x4029dc SBFM	X7, X21, #0, #31

    (29) 0x4029e0 CMP	W3, #1

    (29) 0x4029e4 B.EQ	402c04

  (30) 0x4029e8 ORR	X7, XZR, X22

  (30) 0x4029ec STP	W21, W8, [SP, #108]

  (30) 0x4029f0 STR	W3, [SP, #116]

  (30) 0x4029f4 STP	X0, X11, [SP, #120]

  (30) 0x4029f8 STR	X12, [SP, #136]

    (32) 0x4029fc SBFM	X0, X18, #0, #31

    (32) 0x402a00 ADD	X2, X0, X22

    (32) 0x402a04 UBFM	X1, X2, #61, #60

    (32) 0x402a08 ADD	X8, X17, X2,LSL #3

    (32) 0x402a0c SUB	X3, X2, X20

    (32) 0x402a10 ADD	X11, X1, #24

    (32) 0x402a14 ADD	X3, X3, #1

    (32) 0x402a18 ADD	X11, X5, X11

    (32) 0x402a1c SUB	X12, X1, #8

    (32) 0x402a20 ADD	X23, X5, X3,LSL #3

    (32) 0x402a24 ADD	X21, X1, #16

    (32) 0x402a28 CMP	X11, X8

    (32) 0x402a2c ADD	X21, X17, X21

    (32) 0x402a30 ADD	X11, X1, #8

    (32) 0x402a34 ADD	X12, X5, X12

    (32) 0x402a38 ADD	X2, X20, X2

    (32) 0x402a3c ADD	X2, X2, #1

    (32) 0x402a40 CCMP	X12, X21, #2, #8

    (32) 0x402a44 ADD	X21, X16, X11

    (32) 0x402a48 ADD	X26, X5, X2,LSL #3

    (32) 0x402a4c CCMP	X23, X8, #4, #2

    (32) 0x402a50 SUB	X23, X8, X21

    (32) 0x402a54 ADD	X25, X14, X2,LSL #3

    (32) 0x402a58 UBFM	X3, X3, #61, #60

    (32) 0x402a5c CCMP	X23, #8, #0, #1

    (32) 0x402a60 UBFM	X2, X2, #61, #60

    (32) 0x402a64 CSINC	W23, WZR, WZR, #9

    (32) 0x402a68 CMP	X26, X8

    (32) 0x402a6c ADD	X26, X14, X11

    (32) 0x402a70 CCMP	X25, X8, #4, #1

    (32) 0x402a74 CCMP	X26, X8, #4, #1

    (32) 0x402a78 CSINC	W25, WZR, WZR, #0

    (32) 0x402a7c ANDS	WZR, W23, W25

    (32) 0x402a80 B.EQ	402bf0

    (32) 0x402a84 SUB	X2, X2, #8

    (32) 0x402a88 SUB	X3, X3, #8

    (32) 0x402a8c ADD	X26, X14, X2

    (32) 0x402a90 ADD	X25, X16, X1

    (32) 0x402a94 ADD	X23, X14, X1

    (32) 0x402a98 MOVZ	X0, #0

    (32) 0x402a9c ADD	X3, X5, X3

    (32) 0x402aa0 ADD	X11, X5, X11

    (32) 0x402aa4 ADD	X2, X5, X2

    (32) 0x402aa8 ADD	X1, X5, X1

      (31) 0x402aac LDR	Q25, [X21, X0]

      (31) 0x402ab0 LDR	Q29, [X25, X0]

      (31) 0x402ab4 LDR	Q31, [X12, X0]

      (31) 0x402ab8 LDR	Q23, [X11, X0]

      (31) 0x402abc LDR	Q27, [X26, X0]

      (31) 0x402ac0 FADD	V28.2D, V25.2D, V29.2D

      (31) 0x402ac4 LDR	Q26, [X23, X0]

      (31) 0x402ac8 FMUL	V31.2D, V31.2D, V29.2D

      (31) 0x402acc LDR	Q29, [X3, X0]

      (31) 0x402ad0 FADD	V28.2D, V28.2D, V22.2D

      (31) 0x402ad4 LDR	Q24, [X1, X0]

      (31) 0x402ad8 FMLA	V31.2D, V25.2D, V23.2D

      (31) 0x402adc LDR	Q25, [X2, X0]

      (31) 0x402ae0 FADD	V23.2D, V27.2D, V26.2D

      (31) 0x402ae4 FMUL	V29.2D, V29.2D, V26.2D

      (31) 0x402ae8 FADD	V28.2D, V28.2D, V23.2D

      (31) 0x402aec FNEG	V31.2D, V31.2D

      (31) 0x402af0 FMLA	V29.2D, V27.2D, V25.2D

      (31) 0x402af4 FMLA	V31.2D, V28.2D, V24.2D

      (31) 0x402af8 FSUB	V31.2D, V31.2D, V29.2D

      (31) 0x402afc STR	Q31, [X8, X0]

      (31) 0x402b00 LDR	Q29, [X1, X0]

      (31) 0x402b04 ADD	X0, X0, #16

      (31) 0x402b08 FMUL	V31.2D, V29.2D, V31.2D

      (31) 0x402b0c FADD	D30, D30, D31

      (31) 0x402b10 MOV	D29, V31.D[1]

      (31) 0x402b14 FADD	D30, D29, D30

      (31) 0x402b18 CMP	X0, X13

      (31) 0x402b1c B.NE	402aac

    (32) 0x402b20 CBZ	W27, 402ba0

    (32) 0x402b24 ADD	W1, W28, W18

    (32) 0x402b28 SBFM	X0, X1, #0, #31

    (32) 0x402b2c ADD	W3, W30, W1

    (32) 0x402b30 ADD	X0, X0, #1

    (32) 0x402b34 SUB	W2, W1, W30

    (32) 0x402b38 UBFM	X0, X0, #61, #60

    (32) 0x402b3c SBFM	X3, X3, #61, #31

    (32) 0x402b40 SUB	X1, X0, #8

    (32) 0x402b44 ADD	X8, X5, X0

    (32) 0x402b48 LDR	D19, [X5, X2,SXTW #3]

    (32) 0x402b4c LDR	D31, [X16, X1]

    (32) 0x402b50 LDR	D26, [X16, X0]

    (32) 0x402b54 LDR	D27, [X14, X3]

    (32) 0x402b58 LDR	D29, [X14, X1]

    (32) 0x402b5c FADD	D28, D26, D31

    (32) 0x402b60 LDUR	D25, [X8, #496]

    (32) 0x402b64 LDR	D20, [X5, X0]

    (32) 0x402b68 FADD	D23, D27, D29

    (32) 0x402b6c LDR	D24, [X5, X3]

    (32) 0x402b70 FMUL	D29, D29, D19

    (32) 0x402b74 FADD	D28, D28, D22

    (32) 0x402b78 FMUL	D31, D31, D25

    (32) 0x402b7c LDR	D25, [X5, X1]

    (32) 0x402b80 FMADD	D29, D27, D24, D29

    (32) 0x402b84 FMADD	D31, D26, D20, D31

    (32) 0x402b88 FADD	D28, D28, D23

    (32) 0x402b8c FNMSUB	D31, D28, D25, D31

    (32) 0x402b90 FSUB	D31, D31, S29

    (32) 0x402b94 STR	D31, [X17, X1]

    (32) 0x402b98 LDR	D29, [X5, X1]

    (32) 0x402b9c FMADD	D30, D31, D29, D30

    (32) 0x402ba0 ADD	W15, W15, #1

    (32) 0x402ba4 ADD	W18, W18, W30

    (32) 0x402ba8 CMP	W19, W15

    (32) 0x402bac B.GT	4029fc

(33) 0x402bb0 LDP	X25, X26, [SP, #64]

(33) 0x402bb4 LDP	X27, X28, [SP, #80]

(33) 0x402bb8 ADD	X2, X24, #32

(33) 0x402bbc LDR	X0, [X2]

  (26) 0x402bc0 ORR	X1, XZR, X0

  (26) 0x402bc4 FMOV	D31, X0

  (26) 0x402bc8 FADD	D31, D30, D31

  (26) 0x402bcc FMOV	X3, D31

  (26) 0x402bd0 CAS	X1, X3, [X2]

  (26) 0x402bd4 CMP	X0, X1

  (26) 0x402bd8 B.NE	402ca4

(33) 0x402bdc LDP	X19, X20, [SP, #16]

(33) 0x402be0 LDP	X21, X22, [SP, #32]

(33) 0x402be4 LDP	X23, X24, [SP, #48]

(33) 0x402be8 LDP	X29, X30, [SP], #144

(33) 0x402bec RET

  (30) 0x402bf0 LDR	X12, [SP, #136]

  (30) 0x402bf4 ORR	X1, XZR, X0

  (30) 0x402bf8 LDP	X0, X11, [SP, #120]

  (30) 0x402bfc LDP	W21, W8, [SP, #108]

  (30) 0x402c00 LDR	W3, [SP, #116]

    (29) 0x402c04 ADD	X2, X4, X7

    (29) 0x402c08 ADD	X7, X1, X7

    (29) 0x402c0c ADD	X2, X2, X1

    (29) 0x402c10 UBFM	X1, X7, #61, #60

    (29) 0x402c14 UBFM	X2, X2, #61, #60

    (29) 0x402c18 HINT	#0

    (29) 0x402c1c HINT	#0

      (27) 0x402c20 LDR	D26, [X6, X1]

      (27) 0x402c24 LDR	D31, [X16, X1]

      (27) 0x402c28 LDR	D27, [X0, X1]

      (27) 0x402c2c LDR	D29, [X14, X1]

      (27) 0x402c30 FADD	D28, D26, D31

      (27) 0x402c34 LDR	D25, [X9, X1]

      (27) 0x402c38 LDR	D20, [X10, X1]

      (27) 0x402c3c FADD	D23, D27, D29

      (27) 0x402c40 LDR	D19, [X11, X1]

      (27) 0x402c44 FADD	D28, D28, D21

      (27) 0x402c48 FMUL	D31, D31, D25

      (27) 0x402c4c LDR	D24, [X12, X1]

      (27) 0x402c50 LDR	D25, [X5, X1]

      (27) 0x402c54 FMUL	D29, D29, D19

      (27) 0x402c58 FMADD	D31, D26, D20, D31

      (27) 0x402c5c FADD	D28, D28, D23

      (27) 0x402c60 FMADD	D29, D27, D24, D29

      (27) 0x402c64 FNMSUB	D31, D28, D25, D31

      (27) 0x402c68 FSUB	D31, D31, S29

      (27) 0x402c6c STR	D31, [X17, X1]

      (27) 0x402c70 LDR	D29, [X5, X1]

      (27) 0x402c74 ADD	X1, X1, #8

      (27) 0x402c78 FMADD	D30, D31, D29, D30

      (27) 0x402c7c CMP	X1, X2

      (27) 0x402c80 B.NE	402c20

      (28) 0x402c84 ADD	W15, W15, #1

      (28) 0x402c88 ADD	W18, W18, W30

      (28) 0x402c8c CMP	W19, W15

      (28) 0x402c90 B.GT	4029d0

(33) 0x402c94 B	402bb0

0x402c98 ADD	W1, W1, #1

0x402c9c MOVZ	W0, #0

0x402ca0 B	402948

  (26) 0x402ca4 ORR	X0, XZR, X1

  (26) 0x402ca8 B	402bc0

Coverage (%)	Name	Source Location	Module
►98.96+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.04+	GOMP_parallel	libgomp.h:980	libgomp.so.1.0.0
○	run_cg_calc_w(Chunk*, Settings[...]	cg.cpp:83	exec
○	cg_main_step_driver(Chunk*, Se[...]	cg_driver.cpp:57	exec
○	cg_driver(Chunk*, Settings&, d[...]	cg_driver.cpp:18	exec
○	solve(Chunk*, Settings&, int, [...]	diffuse.cpp:51	exec
○	diffuse(Chunk*, Settings&)	diffuse.cpp:12	exec
○	main	main.cpp:179	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	new_allocator.h:104	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	cg.cpp:83-90
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-118-5752/intel/TeaLeaf/build/TeaLeaf/src/omp/cg.cpp:83-90.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is probably not vectorized. Only 52% of vector register length is used (average across all VPU instructions).

Details

Store and arithmetical VPU instructions are used in scalar version (process only one data element in vector registers).

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.50 to 1.00 cycles (12.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 44 bytes. The binary function is storing 96 bytes.

General properties

nb instructions	53
loop length	212
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

6.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	2.50	2.50	6.33	6.42	6.33	6.33	6.33	6.25	0.75	0.75	0.75	0.75	3.33	3.33	3.33	3.00	3.00
cycles	2.50	2.50	6.33	6.42	6.33	6.33	6.33	6.25	0.75	0.75	0.75	0.75	3.33	3.33	3.33	3.00	3.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	6.63
Overall L1	6.63-12.50

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
other	0%

all	50%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

INT+FP

all	2%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.50 cycles. At this rate:

3% of peak load performance is reached (3.52 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
16% of peak store performance is reached (7.68 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 402908

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #880]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X24, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 401910 <@plt_start@+0x300>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W19, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4018a0 <@plt_start@+0x290>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W15, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
LDP W0, W21, [X24, #44]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
SUB W0, W0, W21,LSL #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SDIV W1, W0, W19	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	N/A
MSUB W0, W1, W19, W0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
CMP W15, W0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 402c98 <_Z9cg_calc_wiiiPdPKdS_S1_S1_._omp_fn.0+0x390>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W15, W1, W15, W0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
MOVI D30, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADD W1, W1, W15	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP W15, W1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 402bb8 <_Z9cg_calc_wiiiPdPKdS_S1_S1_._omp_fn.0+0x2b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD W15, W21, W15	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
FMOV D21, #1.0000000	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FMOV V22.2D, #1.0000000	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ADD W19, W21, W1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SBFM X22, X21, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDR W30, [X24, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X5, X17, [X24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X16, X14, [X24, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
SUB W7, W30, W21,LSL #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SBFM X0, X30, #61, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
SUB W3, W30, W21	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MADD W18, W15, W30, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD X12, X5, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X11, X5, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
UBFM W13, W7, #1, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
AND W1, W7, #1951	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB W4, W30, W21,LSL #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ORR W8, WZR, W3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD X10, X5, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X9, X5, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X6, X16, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SBFM X20, X30, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
UBFM X13, X13, #60, #59	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD W28, W1, W21	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
AND W27, W7, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD X0, X14, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR W3, WZR, W7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W1, W1, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W0, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
B 402948 <_Z9cg_calc_wiiiPdPKdS_S1_S1_._omp_fn.0+0x40>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	cg.cpp:83-90
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-118-5752/intel/TeaLeaf/build/TeaLeaf/src/omp/cg.cpp:83-90.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is probably not vectorized. Only 52% of vector register length is used (average across all VPU instructions).

Details

Store and arithmetical VPU instructions are used in scalar version (process only one data element in vector registers).

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.50 to 1.00 cycles (12.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 44 bytes. The binary function is storing 96 bytes.

General properties

nb instructions	53
loop length	212
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

6.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	2.50	2.50	6.33	6.42	6.33	6.33	6.33	6.25	0.75	0.75	0.75	0.75	3.33	3.33	3.33	3.00	3.00
cycles	2.50	2.50	6.33	6.42	6.33	6.33	6.33	6.25	0.75	0.75	0.75	0.75	3.33	3.33	3.33	3.00	3.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	6.63
Overall L1	6.63-12.50

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
other	0%

all	50%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

INT+FP

all	2%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.50 cycles. At this rate:

3% of peak load performance is reached (3.52 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
16% of peak store performance is reached (7.68 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 402908

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #880]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X24, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 401910 <@plt_start@+0x300>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W19, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4018a0 <@plt_start@+0x290>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W15, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
LDP W0, W21, [X24, #44]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
SUB W0, W0, W21,LSL #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SDIV W1, W0, W19	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	N/A
MSUB W0, W1, W19, W0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
CMP W15, W0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 402c98 <_Z9cg_calc_wiiiPdPKdS_S1_S1_._omp_fn.0+0x390>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W15, W1, W15, W0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
MOVI D30, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADD W1, W1, W15	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP W15, W1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 402bb8 <_Z9cg_calc_wiiiPdPKdS_S1_S1_._omp_fn.0+0x2b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD W15, W21, W15	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
FMOV D21, #1.0000000	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FMOV V22.2D, #1.0000000	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ADD W19, W21, W1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SBFM X22, X21, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDR W30, [X24, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X5, X17, [X24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X16, X14, [X24, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
SUB W7, W30, W21,LSL #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SBFM X0, X30, #61, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
SUB W3, W30, W21	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MADD W18, W15, W30, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD X12, X5, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X11, X5, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
UBFM W13, W7, #1, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
AND W1, W7, #1951	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB W4, W30, W21,LSL #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ORR W8, WZR, W3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD X10, X5, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X9, X5, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X6, X16, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SBFM X20, X30, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
UBFM X13, X13, #60, #59	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD W28, W1, W21	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
AND W27, W7, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD X0, X14, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR W3, WZR, W7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W1, W1, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W0, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
B 402948 <_Z9cg_calc_wiiiPdPKdS_S1_S1_._omp_fn.0+0x40>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼cg_calc_w(int, int, int, double, double const, double, double const, double const*) [clone ._omp_fn.0]–	36.95	59.42
▼Loop 33 - cg.cpp:83-90 - exec–	0.02	0.03
○Loop 26 - cg.cpp:83-83 - exec	0.01	0.01
▼Loop 30 - cg.cpp:83-90 - exec–	0.00	0.00
▼Loop 32 - cg.cpp:83-90 - exec–	0.00	0.01
○Loop 31 - cg.cpp:86-90 - exec	36.92	58.75
▼Loop 29 - cg.cpp:83-90 - exec–	0.00	0.00
○Loop 28 - cg.cpp:86-86 - exec	0.00	0.00
○Loop 27 - cg.cpp:86-90 - exec	0.00	0.00

Report Configuration

Vectorization

Details

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code