OV - exec - Function cg_init(int, int, int, int, double, double, double*, double const*, double const*, double*, double*, double*, double*, double*, double*) [clone ._omp

	Function: cg_init(int, int, int, int, double, double, double, double const, double const, double ...	Module: exec	Source: cg.cpp:59-68	Coverage (incl. loops): 0.02% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-118-5752/intel/TeaLeaf/build/TeaLeaf/src/omp/cg.cpp: 59 - 68

--------------------------------------------------------------------------------

59:   #pragma omp parallel for reduction(+ : rro_temp)

60: #endif

61:   for (int jj = halo_depth; jj < y - halo_depth; ++jj) {

62:     for (int kk = halo_depth; kk < x - halo_depth; ++kk) {

63:       const int index = kk + jj * x;

64:       const double smvp = tealeaf_SMVP(u);

65:       w[index] = smvp;

66:       r[index] = u[index] - w[index];

67:       p[index] = r[index];

68:       rro_temp += r[index] * p[index];

0x402780 STP	X29, X30, [SP, #976]!

0x402784 ADD	X29, SP, #0

0x402788 STP	X19, X20, [SP, #16]

0x40278c ORR	X19, XZR, X0

0x402790 BL	401910

0x402794 ORR	W20, WZR, W0

0x402798 BL	4018a0

0x40279c ORR	W15, WZR, W0

0x4027a0 LDP	W0, W17, [X19, #60]

0x4027a4 SUB	W0, W0, W17,LSL #1

0x4027a8 SDIV	W1, W0, W20

0x4027ac MSUB	W0, W1, W20, W0

0x4027b0 CMP	W15, W0

0x4027b4 B.LT	4028f4

(23) 0x4027b8 MADD	W15, W1, W15, W0

(23) 0x4027bc MOVI	D26, #0

(23) 0x4027c0 ADD	W1, W1, W15

(23) 0x4027c4 CMP	W15, W1

(23) 0x4027c8 B.GE	4028c4

(23) 0x4027cc LDR	W18, [X19, #56]

(23) 0x4027d0 ADD	W15, W17, W15

(23) 0x4027d4 FMOV	D20, #1.0000000

(23) 0x4027d8 ADD	W0, W17, W1

(23) 0x4027dc STR	X21, [SP, #32]

(23) 0x4027e0 SBFM	X21, X17, #0, #31

(23) 0x4027e4 LDP	X2, X14, [X19]

(23) 0x4027e8 LDP	X6, X5, [X19, #32]

(23) 0x4027ec SUB	W20, W18, W17,LSL #1

(23) 0x4027f0 SBFM	X4, X18, #61, #31

(23) 0x4027f4 SUB	W30, W18, W17

(23) 0x4027f8 MADD	W16, W15, W18, WZR

(23) 0x4027fc ADD	X13, X2, X4

(23) 0x402800 SUB	X12, X2, X4

(23) 0x402804 LDP	X7, X8, [X19, #16]

(23) 0x402808 ADD	X20, X20, X21

(23) 0x40280c ADD	X11, X2, #8

(23) 0x402810 SUB	X10, X2, #8

(23) 0x402814 ADD	X9, X6, #8

(23) 0x402818 ADD	X4, X5, X4

(23) 0x40281c HINT	#0

  (24) 0x402820 CMP	W17, W30

  (24) 0x402824 B.GE	4028b0

  (24) 0x402828 SBFM	X3, X16, #0, #31

  (24) 0x40282c ADD	X1, X3, X21

  (24) 0x402830 ADD	X3, X20, X3

  (24) 0x402834 UBFM	X1, X1, #61, #60

  (24) 0x402838 UBFM	X3, X3, #61, #60

  (24) 0x40283c HINT	#0

    (25) 0x402840 LDR	D27, [X9, X1]

    (25) 0x402844 LDR	D31, [X6, X1]

    (25) 0x402848 LDR	D28, [X4, X1]

    (25) 0x40284c LDR	D30, [X5, X1]

    (25) 0x402850 FADD	D29, D27, D31

    (25) 0x402854 LDR	D25, [X10, X1]

    (25) 0x402858 LDR	D22, [X11, X1]

    (25) 0x40285c FADD	D23, D28, D30

    (25) 0x402860 LDR	D21, [X12, X1]

    (25) 0x402864 FADD	D29, D29, D20

    (25) 0x402868 FMUL	D31, D31, D25

    (25) 0x40286c LDR	D24, [X13, X1]

    (25) 0x402870 LDR	D25, [X2, X1]

    (25) 0x402874 FMUL	D30, D30, D21

    (25) 0x402878 FMADD	D31, D27, D22, D31

    (25) 0x40287c FADD	D29, D29, D23

    (25) 0x402880 FMADD	D30, D28, D24, D30

    (25) 0x402884 FNMSUB	D31, D29, D25, D31

    (25) 0x402888 FSUB	D31, D31, S30

    (25) 0x40288c STR	D31, [X8, X1]

    (25) 0x402890 LDR	D30, [X2, X1]

    (25) 0x402894 FSUB	D31, D30, S31

    (25) 0x402898 STR	D31, [X7, X1]

    (25) 0x40289c FMADD	D26, D31, D31, D26

    (25) 0x4028a0 STR	D31, [X14, X1]

    (25) 0x4028a4 ADD	X1, X1, #8

    (25) 0x4028a8 CMP	X3, X1

    (25) 0x4028ac B.NE	402840

  (24) 0x4028b0 ADD	W15, W15, #1

  (24) 0x4028b4 ADD	W16, W16, W18

  (24) 0x4028b8 CMP	W0, W15

  (24) 0x4028bc B.GT	402820

(23) 0x4028c0 LDR	X21, [SP, #32]

(23) 0x4028c4 ADD	X19, X19, #48

(23) 0x4028c8 LDR	X0, [X19]

  (22) 0x4028cc FMOV	D31, X0

  (22) 0x4028d0 ORR	X1, XZR, X0

  (22) 0x4028d4 FADD	D31, D26, D31

  (22) 0x4028d8 FMOV	X2, D31

  (22) 0x4028dc CAS	X1, X2, [X19]

  (22) 0x4028e0 CMP	X0, X1

  (22) 0x4028e4 B.NE	402900

(23) 0x4028e8 LDP	X19, X20, [SP, #16]

(23) 0x4028ec LDP	X29, X30, [SP], #48

(23) 0x4028f0 RET

(23) 0x4028f4 ADD	W1, W1, #1

(23) 0x4028f8 MOVZ	W0, #0

(23) 0x4028fc B	4027b8

  (22) 0x402900 ORR	X0, XZR, X1

  (22) 0x402904 B	4028cc

Coverage (%)	Name	Source Location	Module
►98.48+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.52+	GOMP_parallel	libgomp.h:980	libgomp.so.1.0.0
○	run_cg_init(Chunk*, Settings&,[...]	cg.cpp:73	exec
○	cg_init_driver(Chunk*, Setting[...]	cg_driver.cpp:30	exec
○	cg_driver(Chunk*, Settings&, d[...]	cg_driver.cpp:15	exec
○	solve(Chunk*, Settings&, int, [...]	diffuse.cpp:51	exec
○	diffuse(Chunk*, Settings&)	diffuse.cpp:12	exec
○	main	main.cpp:179	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	new_allocator.h:104	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	cg.cpp:59-68
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-118-5752/intel/TeaLeaf/build/TeaLeaf/src/omp/cg.cpp:59-68.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 60% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 12.50 to 3.12 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.50 to 1.00 cycles (12.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 8 bytes. The binary function is storing 32 bytes.

General properties

nb instructions	14
loop length	56
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.50	1.50	1.83	1.83	1.83	1.83	2.00	1.67	0.00	0.00	0.00	0.00	1.00	1.00	1.00	1.00	1.00
cycles	1.50	1.50	1.83	1.83	1.83	1.83	2.00	1.67	0.00	0.00	0.00	0.00	1.00	1.00	1.00	1.00	1.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	1.75
Overall L1	5.00-12.50

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.50 cycles. At this rate:

0% of peak load performance is reached (0.64 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (2.56 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 402780

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #976]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X19, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
BL 401910 <@plt_start@+0x300>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W20, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4018a0 <@plt_start@+0x290>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W15, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDP W0, W17, [X19, #60]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB W0, W0, W17,LSL #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
SDIV W1, W0, W20	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5-12	5-12.50	scal (25.0%)
MSUB W0, W1, W20, W0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
CMP W15, W0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.LT 4028f4 <_Z7cg_initiiiiddPdPKdS1_S_S_S_S_S_S_._omp_fn.3+0x174>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	cg.cpp:59-68
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-118-5752/intel/TeaLeaf/build/TeaLeaf/src/omp/cg.cpp:59-68.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.50 to 1.00 cycles (12.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 8 bytes. The binary function is storing 32 bytes.

General properties

nb instructions	14
loop length	56
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.50	1.50	1.83	1.83	1.83	1.83	2.00	1.67	0.00	0.00	0.00	0.00	1.00	1.00	1.00	1.00	1.00
cycles	1.50	1.50	1.83	1.83	1.83	1.83	2.00	1.67	0.00	0.00	0.00	0.00	1.00	1.00	1.00	1.00	1.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	1.75
Overall L1	5.00-12.50

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.50 cycles. At this rate:

0% of peak load performance is reached (0.64 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (2.56 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 402780

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #976]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X19, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
BL 401910 <@plt_start@+0x300>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W20, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4018a0 <@plt_start@+0x290>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W15, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDP W0, W17, [X19, #60]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB W0, W0, W17,LSL #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
SDIV W1, W0, W20	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5-12	5-12.50	scal (25.0%)
MSUB W0, W1, W20, W0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
CMP W15, W0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.LT 4028f4 <_Z7cg_initiiiiddPdPKdS1_S_S_S_S_S_S_._omp_fn.3+0x174>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼cg_init(int, int, int, int, double, double, double, double const, double const, double, double, double, double, double, double*) [clone ._omp_fn.3]–	0.02	0.02
▼Loop 23 - cg.cpp:59-68 - exec–	0.00	0.00
○Loop 22 - cg.cpp:59-59 - exec	0.00	0.00
▼Loop 24 - cg.cpp:62-68 - exec–	0.00	0.00
○Loop 25 - cg.cpp:62-68 - exec	0.02	0.02

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code