OV - exec - Loop 2

	Loop Id: 2	Module: exec	Source: cg.cpp:21-25	Coverage: 0.01%

0x401c20 ADD	X1, X24, X21

0x401c24 ST1B	{Z0.B}, P0, [X24, X21]    [2]

0x401c28 ADD	X17, X26, X21

0x401c2c ST1D	{Z0.D}, P1, [X1, #1, MUL VL]    [7]

0x401c30 ADD	X1, X25, X21

0x401c34 DECW	X30, ALL

0x401c38 ST1B	{Z0.B}, P0, [X25, X21]    [3]

0x401c3c ADDVL	X25, X25, #2

0x401c40 ADDVL	X24, X24, #2

0x401c44 ST1D	{Z0.D}, P1, [X1, #1, MUL VL]    [6]

0x401c48 ADD	X1, X27, X21

0x401c4c LD1B	{Z1.B}, P0/Z, [X26, X21]    [4]

0x401c50 LD1B	{Z2.B}, P0/Z, [X27, X21]    [9]

0x401c54 LD1D	{Z3.D}, P1/Z, [X17, #1, MUL VL]    [8]

0x401c58 LD1D	{Z4.D}, P1/Z, [X1, #1, MUL VL]    [5]

0x401c5c ADD	X17, X28, X21

0x401c60 ADDVL	X27, X27, #2

0x401c64 ADDVL	X26, X26, #2

0x401c68 FMUL	Z1.D, Z1.D, Z2.D

0x401c6c FMUL	Z2.D, Z3.D, Z4.D

0x401c70 ST1B	{Z1.B}, P0, [X28, X21]    [10]

0x401c74 ADDVL	X28, X28, #2

0x401c78 ST1D	{Z2.D}, P1, [X17, #1, MUL VL]    [1]

0x401c7c CBNZ	X30, 401c20

/home/hbollore/qaas/qaas-runs/174-118-5752/intel/TeaLeaf/build/TeaLeaf/src/omp/cg.cpp: 21 - 25

--------------------------------------------------------------------------------

21:     for (int kk = 0; kk < x; ++kk) {

22:       const int index = kk + jj * x;

23:       p[index] = 0.0;

24:       r[index] = 0.0;

25:       u[index] = energy[index] * density[index];

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.11
Bottlenecks	P12, P13, P14,
Function	cg_init(int, int, int, int, double, double, double, double const, double const, double, double, double, double, double, double*) [clone .omp_outlined]
Source	cg.cpp:21-25
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	4
CQA cycles	3.33
CQA cycles if no scalar integer	3.33
CQA cycles if FP arith vectorized	3.33
CQA cycles if fully vectorized	3.33
Front-end cycles	3.00
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	1.33
P3 cycles	1.33
P4 cycles	1.17
P5 cycles	1.17
P6 cycles	3.00
P7 cycles	3.00
P8 cycles	3.00
P9 cycles	3.00
P10 cycles	1.00
P11 cycles	1.00
P12 cycles	3.33
P13 cycles	3.33
P14 cycles	3.33
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	24.00
Nb uops	24.00
Nb loads	NA
Nb stores	6.00
Nb stack references	0.00
FLOP/cycle	1.20
Nb FLOP add-sub	0.00
Nb FLOP mul	4.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	48.00
Bytes prefetched	0.00
Bytes loaded	64.00
Bytes stored	96.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	5.00
Stride indirect	0.00
Vectorization ratio all	92.31
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	96.15
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.11
Bottlenecks	P12, P13, P14,
Function	cg_init(int, int, int, int, double, double, double, double const, double const, double, double, double, double, double, double*) [clone .omp_outlined]
Source	cg.cpp:21-25
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	4
CQA cycles	3.33
CQA cycles if no scalar integer	3.33
CQA cycles if FP arith vectorized	3.33
CQA cycles if fully vectorized	3.33
Front-end cycles	3.00
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	1.33
P3 cycles	1.33
P4 cycles	1.17
P5 cycles	1.17
P6 cycles	3.00
P7 cycles	3.00
P8 cycles	3.00
P9 cycles	3.00
P10 cycles	1.00
P11 cycles	1.00
P12 cycles	3.33
P13 cycles	3.33
P14 cycles	3.33
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	24.00
Nb uops	24.00
Nb loads	NA
Nb stores	6.00
Nb stack references	0.00
FLOP/cycle	1.20
Nb FLOP add-sub	0.00
Nb FLOP mul	4.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	48.00
Bytes prefetched	0.00
Bytes loaded	64.00
Bytes stored	96.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	5.00
Stride indirect	0.00
Vectorization ratio all	92.31
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	96.15
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	cg_init(int, int, int, int, double, double, double, double const, double const, double, double, double, double, double, double*) [clone .omp_outlined]
Source file and lines	cg.cpp:21-25
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/174-118-5752/intel/TeaLeaf/build/TeaLeaf/src/omp/cg.cpp:21-25.

The related source loop is unrolled by 4 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. 96% of vector register length is used (average across all VPU instructions).

Details

92% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU addition or subtraction instructions are used in vector version.

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 4 FP arithmetical operations:

4: multiply

The binary loop is loading 64 bytes. The binary loop is storing 96 bytes.

Arithmetic intensity

Arithmetic intensity is 0.02 FP operations per loaded or stored byte.

General properties

nb instructions	24
loop length	96
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	0.50	0.50	1.33	1.33	1.17	1.17	3.00	3.00	3.00	3.00	1.00	1.00	3.33	3.33	3.33	0.00	0.00
cycles	0.50	0.50	1.33	1.33	1.17	1.17	3.00	3.00	3.00	3.00	1.00	1.00	3.33	3.33	3.33	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	3.00
Data deps.	2.00
Overall L1	3.33

Vectorization ratios

INT

all	90%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	92%
load	100%
store	100%
mul	100%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.33 cycles. At this rate:

20% of peak load performance is reached (19.20 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
59% of peak store performance is reached (28.80 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 401c20

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
ADD X1, X24, X21	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ST1B {Z0.B}, P0, [X24, X21]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
ADD X17, X26, X21	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ST1D {Z0.D}, P1, [X1, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
ADD X1, X25, X21	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
DECW X30, ALL	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (50.0%)
ST1B {Z0.B}, P0, [X25, X21]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
ADDVL X25, X25, #2	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	N/A
ADDVL X24, X24, #2	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	N/A
ST1D {Z0.D}, P1, [X1, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
ADD X1, X27, X21	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LD1B {Z1.B}, P0/Z, [X26, X21]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1B {Z2.B}, P0/Z, [X27, X21]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z3.D}, P1/Z, [X17, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z4.D}, P1/Z, [X1, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
ADD X17, X28, X21	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADDVL X27, X27, #2	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	N/A
ADDVL X26, X26, #2	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	N/A
FMUL Z1.D, Z1.D, Z2.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FMUL Z2.D, Z3.D, Z4.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
ST1B {Z1.B}, P0, [X28, X21]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
ADDVL X28, X28, #2	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	N/A
ST1D {Z2.D}, P1, [X17, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
CBNZ X30, 401c20 <_Z7cg_initiiiiddPdPKdS1_S_S_S_S_S_S_.omp_outlined+0x274>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	cg_init(int, int, int, int, double, double, double, double const, double const, double, double, double, double, double, double*) [clone .omp_outlined]
Source file and lines	cg.cpp:21-25
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/174-118-5752/intel/TeaLeaf/build/TeaLeaf/src/omp/cg.cpp:21-25.

The related source loop is unrolled by 4 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. 96% of vector register length is used (average across all VPU instructions).

Details

92% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU addition or subtraction instructions are used in vector version.

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 4 FP arithmetical operations:

4: multiply

The binary loop is loading 64 bytes. The binary loop is storing 96 bytes.

Arithmetic intensity

Arithmetic intensity is 0.02 FP operations per loaded or stored byte.

General properties

nb instructions	24
loop length	96
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	0.50	0.50	1.33	1.33	1.17	1.17	3.00	3.00	3.00	3.00	1.00	1.00	3.33	3.33	3.33	0.00	0.00
cycles	0.50	0.50	1.33	1.33	1.17	1.17	3.00	3.00	3.00	3.00	1.00	1.00	3.33	3.33	3.33	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	3.00
Data deps.	2.00
Overall L1	3.33

Vectorization ratios

INT

all	90%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	92%
load	100%
store	100%
mul	100%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.33 cycles. At this rate:

20% of peak load performance is reached (19.20 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
59% of peak store performance is reached (28.80 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 401c20

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
ADD X1, X24, X21	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ST1B {Z0.B}, P0, [X24, X21]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
ADD X17, X26, X21	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ST1D {Z0.D}, P1, [X1, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
ADD X1, X25, X21	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
DECW X30, ALL	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (50.0%)
ST1B {Z0.B}, P0, [X25, X21]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
ADDVL X25, X25, #2	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	N/A
ADDVL X24, X24, #2	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	N/A
ST1D {Z0.D}, P1, [X1, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
ADD X1, X27, X21	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LD1B {Z1.B}, P0/Z, [X26, X21]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1B {Z2.B}, P0/Z, [X27, X21]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z3.D}, P1/Z, [X17, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LD1D {Z4.D}, P1/Z, [X1, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
ADD X17, X28, X21	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADDVL X27, X27, #2	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	N/A
ADDVL X26, X26, #2	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	N/A
FMUL Z1.D, Z1.D, Z2.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FMUL Z2.D, Z3.D, Z4.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
ST1B {Z1.B}, P0, [X28, X21]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
ADDVL X28, X28, #2	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	N/A
ST1D {Z2.D}, P1, [X17, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
CBNZ X30, 401c20 <_Z7cg_initiiiiddPdPKdS1_S_S_S_S_S_S_.omp_outlined+0x274>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code