OV - exec - Function calculate_residual(int, int, int, double const*, double const*, double*, double const*, double const*) [clone .omp

	Function: calculate_residual(int, int, int, double const, double const, double, double const, do ...	Module: exec	Source: solver_methods.cpp:66-72	Coverage (incl. loops): 0.01% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-118-5752/intel/TeaLeaf/build/TeaLeaf/src/omp/solver_methods.cpp: 66 - 72

--------------------------------------------------------------------------------

66:   #pragma omp parallel for

67: #endif

68:   for (int jj = halo_depth; jj < y - halo_depth; ++jj) {

69:     for (int kk = halo_depth; kk < x - halo_depth; ++kk) {

70:       const int index = kk + jj * x;

71:       const double smvp = tealeaf_SMVP(u);

72:       r[index] = u0[index] - smvp;

0x40a434 SUB	SP, SP, #272

0x40a438 STP	X29, X30, [SP, #176]

0x40a43c STP	X28, X27, [SP, #192]

0x40a440 STP	X26, X25, [SP, #208]

0x40a444 STP	X24, X23, [SP, #224]

0x40a448 STP	X22, X21, [SP, #240]

0x40a44c STP	X20, X19, [SP, #256]

0x40a450 ADD	X29, SP, #176

0x40a454 LDRSW	X22, [X3]

0x40a458 LDR	W8, [X2]

0x40a45c SUB	W8, W8, W22

0x40a460 CMP	W22, W8

0x40a464 B.GE	40a8b4

0x40a468 ORN	W9, WZR, W22

0x40a46c LDR	W1, [X0]

0x40a470 ORR	X20, XZR, X4

0x40a474 ORR	X23, XZR, X5

0x40a478 ORR	X21, XZR, X6

0x40a47c ORR	X19, XZR, X7

0x40a480 MOVZ	W10, #1

0x40a484 ADD	W24, W8, W9

0x40a488 ADRP	X0,

0x40a48c ADD	X0, X0, #3152

0x40a490 SUB	X3, X29, #24

0x40a494 SUB	X4, X29, #12

0x40a498 SUB	X5, X29, #16

0x40a49c SUB	X6, X29, #20

0x40a4a0 MOVZ	W2, #34

0x40a4a4 MOVZ	W7, #1

0x40a4a8 STP	WZR, W10, [X29, #488]

0x40a4ac STP	W24, WZR, [X29, #496]

0x40a4b0 STR	W1, [SP, #20]

0x40a4b4 STR	W10, [SP]

0x40a4b8 BL	4014d0

0x40a4bc LDP	W8, W9, [X29, #496]

0x40a4c0 CMP	W8, W24

0x40a4c4 CSEL	W8, W8, W24, #3

0x40a4c8 ADD	W10, W8, #1

0x40a4cc CMP	W9, W10

0x40a4d0 B.CS	40a8a4

0x40a4d4 LDRSW	X10, [X20]

0x40a4d8 SUB	W11, W10, W22

0x40a4dc CMP	W22, W11

0x40a4e0 B.GE	40a8a4

0x40a4e4 UBFM	X18, X22, #61, #60

0x40a4e8 LDR	X28, [X23]

0x40a4ec MOVZ	W17, #8

0x40a4f0 LDP	X15, X16, [X29, #96]

0x40a4f4 LDR	X13, [X21]

0x40a4f8 SUB	X1, X17, X18

0x40a4fc UBFM	X0, X10, #60, #59

0x40a500 LDR	X14, [X19]

0x40a504 ADD	X12, X28, X1

0x40a508 ADD	W2, W9, W22

0x40a50c FMOV	D0, #1.0000000

0x40a510 STR	X12, [SP, #56]

0x40a514 SUB	X12, X13, X18

0x40a518 LDR	X17, [X16]

0x40a51c STUR	X12, [X29, #448]

0x40a520 ADD	X12, X22, X10

0x40a524 SUB	X16, X0, X18

0x40a528 STUR	X12, [X29, #456]

0x40a52c ADD	X12, X13, X16

0x40a530 LDR	X15, [X15]

0x40a534 STUR	X12, [X29, #440]

0x40a538 SUB	X12, X14, X18

0x40a53c SUB	X23, X10, X22,LSL #1

0x40a540 STUR	X12, [X29, #432]

0x40a544 ADD	X12, X14, X16

0x40a548 ADD	X16, X14, X1

0x40a54c STR	X12, [SP, #88]

0x40a550 SUB	X12, X14, #8

0x40a554 PTRUE	P0.D, ALL

0x40a558 STP	X16, X12, [SP, #72]

0x40a55c CNTD	X12, ALL

0x40a560 ORR	W11, WZR, WZR

0x40a564 CMP	X12, #4

0x40a568 MOVZ	W16, #4

0x40a56c CSEL	X12, X12, X16, #8

0x40a570 MADD	W16, W10, W2, WZR

0x40a574 SUB	X30, X15, X18

0x40a578 STUR	X12, [X29, #480]

0x40a57c ADD	X12, X14, X18

0x40a580 SUB	X4, X22, X10

0x40a584 STR	X12, [SP, #32]

0x40a588 ADD	X12, X13, X18

0x40a58c SUB	X0, X17, X18

0x40a590 STR	X12, [SP, #24]

0x40a594 SUB	X12, XZR, X10

0x40a598 ORR	W25, WZR, W2

0x40a59c STUR	X12, [X29, #472]

0x40a5a0 ADD	X12, X28, #8

0x40a5a4 MOVZ	X20, #1

0x40a5a8 MOVN	X26, #0

0x40a5ac STR	X0, [SP, #64]

0x40a5b0 STUR	X12, [X29, #464]

0x40a5b4 STR	X30, [SP, #48]

0x40a5b8 STR	W8, [SP, #44]

0x40a5bc B	40a5d4

(128) 0x40a5c0 CMP	W9, W8

(128) 0x40a5c4 ADD	W9, W9, #1

(128) 0x40a5c8 ADD	W11, W11, #1

(128) 0x40a5cc ADD	W16, W27, W10

(128) 0x40a5d0 B.EQ	40a8a4

(128) 0x40a5d4 LDUR	X12, [X29, #480]

(128) 0x40a5d8 SBFM	X27, X16, #0, #31

(128) 0x40a5dc SBFM	X19, X16, #61, #31

(128) 0x40a5e0 ORR	X21, XZR, X22

(128) 0x40a5e4 CMP	X23, X12

(128) 0x40a5e8 B.CS	40a6a0

(128) 0x40a5ec LDUR	X1, [X29, #472]

(128) 0x40a5f0 ADD	X12, X21, X27

(128) 0x40a5f4 ADD	X16, X19, X21,LSL #3

(128) 0x40a5f8 ADD	X18, X12, X10

(128) 0x40a5fc ORR	X0, XZR, XZR

(128) 0x40a600 ADD	X2, X12, X1

(128) 0x40a604 UBFM	X12, X12, #61, #60

(128) 0x40a608 UBFM	X18, X18, #61, #60

(128) 0x40a60c ADD	X3, X14, X2,LSL #3

(128) 0x40a610 LDUR	X2, [X29, #464]

(128) 0x40a614 ADD	X1, X4, X21

(128) 0x40a618 ADD	X19, X13, X16

(128) 0x40a61c ADD	X5, X13, X18

(128) 0x40a620 ADD	X6, X14, X18

(128) 0x40a624 ADD	X21, X2, X12

(128) 0x40a628 ADD	X7, X14, X16

(128) 0x40a62c ADD	X16, X17, X12

(128) 0x40a630 ADD	X18, X15, X12

  (127) 0x40a634 ADD	X12, X21, X0

  (127) 0x40a638 LDR	D4, [X5, X0]

  (127) 0x40a63c LDR	D5, [X19, X0]

  (127) 0x40a640 LDP	D2, D1, [X12, #1016]

  (127) 0x40a644 ADD	X12, X7, X0

  (127) 0x40a648 LDUR	D6, [X12, #504]

  (127) 0x40a64c FADD	D7, D4, D5

  (127) 0x40a650 LDR	D16, [X3, X0]

  (127) 0x40a654 ADDS	X1, X1, #1

  (127) 0x40a658 FADD	D3, D1, D2

  (127) 0x40a65c FMUL	D2, D2, D6

  (127) 0x40a660 LDR	D6, [X12, #8]

  (127) 0x40a664 FADD	D3, D3, D0

  (127) 0x40a668 FMADD	D1, D1, D6, D2

  (127) 0x40a66c FMUL	D2, D5, D16

  (127) 0x40a670 LDR	D5, [X12]

  (127) 0x40a674 LDR	D6, [X6, X0]

  (127) 0x40a678 FADD	D3, D3, D7

  (127) 0x40a67c FMADD	D2, D4, D6, D2

  (127) 0x40a680 FNMSUB	D1, D3, D5, D1

  (127) 0x40a684 FSUB	D1, D1, S2

  (127) 0x40a688 LDR	D2, [X16, X0]

  (127) 0x40a68c FSUB	D1, D2, S1

  (127) 0x40a690 STR	D1, [X18, X0]

  (127) 0x40a694 ADD	X0, X0, #8

  (127) 0x40a698 B.CC	40a634

(128) 0x40a69c B	40a5c0

(128) 0x40a6a0 ADD	W16, W25, W11

(128) 0x40a6a4 LDUR	X12, [X29, #456]

(128) 0x40a6a8 ORR	X24, XZR, X23

(128) 0x40a6ac MADD	W16, W10, W16, WZR

(128) 0x40a6b0 SBFM	X18, X16, #0, #31

(128) 0x40a6b4 ADD	X0, X10, X18

(128) 0x40a6b8 ADD	X1, X22, X18

(128) 0x40a6bc UBFM	X5, X0, #61, #60

(128) 0x40a6c0 SBFM	X0, X16, #61, #31

(128) 0x40a6c4 ADD	X16, X12, X18

(128) 0x40a6c8 LDUR	X12, [X29, #448]

(128) 0x40a6cc UBFM	X3, X1, #61, #60

(128) 0x40a6d0 UBFM	X1, X16, #61, #60

(128) 0x40a6d4 ADD	X7, X30, X5

(128) 0x40a6d8 ADD	X18, X4, X18

(128) 0x40a6dc ADD	X16, X12, X5

(128) 0x40a6e0 LDUR	X12, [X29, #440]

(128) 0x40a6e4 ADD	X6, X15, X3

(128) 0x40a6e8 ADD	X2, X13, X3

(128) 0x40a6ec CMP	X6, X16

(128) 0x40a6f0 ADD	X23, X14, X18,LSL #3

(128) 0x40a6f4 ADD	X21, X12, X0

(128) 0x40a6f8 LDUR	X12, [X29, #432]

(128) 0x40a6fc CCMP	X2, X7, #2, #3

(128) 0x40a700 ADD	X2, X13, X1

(128) 0x40a704 CSINC	W16, WZR, WZR, #2

(128) 0x40a708 CMP	X6, X21

(128) 0x40a70c ADD	X21, X12, X0

(128) 0x40a710 LDR	X12, [SP, #88]

(128) 0x40a714 CCMP	X2, X7, #2, #3

(128) 0x40a718 CSINC	W18, WZR, WZR, #2

(128) 0x40a71c CMP	X6, X21

(128) 0x40a720 ADD	X1, X14, X1

(128) 0x40a724 ADD	X2, X12, X0

(128) 0x40a728 LDR	X12, [SP, #72]

(128) 0x40a72c CCMP	X23, X7, #2, #3

(128) 0x40a730 CSINC	W0, WZR, WZR, #2

(128) 0x40a734 CMP	X6, X2

(128) 0x40a738 ADD	X2, X12, X5

(128) 0x40a73c LDR	X12, [SP, #80]

(128) 0x40a740 CCMP	X1, X7, #2, #3

(128) 0x40a744 CSINC	W1, WZR, WZR, #2

(128) 0x40a748 CMP	X6, X2

(128) 0x40a74c ADD	X21, X12, X3

(128) 0x40a750 LDR	X12, [SP, #64]

(128) 0x40a754 CCMP	X21, X7, #2, #3

(128) 0x40a758 ADD	X21, X17, X3

(128) 0x40a75c ADD	X23, X12, X5

(128) 0x40a760 CSINC	W2, WZR, WZR, #2

(128) 0x40a764 LDR	X12, [SP, #56]

(128) 0x40a768 CMP	X6, X23

(128) 0x40a76c ADD	X23, X28, X3

(128) 0x40a770 CCMP	X21, X7, #2, #3

(128) 0x40a774 ADD	X5, X12, X5

(128) 0x40a778 ORR	X21, XZR, X22

(128) 0x40a77c CSINC	W3, WZR, WZR, #2

(128) 0x40a780 CMP	X23, X7

(128) 0x40a784 ORR	X23, XZR, X24

(128) 0x40a788 CCMP	X6, X5, #2, #3

(128) 0x40a78c B.CC	40a5ec

(128) 0x40a790 ORR	X21, XZR, X22

(128) 0x40a794 TBNZ	W16, #0, 40a5ec

(128) 0x40a798 ORR	X21, XZR, X22

(128) 0x40a79c TBNZ	W18, #0, 40a5ec

(128) 0x40a7a0 ORR	X21, XZR, X22

(128) 0x40a7a4 TBNZ	W0, #0, 40a5ec

(128) 0x40a7a8 ORR	X21, XZR, X22

(128) 0x40a7ac TBNZ	W1, #0, 40a5ec

(128) 0x40a7b0 ORR	X21, XZR, X22

(128) 0x40a7b4 TBNZ	W2, #0, 40a5ec

(128) 0x40a7b8 ORR	X21, XZR, X22

(128) 0x40a7bc TBNZ	W3, #0, 40a5ec

(128) 0x40a7c0 LDUR	X12, [X29, #456]

(128) 0x40a7c4 ADD	X16, X22, X27

(128) 0x40a7c8 ADD	X18, X4, X27

(128) 0x40a7cc UBFM	X21, X16, #61, #60

(128) 0x40a7d0 ADD	X5, X14, X18,LSL #3

(128) 0x40a7d4 ORR	X0, XZR, XZR

(128) 0x40a7d8 ADD	X2, X12, X27

(128) 0x40a7dc LDR	X12, [SP, #32]

(128) 0x40a7e0 ORR	X30, XZR, X28

(128) 0x40a7e4 UBFM	X2, X2, #61, #60

(128) 0x40a7e8 ADD	X6, X15, X21

(128) 0x40a7ec ADD	X16, X17, X21

(128) 0x40a7f0 ADD	X1, X12, X19

(128) 0x40a7f4 LDR	X12, [SP, #24]

(128) 0x40a7f8 ADD	X18, X14, X2

(128) 0x40a7fc ADD	X3, X12, X19

(128) 0x40a800 CNTD	X12, ALL

(128) 0x40a804 SUB	X7, XZR, X12

(128) 0x40a808 AND	X7, X23, X7

(128) 0x40a80c ADD	X23, X13, X2

(128) 0x40a810 ADD	X2, X28, X21

(128) 0x40a814 ADD	X21, X7, X22

  (129) 0x40a818 UBFM	X12, X0, #61, #60

  (129) 0x40a81c LD1D	{Z2.D}, P0/Z, [X2, X0,LSL #3]

  (129) 0x40a820 LD1D	{Z4.D}, P0/Z, [X23, X0,LSL #3]

  (129) 0x40a824 LD1D	{Z5.D}, P0/Z, [X3, X0,LSL #3]

  (129) 0x40a828 LD1D	{Z16.D}, P0/Z, [X5, X0,LSL #3]

  (129) 0x40a82c ADD	X28, X2, X12

  (129) 0x40a830 ADD	X12, X1, X12

  (129) 0x40a834 LD1D	{Z1.D}, P0/Z, [X28, X20,LSL #3]

  (129) 0x40a838 LD1D	{Z6.D}, P0/Z, [X12, X26,LSL #3]

  (129) 0x40a83c FADD	Z7.D, Z4.D, Z5.D

  (129) 0x40a840 FADD	Z3.D, Z1.D, Z2.D

  (129) 0x40a844 FMUL	Z2.D, Z2.D, Z6.D

  (129) 0x40a848 LD1D	{Z6.D}, P0/Z, [X12, X20,LSL #3]

  (129) 0x40a84c FADD	Z3.D, P0/M, Z3.D, #1

  (129) 0x40a850 FMAD	Z1.D, P0/M, Z6.D, Z2.D

  (129) 0x40a854 FMUL	Z2.D, Z5.D, Z16.D

  (129) 0x40a858 LD1D	{Z5.D}, P0/Z, [X1, X0,LSL #3]

  (129) 0x40a85c LD1D	{Z6.D}, P0/Z, [X18, X0,LSL #3]

  (129) 0x40a860 FADD	Z3.D, Z3.D, Z7.D

  (129) 0x40a864 FMLA	Z2.D, P0/M, Z4.D, Z6.D

  (129) 0x40a868 FNMLS	Z1.D, P0/M, Z3.D, Z5.D

  (129) 0x40a86c FSUB	Z1.D, Z1.D, Z2.D

  (129) 0x40a870 LD1D	{Z2.D}, P0/Z, [X16, X0,LSL #3]

  (129) 0x40a874 FSUB	Z1.D, Z2.D, Z1.D

  (129) 0x40a878 ST1D	{Z1.D}, P0, [X6, X0,LSL #3]

  (129) 0x40a87c INCD	X0, ALL

  (129) 0x40a880 CMP	X7, X0

  (129) 0x40a884 B.NE	40a818

(128) 0x40a888 ORR	X28, XZR, X30

(128) 0x40a88c LDR	W8, [SP, #44]

(128) 0x40a890 LDR	X30, [SP, #48]

(128) 0x40a894 ORR	X23, XZR, X24

(128) 0x40a898 CMP	X24, X7

(128) 0x40a89c B.EQ	40a5c0

(128) 0x40a8a0 B	40a5ec

0x40a8a4 LDR	W1, [SP, #20]

0x40a8a8 ADRP	X0,

0x40a8ac ADD	X0, X0, #3176

0x40a8b0 BL	4013f0

0x40a8b4 LDP	X20, X19, [SP, #256]

0x40a8b8 LDP	X22, X21, [SP, #240]

0x40a8bc LDP	X24, X23, [SP, #224]

0x40a8c0 LDP	X26, X25, [SP, #208]

0x40a8c4 LDP	X28, X27, [SP, #192]

0x40a8c8 LDP	X29, X30, [SP, #176]

0x40a8cc ADD	SP, SP, #272

0x40a8d0 RET

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	solver_methods.cpp:66-72
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-118-5752/intel/TeaLeaf/build/TeaLeaf/src/omp/solver_methods.cpp:66-72.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 14.50 to 0.50 cycles (29.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 49% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 14.50 to 9.44 cycles (1.54x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 14.50 to 1.00 cycles (14.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 180 bytes. The binary function is storing 244 bytes.

General properties

nb instructions	111
loop length	444
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

13.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	3.50	3.50	10.33	10.33	10.33	10.33	10.33	10.33	0.25	0.25	0.25	0.25	14.50	14.17	14.33	12.50	12.50
cycles	3.50	3.50	10.33	10.33	10.33	10.33	10.33	10.33	0.25	0.25	0.25	0.25	14.50	14.17	14.33	12.50	12.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	13.88
Overall L1	14.50

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 14.50 cycles. At this rate:

12% of peak load performance is reached (12.41 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
35% of peak store performance is reached (16.83 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 40a434

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
SUB SP, SP, #272	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X29, X30, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X28, X27, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X26, X25, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X24, X23, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X22, X21, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X20, X19, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #176	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDRSW X22, [X3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W8, [X2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SUB W8, W8, W22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W22, W8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 40a8b4 <_Z18calculate_residualiiiPKdS0_PdS0_S0_.omp_outlined+0x480>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORN W9, WZR, W22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
LDR W1, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X20, XZR, X4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X23, XZR, X5	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X21, XZR, X6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X19, XZR, X7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W10, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W24, W8, W9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADRP X0, <42f488>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #3152	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X3, X29, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X4, X29, #12	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X5, X29, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X6, X29, #20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W2, #34	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W7, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STP WZR, W10, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP W24, WZR, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR W1, [SP, #20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR W10, [SP]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 4014d0 <@plt_start@+0x100>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP W8, W9, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP W8, W24	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CSEL W8, W8, W24, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W10, W8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W9, W10	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.CS 40a8a4 <_Z18calculate_residualiiiPKdS0_PdS0_S0_.omp_outlined+0x470>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDRSW X10, [X20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SUB W11, W10, W22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W22, W11	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 40a8a4 <_Z18calculate_residualiiiPKdS0_PdS0_S0_.omp_outlined+0x470>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X18, X22, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X28, [X23]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
MOVZ W17, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
LDP X15, X16, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X13, [X21]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
SUB X1, X17, X18	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
UBFM X0, X10, #60, #59	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X14, [X19]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD X12, X28, X1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD W2, W9, W22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
FMOV D0, #1.0000000	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
STR X12, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
SUB X12, X13, X18	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X17, [X16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
STUR X12, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X12, X22, X10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X16, X0, X18	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STUR X12, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X12, X13, X16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X15, [X15]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X12, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
SUB X12, X14, X18	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X23, X10, X22,LSL #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STUR X12, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X12, X14, X16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X16, X14, X1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X12, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
SUB X12, X14, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
PTRUE P0.D, ALL	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (100.0%)
STP X16, X12, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
CNTD X12, ALL	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (50.0%)
ORR W11, WZR, WZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP X12, #4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
MOVZ W16, #4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CSEL X12, X12, X16, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MADD W16, W10, W2, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
SUB X30, X15, X18	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STUR X12, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X12, X14, X18	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X4, X22, X10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR X12, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X12, X13, X18	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X0, X17, X18	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X12, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
SUB X12, XZR, X10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR W25, WZR, W2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STUR X12, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X12, X28, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ X20, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVN X26, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR X0, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STUR X12, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X30, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR W8, [SP, #44]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B 40a5d4 <_Z18calculate_residualiiiPKdS0_PdS0_S0_.omp_outlined+0x1a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W1, [SP, #20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADRP X0, <42f8a8>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #3176	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 4013f0 <@plt_start@+0x20>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X20, X19, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X22, X21, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X24, X23, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X26, X25, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X28, X27, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X29, X30, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
ADD SP, SP, #272	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	solver_methods.cpp:66-72
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-118-5752/intel/TeaLeaf/build/TeaLeaf/src/omp/solver_methods.cpp:66-72.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 14.50 to 1.00 cycles (14.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 180 bytes. The binary function is storing 244 bytes.

General properties

nb instructions	111
loop length	444
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

13.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	3.50	3.50	10.33	10.33	10.33	10.33	10.33	10.33	0.25	0.25	0.25	0.25	14.50	14.17	14.33	12.50	12.50
cycles	3.50	3.50	10.33	10.33	10.33	10.33	10.33	10.33	0.25	0.25	0.25	0.25	14.50	14.17	14.33	12.50	12.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	13.88
Overall L1	14.50

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 14.50 cycles. At this rate:

12% of peak load performance is reached (12.41 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
35% of peak store performance is reached (16.83 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 40a434

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
SUB SP, SP, #272	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X29, X30, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X28, X27, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X26, X25, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X24, X23, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X22, X21, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X20, X19, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #176	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDRSW X22, [X3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W8, [X2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SUB W8, W8, W22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W22, W8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 40a8b4 <_Z18calculate_residualiiiPKdS0_PdS0_S0_.omp_outlined+0x480>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORN W9, WZR, W22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
LDR W1, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X20, XZR, X4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X23, XZR, X5	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X21, XZR, X6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X19, XZR, X7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W10, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W24, W8, W9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADRP X0, <42f488>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #3152	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X3, X29, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X4, X29, #12	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X5, X29, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X6, X29, #20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W2, #34	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W7, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STP WZR, W10, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP W24, WZR, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR W1, [SP, #20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR W10, [SP]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 4014d0 <@plt_start@+0x100>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP W8, W9, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP W8, W24	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CSEL W8, W8, W24, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W10, W8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W9, W10	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.CS 40a8a4 <_Z18calculate_residualiiiPKdS0_PdS0_S0_.omp_outlined+0x470>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDRSW X10, [X20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SUB W11, W10, W22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W22, W11	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 40a8a4 <_Z18calculate_residualiiiPKdS0_PdS0_S0_.omp_outlined+0x470>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X18, X22, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X28, [X23]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
MOVZ W17, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
LDP X15, X16, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X13, [X21]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
SUB X1, X17, X18	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
UBFM X0, X10, #60, #59	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X14, [X19]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD X12, X28, X1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD W2, W9, W22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
FMOV D0, #1.0000000	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
STR X12, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
SUB X12, X13, X18	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X17, [X16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
STUR X12, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X12, X22, X10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X16, X0, X18	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STUR X12, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X12, X13, X16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X15, [X15]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X12, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
SUB X12, X14, X18	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X23, X10, X22,LSL #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STUR X12, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X12, X14, X16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X16, X14, X1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X12, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
SUB X12, X14, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
PTRUE P0.D, ALL	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (100.0%)
STP X16, X12, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
CNTD X12, ALL	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (50.0%)
ORR W11, WZR, WZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP X12, #4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
MOVZ W16, #4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CSEL X12, X12, X16, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MADD W16, W10, W2, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
SUB X30, X15, X18	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STUR X12, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X12, X14, X18	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X4, X22, X10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR X12, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X12, X13, X18	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X0, X17, X18	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X12, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
SUB X12, XZR, X10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR W25, WZR, W2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STUR X12, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X12, X28, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ X20, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVN X26, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR X0, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STUR X12, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X30, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR W8, [SP, #44]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B 40a5d4 <_Z18calculate_residualiiiPKdS0_PdS0_S0_.omp_outlined+0x1a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W1, [SP, #20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADRP X0, <42f8a8>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #3176	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 4013f0 <@plt_start@+0x20>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X20, X19, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X22, X21, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X24, X23, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X26, X25, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X28, X27, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X29, X30, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
ADD SP, SP, #272	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼calculate_residual(int, int, int, double const, double const, double, double const, double const*) [clone .omp_outlined]–	0.01	0.02
▼Loop 128 - solver_methods.cpp:68-72 - exec–	0.00	0.00
○Loop 129 - solver_methods.cpp:71-72 - exec	0.01	0.02
○Loop 127 - solver_methods.cpp:69-72 - exec	0.00	0.00

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Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code