OV - exec - Function update_bottom(int, int, int, int, double*, bool) [clone .omp

	Function: update_bottom(int, int, int, int, double*, bool) [clone .omp_outlined]	Module: exec	Source: local_halos.cpp:58-62	Coverage (incl. loops): 0.01% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-118-5752/intel/TeaLeaf/build/TeaLeaf/src/omp/local_halos.cpp: 58 - 62

--------------------------------------------------------------------------------

58:   #pragma omp parallel for

59: #endif

60:     for (int kk = halo_depth; kk < x - halo_depth; ++kk) {

61:       int base = kk;

62:       buffer[base + (halo_depth - jj - 1) * x] = buffer[base + (halo_depth + jj) * x];

0x407468 SUB	SP, SP, #96

0x40746c STP	X29, X30, [SP, #32]

0x407470 STP	X24, X23, [SP, #48]

0x407474 STP	X22, X21, [SP, #64]

0x407478 STP	X20, X19, [SP, #80]

0x40747c ADD	X29, SP, #32

0x407480 LDR	W22, [X3]

0x407484 LDR	W23, [X2]

0x407488 SUB	W8, W23, W22

0x40748c CMP	W22, W8

0x407490 B.GE	407574

0x407494 LDR	W19, [X0]

0x407498 ORN	W9, WZR, W22

0x40749c ORR	X21, XZR, X5

0x4074a0 ORR	X20, XZR, X4

0x4074a4 MOVZ	W10, #1

0x4074a8 ADD	W24, W8, W9

0x4074ac ADRP	X0,

0x4074b0 ADD	X0, X0, #2144

0x4074b4 ADD	X3, SP, #16

0x4074b8 SUB	X4, X29, #4

0x4074bc SUB	X5, X29, #8

0x4074c0 SUB	X6, X29, #12

0x4074c4 ORR	W1, WZR, W19

0x4074c8 MOVZ	W2, #34

0x4074cc MOVZ	W7, #1

0x4074d0 STUR	W10, [X29, #500]

0x4074d4 STP	W24, WZR, [X29, #504]

0x4074d8 STR	WZR, [SP, #16]

0x4074dc STR	W10, [SP]

0x4074e0 BL	4014d0

0x4074e4 LDP	W9, W8, [X29, #504]

0x4074e8 CMP	W9, W24

0x4074ec CSEL	W10, W9, W24, #3

0x4074f0 ADD	W9, W10, #1

0x4074f4 CMP	W8, W9

0x4074f8 B.CS	407564

0x4074fc LDR	W9, [X21]

0x407500 CNTW	X16, ALL

0x407504 SUB	W17, W10, W8

0x407508 CMP	W16, #24

0x40750c MOVZ	W14, #24

0x407510 ADD	W13, W17, #1

0x407514 ADD	W11, W9, W22

0x407518 ORN	W9, WZR, W9

0x40751c CSEL	W14, W16, W14, #8

0x407520 ADD	W9, W22, W9

0x407524 MADD	W11, W11, W23, WZR

0x407528 CMP	W13, W14

0x40752c MADD	W12, W9, W23, WZR

0x407530 LDR	X9, [X20]

0x407534 B.CS	40758c

(82) 0x407538 SUB	W10, W10, W8

(82) 0x40753c ADD	W13, W8, W22

(82) 0x407540 ADD	W8, W10, #1

(82) 0x407544 ADD	W10, W13, W12

(82) 0x407548 ADD	W11, W13, W11

  (81) 0x40754c LDR	D0, [X9, X11,SXTW #3]

  (81) 0x407550 SUBS	W8, W8, #1

  (81) 0x407554 ADD	W11, W11, #1

  (81) 0x407558 STR	D0, [X9, X10,SXTW #3]

  (81) 0x40755c ADD	W10, W10, #1

  (81) 0x407560 B.NE	40754c

(82) 0x407564 ADRP	X0,

(82) 0x407568 ADD	X0, X0, #2168

(82) 0x40756c ORR	W1, WZR, W19

(82) 0x407570 BL	4013f0

(82) 0x407574 LDP	X20, X19, [SP, #80]

(82) 0x407578 LDP	X22, X21, [SP, #64]

(82) 0x40757c LDP	X24, X23, [SP, #48]

(82) 0x407580 LDP	X29, X30, [SP, #32]

(82) 0x407584 ADD	SP, SP, #96

(82) 0x407588 RET

(82) 0x40758c ADD	W15, W8, W22

(82) 0x407590 ADD	W14, W15, W12

(82) 0x407594 ADD	W18, W14, W17

(82) 0x407598 CMP	W18, W14

(82) 0x40759c B.LT	407538

(82) 0x4075a0 ADD	W15, W15, W11

(82) 0x4075a4 ADD	W17, W15, W17

(82) 0x4075a8 CMP	W17, W15

(82) 0x4075ac B.LT	407538

(82) 0x4075b0 ADD	W17, W8, W22

(82) 0x4075b4 ADD	W18, W17, W12

(82) 0x4075b8 ADD	W17, W17, W11

(82) 0x4075bc SBFM	X18, X18, #0, #31

(82) 0x4075c0 SUB	X17, X18, W17,SXTW

(82) 0x4075c4 RDVL	X18, #2

(82) 0x4075c8 CMP	X18, X17,LSL #3

(82) 0x4075cc B.HI	407538

(82) 0x4075d0 SUB	X16, XZR, X16

(82) 0x4075d4 PTRUE	P0.D, ALL

(82) 0x4075d8 ORR	W17, WZR, WZR

(82) 0x4075dc AND	W16, W13, W16

(82) 0x4075e0 ADD	W8, W8, W16

  (83) 0x4075e4 ADD	W18, W15, W17

  (83) 0x4075e8 ADD	W1, W14, W17

  (83) 0x4075ec INCW	X17, ALL

  (83) 0x4075f0 SBFM	X0, X18, #0, #31

  (83) 0x4075f4 ADD	X18, X9, W18,SXTW #3

  (83) 0x4075f8 LD1D	{Z0.D}, P0/Z, [X9, X0,LSL #3]

  (83) 0x4075fc LD1D	{Z1.D}, P0/Z, [X18, #1, MUL VL]

  (83) 0x407600 SBFM	X0, X1, #0, #31

  (83) 0x407604 ADD	X18, X9, W1,SXTW #3

  (83) 0x407608 CMP	W16, W17

  (83) 0x40760c ST1D	{Z0.D}, P0, [X9, X0,LSL #3]

  (83) 0x407610 ST1D	{Z1.D}, P0, [X18, #1, MUL VL]

  (83) 0x407614 B.NE	4075e4

(82) 0x407618 CMP	W13, W16

(82) 0x40761c B.NE	407538

(82) 0x407620 B	407564

Coverage (%)	Name	Source Location	Module
○97.78	__kmp_invoke_microtask		libomp.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	local_halos.cpp:58-62
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-118-5752/intel/TeaLeaf/build/TeaLeaf/src/omp/local_halos.cpp:58-62.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 38% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 6.50 to 3.91 cycles (1.66x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 6.50 to 0.50 cycles (13.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 32 bytes. The binary function is storing 84 bytes.

General properties

nb instructions	52
loop length	208
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

6.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	2.00	2.00	5.83	5.83	5.83	5.83	5.83	5.83	0.00	0.00	0.00	0.00	4.67	4.67	4.67	4.00	4.00
cycles	2.00	2.00	5.83	5.83	5.83	5.83	5.83	5.83	0.00	0.00	0.00	0.00	4.67	4.67	4.67	4.00	4.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.50
Overall L1	6.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 6.50 cycles. At this rate:

5% of peak load performance is reached (4.92 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
26% of peak store performance is reached (12.92 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 407468

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
SUB SP, SP, #96	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STP X29, X30, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X24, X23, [SP, #48]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X22, X21, [SP, #64]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X20, X19, [SP, #80]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR W22, [X3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W23, [X2]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SUB W8, W23, W22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W22, W8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 407574 <_Z13update_bottomiiiiPdb.omp_outlined+0x10c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W19, [X0]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORN W9, WZR, W22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ORR X21, XZR, X5	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ORR X20, XZR, X4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
MOVZ W10, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W24, W8, W9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ADRP X0, <42f4ac>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #2144	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD X3, SP, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
SUB X4, X29, #4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X5, X29, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X6, X29, #12	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
ORR W1, WZR, W19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
MOVZ W2, #34	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
MOVZ W7, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
STUR W10, [X29, #500]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP W24, WZR, [X29, #504]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR WZR, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR W10, [SP]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 4014d0 <@plt_start@+0x100>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP W9, W8, [X29, #504]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP W9, W24	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
CSEL W10, W9, W24, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W9, W10, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W8, W9	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.CS 407564 <_Z13update_bottomiiiiPdb.omp_outlined+0xfc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W9, [X21]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CNTW X16, ALL	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (50.0%)
SUB W17, W10, W8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W16, #24	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
MOVZ W14, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD W13, W17, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD W11, W9, W22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ORN W9, WZR, W9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
CSEL W14, W16, W14, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD W9, W22, W9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
MADD W11, W11, W23, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
CMP W13, W14	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	N/A
MADD W12, W9, W23, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
LDR X9, [X20]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
B.CS 40758c <_Z13update_bottomiiiiPdb.omp_outlined+0x124>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	local_halos.cpp:58-62
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-118-5752/intel/TeaLeaf/build/TeaLeaf/src/omp/local_halos.cpp:58-62.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 6.50 to 0.50 cycles (13.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 32 bytes. The binary function is storing 84 bytes.

General properties

nb instructions	52
loop length	208
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

6.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	2.00	2.00	5.83	5.83	5.83	5.83	5.83	5.83	0.00	0.00	0.00	0.00	4.67	4.67	4.67	4.00	4.00
cycles	2.00	2.00	5.83	5.83	5.83	5.83	5.83	5.83	0.00	0.00	0.00	0.00	4.67	4.67	4.67	4.00	4.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.50
Overall L1	6.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 6.50 cycles. At this rate:

5% of peak load performance is reached (4.92 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
26% of peak store performance is reached (12.92 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 407468

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
SUB SP, SP, #96	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STP X29, X30, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X24, X23, [SP, #48]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X22, X21, [SP, #64]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X20, X19, [SP, #80]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR W22, [X3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W23, [X2]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SUB W8, W23, W22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W22, W8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 407574 <_Z13update_bottomiiiiPdb.omp_outlined+0x10c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W19, [X0]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORN W9, WZR, W22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ORR X21, XZR, X5	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ORR X20, XZR, X4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
MOVZ W10, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W24, W8, W9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ADRP X0, <42f4ac>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #2144	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD X3, SP, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
SUB X4, X29, #4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X5, X29, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X6, X29, #12	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
ORR W1, WZR, W19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
MOVZ W2, #34	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
MOVZ W7, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
STUR W10, [X29, #500]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP W24, WZR, [X29, #504]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR WZR, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR W10, [SP]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 4014d0 <@plt_start@+0x100>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP W9, W8, [X29, #504]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP W9, W24	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
CSEL W10, W9, W24, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W9, W10, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W8, W9	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.CS 407564 <_Z13update_bottomiiiiPdb.omp_outlined+0xfc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W9, [X21]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CNTW X16, ALL	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (50.0%)
SUB W17, W10, W8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W16, #24	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
MOVZ W14, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD W13, W17, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD W11, W9, W22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ORN W9, WZR, W9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
CSEL W14, W16, W14, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD W9, W22, W9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
MADD W11, W11, W23, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
CMP W13, W14	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	N/A
MADD W12, W9, W23, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
LDR X9, [X20]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
B.CS 40758c <_Z13update_bottomiiiiPdb.omp_outlined+0x124>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼update_bottom(int, int, int, int, double*, bool) [clone .omp_outlined]–	0.01	0.02
▼Loop 82 - local_halos.cpp:58-62 - exec–	0.00	0.00
○Loop 83 - local_halos.cpp:62-62 - exec	0.01	0.01
○Loop 81 - local_halos.cpp:60-62 - exec	0.00	0.00

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code