OV - exec - Function update_top(int, int, int, int, double*, bool) [clone .omp

	Function: update_top(int, int, int, int, double*, bool) [clone .omp_outlined]	Module: exec	Source: local_halos.cpp:42-46	Coverage (incl. loops): 0.01% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-118-5752/intel/TeaLeaf/build/TeaLeaf/src/omp/local_halos.cpp: 42 - 46

--------------------------------------------------------------------------------

42:   #pragma omp parallel for

43: #endif

44:     for (int kk = halo_depth; kk < x - halo_depth; ++kk) {

45:       int base = kk;

46:       buffer[base + (y - halo_depth + jj) * x] = buffer[base + (y - halo_depth - 1 - jj) * x];

0x407214 SUB	SP, SP, #96

0x407218 STP	X29, X30, [SP, #16]

0x40721c STR	X25, [SP, #32]

0x407220 STP	X24, X23, [SP, #48]

0x407224 STP	X22, X21, [SP, #64]

0x407228 STP	X20, X19, [SP, #80]

0x40722c ADD	X29, SP, #16

0x407230 LDR	W23, [X3]

0x407234 LDR	W24, [X2]

0x407238 SUB	W8, W24, W23

0x40723c CMP	W23, W8

0x407240 B.GE	407330

0x407244 LDR	W19, [X0]

0x407248 ORN	W9, WZR, W23

0x40724c ORR	X21, XZR, X6

0x407250 ORR	X22, XZR, X5

0x407254 ORR	X20, XZR, X4

0x407258 MOVZ	W10, #1

0x40725c ADD	W25, W8, W9

0x407260 ADRP	X0,

0x407264 ADD	X0, X0, #2072

0x407268 ADD	X3, SP, #8

0x40726c ADD	X4, X29, #28

0x407270 ADD	X5, X29, #24

0x407274 SUB	X6, X29, #4

0x407278 ORR	W1, WZR, W19

0x40727c MOVZ	W2, #34

0x407280 MOVZ	W7, #1

0x407284 STUR	W10, [X29, #508]

0x407288 STP	W25, WZR, [X29, #24]

0x40728c STR	WZR, [SP, #8]

0x407290 STR	W10, [SP]

0x407294 BL	4014d0

0x407298 LDP	W10, W8, [X29, #24]

0x40729c CMP	W10, W25

0x4072a0 CSEL	W9, W10, W25, #3

0x4072a4 ADD	W10, W9, #1

0x4072a8 CMP	W8, W10

0x4072ac B.CS	407320

0x4072b0 LDR	W10, [X22]

0x4072b4 LDR	W11, [X21]

0x4072b8 CNTW	X16, ALL

0x4072bc SUB	W17, W9, W8

0x4072c0 MOVZ	W14, #24

0x4072c4 CMP	W16, #24

0x4072c8 SUB	W10, W10, W23

0x4072cc ORN	W12, WZR, W11

0x4072d0 ADD	W13, W17, #1

0x4072d4 ADD	W12, W10, W12

0x4072d8 ADD	W10, W10, W11

0x4072dc CSEL	W14, W16, W14, #8

0x4072e0 MADD	W11, W12, W24, WZR

0x4072e4 CMP	W13, W14

0x4072e8 MADD	W12, W10, W24, WZR

0x4072ec LDR	X10, [X20]

0x4072f0 B.CS	40734c

(78) 0x4072f4 SUB	W9, W9, W8

(78) 0x4072f8 ADD	W13, W8, W23

(78) 0x4072fc ADD	W8, W9, #1

(78) 0x407300 ADD	W9, W13, W12

(78) 0x407304 ADD	W11, W13, W11

  (77) 0x407308 LDR	D0, [X10, X11,SXTW #3]

  (77) 0x40730c SUBS	W8, W8, #1

  (77) 0x407310 ADD	W11, W11, #1

  (77) 0x407314 STR	D0, [X10, X9,SXTW #3]

  (77) 0x407318 ADD	W9, W9, #1

  (77) 0x40731c B.NE	407308

(78) 0x407320 ADRP	X0,

(78) 0x407324 ADD	X0, X0, #2096

(78) 0x407328 ORR	W1, WZR, W19

(78) 0x40732c BL	4013f0

(78) 0x407330 LDP	X20, X19, [SP, #80]

(78) 0x407334 LDR	X25, [SP, #32]

(78) 0x407338 LDP	X22, X21, [SP, #64]

(78) 0x40733c LDP	X24, X23, [SP, #48]

(78) 0x407340 LDP	X29, X30, [SP, #16]

(78) 0x407344 ADD	SP, SP, #96

(78) 0x407348 RET

(78) 0x40734c ADD	W15, W8, W23

(78) 0x407350 ADD	W14, W15, W12

(78) 0x407354 ADD	W18, W14, W17

(78) 0x407358 CMP	W18, W14

(78) 0x40735c B.LT	4072f4

(78) 0x407360 ADD	W15, W15, W11

(78) 0x407364 ADD	W17, W15, W17

(78) 0x407368 CMP	W17, W15

(78) 0x40736c B.LT	4072f4

(78) 0x407370 ADD	W17, W8, W23

(78) 0x407374 ADD	W18, W17, W12

(78) 0x407378 ADD	W17, W17, W11

(78) 0x40737c SBFM	X18, X18, #0, #31

(78) 0x407380 SUB	X17, X18, W17,SXTW

(78) 0x407384 RDVL	X18, #2

(78) 0x407388 CMP	X18, X17,LSL #3

(78) 0x40738c B.HI	4072f4

(78) 0x407390 SUB	X16, XZR, X16

(78) 0x407394 PTRUE	P0.D, ALL

(78) 0x407398 ORR	W17, WZR, WZR

(78) 0x40739c AND	W16, W13, W16

(78) 0x4073a0 ADD	W8, W8, W16

  (79) 0x4073a4 ADD	W18, W15, W17

  (79) 0x4073a8 ADD	W1, W14, W17

  (79) 0x4073ac INCW	X17, ALL

  (79) 0x4073b0 SBFM	X0, X18, #0, #31

  (79) 0x4073b4 ADD	X18, X10, W18,SXTW #3

  (79) 0x4073b8 LD1D	{Z0.D}, P0/Z, [X10, X0,LSL #3]

  (79) 0x4073bc LD1D	{Z1.D}, P0/Z, [X18, #1, MUL VL]

  (79) 0x4073c0 SBFM	X0, X1, #0, #31

  (79) 0x4073c4 ADD	X18, X10, W1,SXTW #3

  (79) 0x4073c8 CMP	W16, W17

  (79) 0x4073cc ST1D	{Z0.D}, P0, [X10, X0,LSL #3]

  (79) 0x4073d0 ST1D	{Z1.D}, P0, [X18, #1, MUL VL]

  (79) 0x4073d4 B.NE	4073a4

(78) 0x4073d8 CMP	W13, W16

(78) 0x4073dc B.NE	4072f4

(78) 0x4073e0 B	407320

Coverage (%)	Name	Source Location	Module
○99.73	__kmp_invoke_microtask		libomp.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	local_halos.cpp:42-46
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-118-5752/intel/TeaLeaf/build/TeaLeaf/src/omp/local_halos.cpp:42-46.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 37% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 7.00 to 4.16 cycles (1.68x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 7.00 to 0.50 cycles (14.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 36 bytes. The binary function is storing 92 bytes.

General properties

nb instructions	56
loop length	224
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

7.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	2.00	2.00	6.17	6.17	6.17	6.17	6.17	6.17	0.00	0.00	0.00	0.00	5.50	5.17	5.33	4.50	4.50
cycles	2.00	2.00	6.17	6.17	6.17	6.17	6.17	6.17	0.00	0.00	0.00	0.00	5.50	5.17	5.33	4.50	4.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	7.00
Overall L1	7.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 7.00 cycles. At this rate:

5% of peak load performance is reached (5.14 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
27% of peak store performance is reached (13.14 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 407214

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
SUB SP, SP, #96	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STP X29, X30, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X25, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X24, X23, [SP, #48]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X22, X21, [SP, #64]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X20, X19, [SP, #80]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR W23, [X3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W24, [X2]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SUB W8, W24, W23	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W23, W8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 407330 <_Z10update_topiiiiPdb.omp_outlined+0x11c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W19, [X0]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORN W9, WZR, W23	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ORR X21, XZR, X6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ORR X22, XZR, X5	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ORR X20, XZR, X4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
MOVZ W10, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W25, W8, W9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ADRP X0, <42f260>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #2072	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD X3, SP, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD X4, X29, #28	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X5, X29, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X6, X29, #4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
ORR W1, WZR, W19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
MOVZ W2, #34	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
MOVZ W7, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
STUR W10, [X29, #508]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP W25, WZR, [X29, #24]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR WZR, [SP, #8]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR W10, [SP]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 4014d0 <@plt_start@+0x100>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP W10, W8, [X29, #24]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP W10, W25	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
CSEL W9, W10, W25, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W10, W9, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W8, W10	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.CS 407320 <_Z10update_topiiiiPdb.omp_outlined+0x10c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W10, [X22]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W11, [X21]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CNTW X16, ALL	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (50.0%)
SUB W17, W9, W8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
MOVZ W14, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
CMP W16, #24	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
SUB W10, W10, W23	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ORN W12, WZR, W11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W13, W17, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD W12, W10, W12	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W10, W10, W11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
CSEL W14, W16, W14, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
MADD W11, W12, W24, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
CMP W13, W14	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	N/A
MADD W12, W10, W24, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
LDR X10, [X20]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
B.CS 40734c <_Z10update_topiiiiPdb.omp_outlined+0x138>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	local_halos.cpp:42-46
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-118-5752/intel/TeaLeaf/build/TeaLeaf/src/omp/local_halos.cpp:42-46.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 7.00 to 0.50 cycles (14.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 36 bytes. The binary function is storing 92 bytes.

General properties

nb instructions	56
loop length	224
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

7.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	2.00	2.00	6.17	6.17	6.17	6.17	6.17	6.17	0.00	0.00	0.00	0.00	5.50	5.17	5.33	4.50	4.50
cycles	2.00	2.00	6.17	6.17	6.17	6.17	6.17	6.17	0.00	0.00	0.00	0.00	5.50	5.17	5.33	4.50	4.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	7.00
Overall L1	7.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 7.00 cycles. At this rate:

5% of peak load performance is reached (5.14 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
27% of peak store performance is reached (13.14 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 407214

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
SUB SP, SP, #96	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STP X29, X30, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X25, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X24, X23, [SP, #48]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X22, X21, [SP, #64]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X20, X19, [SP, #80]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR W23, [X3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W24, [X2]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SUB W8, W24, W23	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W23, W8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 407330 <_Z10update_topiiiiPdb.omp_outlined+0x11c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W19, [X0]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORN W9, WZR, W23	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ORR X21, XZR, X6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ORR X22, XZR, X5	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ORR X20, XZR, X4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
MOVZ W10, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W25, W8, W9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ADRP X0, <42f260>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #2072	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD X3, SP, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD X4, X29, #28	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X5, X29, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X6, X29, #4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
ORR W1, WZR, W19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
MOVZ W2, #34	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
MOVZ W7, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
STUR W10, [X29, #508]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP W25, WZR, [X29, #24]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR WZR, [SP, #8]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR W10, [SP]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 4014d0 <@plt_start@+0x100>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP W10, W8, [X29, #24]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP W10, W25	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
CSEL W9, W10, W25, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W10, W9, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W8, W10	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.CS 407320 <_Z10update_topiiiiPdb.omp_outlined+0x10c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W10, [X22]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W11, [X21]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CNTW X16, ALL	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (50.0%)
SUB W17, W9, W8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
MOVZ W14, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
CMP W16, #24	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
SUB W10, W10, W23	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ORN W12, WZR, W11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W13, W17, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD W12, W10, W12	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W10, W10, W11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
CSEL W14, W16, W14, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
MADD W11, W12, W24, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
CMP W13, W14	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	N/A
MADD W12, W10, W24, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
LDR X10, [X20]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
B.CS 40734c <_Z10update_topiiiiPdb.omp_outlined+0x138>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼update_top(int, int, int, int, double*, bool) [clone .omp_outlined]–	0.01	0.02
▼Loop 78 - local_halos.cpp:42-46 - exec–	0.00	0.00
○Loop 79 - local_halos.cpp:46-46 - exec	0.01	0.01
○Loop 77 - local_halos.cpp:44-46 - exec	0.00	0.00

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code