OV - exec - Function cg_calc_p(int, int, int, double, double*, double const*) [clone .omp

	Function: cg_calc_p(int, int, int, double, double, double const) [clone .omp_outlined]	Module: exec	Source: cg.cpp:125-131	Coverage (incl. loops): 16.51% \| (excl. loops): 0.01%

/home/hbollore/qaas/qaas-runs/174-118-5752/intel/TeaLeaf/build/TeaLeaf/src/omp/cg.cpp: 125 - 131

--------------------------------------------------------------------------------

125:   #pragma omp parallel for

126: #endif

127:   for (int jj = halo_depth; jj < y - halo_depth; ++jj) {

128:     for (int kk = halo_depth; kk < x - halo_depth; ++kk) {

129:       const int index = kk + jj * x;

130:

131:       p[index] = beta * p[index] + r[index];

0x402c34 SUB	SP, SP, #96

0x402c38 STP	X29, X30, [SP, #16]

0x402c3c STR	X25, [SP, #32]

0x402c40 STP	X24, X23, [SP, #48]

0x402c44 STP	X22, X21, [SP, #64]

0x402c48 STP	X20, X19, [SP, #80]

0x402c4c ADD	X29, SP, #16

0x402c50 LDRSW	X22, [X3]

0x402c54 LDR	W8, [X2]

0x402c58 SUB	W8, W8, W22

0x402c5c CMP	W22, W8

0x402c60 B.GE	402e44

0x402c64 LDR	W20, [X0]

0x402c68 ORN	W9, WZR, W22

0x402c6c ORR	X19, XZR, X6

0x402c70 ORR	X21, XZR, X4

0x402c74 ORR	X24, XZR, X5

0x402c78 ORR	X23, XZR, X7

0x402c7c MOVZ	W10, #1

0x402c80 ADD	W25, W8, W9

0x402c84 ADRP	X0,

0x402c88 ADD	X0, X0, #1256

0x402c8c ADD	X3, SP, #8

0x402c90 ADD	X4, X29, #28

0x402c94 ADD	X5, X29, #24

0x402c98 SUB	X6, X29, #4

0x402c9c ORR	W1, WZR, W20

0x402ca0 MOVZ	W2, #34

0x402ca4 MOVZ	W7, #1

0x402ca8 STUR	W10, [X29, #508]

0x402cac STP	W25, WZR, [X29, #24]

0x402cb0 STR	WZR, [SP, #8]

0x402cb4 STR	W10, [SP]

0x402cb8 BL	4014d0

0x402cbc LDP	W8, W9, [X29, #24]

0x402cc0 CMP	W8, W25

0x402cc4 CSEL	W8, W8, W25, #3

0x402cc8 ADD	W10, W8, #1

0x402ccc CMP	W9, W10

0x402cd0 B.CS	402e34

0x402cd4 LDRSW	X10, [X21]

0x402cd8 SUB	W11, W10, W22

0x402cdc CMP	W22, W11

0x402ce0 B.GE	402e34

0x402ce4 ADD	W14, W9, W22

0x402ce8 LDR	X12, [X24]

0x402cec LDR	X13, [X23]

0x402cf0 UBFM	X17, X22, #61, #60

0x402cf4 MADD	W4, W10, W14, WZR

0x402cf8 SUB	X18, X10, X22,LSL #1

0x402cfc PTRUE	P0.D, ALL

0x402d00 ORR	W11, WZR, WZR

0x402d04 ADD	X15, X19, #8

0x402d08 SUB	X16, X12, X17

0x402d0c SUB	X17, X13, X17

0x402d10 CNTW	X0, ALL

0x402d14 ADDVL	X1, X13, #1

0x402d18 ADDVL	X2, X12, #1

0x402d1c SUB	X3, X22, X10

0x402d20 B	402d38

(22) 0x402d24 CMP	W9, W8

(22) 0x402d28 ADD	W9, W9, #1

(22) 0x402d2c ADD	W11, W11, #1

(22) 0x402d30 ADD	W4, W4, W10

(22) 0x402d34 B.EQ	402e34

(22) 0x402d38 SBFM	X4, X4, #0, #31

(22) 0x402d3c CMP	X18, X0

(22) 0x402d40 ORR	X5, XZR, X22

(22) 0x402d44 B.CS	402d7c

(22) 0x402d48 ADD	X6, X5, X4

(22) 0x402d4c ADD	X5, X3, X5

(22) 0x402d50 UBFM	X7, X6, #61, #60

(22) 0x402d54 ADD	X6, X12, X7

(22) 0x402d58 ADD	X7, X13, X7

  (21) 0x402d5c LDR	D0, [X19]

  (21) 0x402d60 LDR	D1, [X6]

  (21) 0x402d64 ADDS	X5, X5, #1

  (21) 0x402d68 LDR	D2, [X7], #8

  (21) 0x402d6c FMADD	D0, D0, D1, D2

  (21) 0x402d70 STR	D0, [X6], #8

  (21) 0x402d74 B.CC	402d5c

(22) 0x402d78 B	402d24

(22) 0x402d7c ADD	W5, W14, W11

(22) 0x402d80 MADD	W5, W10, W5, WZR

(22) 0x402d84 SBFM	X5, X5, #0, #31

(22) 0x402d88 ADD	X6, X10, X5

(22) 0x402d8c ADD	X5, X22, X5

(22) 0x402d90 UBFM	X6, X6, #61, #60

(22) 0x402d94 UBFM	X5, X5, #61, #60

(22) 0x402d98 ADD	X7, X17, X6

(22) 0x402d9c ADD	X21, X12, X5

(22) 0x402da0 ADD	X5, X13, X5

(22) 0x402da4 ADD	X23, X16, X6

(22) 0x402da8 CMP	X21, X7

(22) 0x402dac CCMP	X5, X23, #2, #3

(22) 0x402db0 ORR	X5, XZR, X22

(22) 0x402db4 CSINC	W6, WZR, WZR, #2

(22) 0x402db8 CMP	X23, X19

(22) 0x402dbc CCMP	X21, X15, #2, #8

(22) 0x402dc0 B.CC	402d48

(22) 0x402dc4 ORR	X5, XZR, X22

(22) 0x402dc8 TBNZ	W6, #0, 402d48

(22) 0x402dcc ADD	X5, X22, X4

(22) 0x402dd0 SUB	X7, XZR, X0

(22) 0x402dd4 LD1RD	{Z0.D}, P0/Z, [X19]

(22) 0x402dd8 UBFM	X5, X5, #61, #60

(22) 0x402ddc AND	X7, X18, X7

(22) 0x402de0 ORR	X6, XZR, XZR

(22) 0x402de4 ADD	X21, X1, X5

(22) 0x402de8 ADD	X23, X13, X5

(22) 0x402dec ADD	X24, X2, X5

(22) 0x402df0 ADD	X25, X12, X5

(22) 0x402df4 ADD	X5, X7, X22

  (23) 0x402df8 LD1D	{Z1.D}, P0/Z, [X25, X6,LSL #3]

  (23) 0x402dfc LD1D	{Z2.D}, P0/Z, [X23, X6,LSL #3]

  (23) 0x402e00 LD1D	{Z3.D}, P0/Z, [X24, X6,LSL #3]

  (23) 0x402e04 LD1D	{Z4.D}, P0/Z, [X21, X6,LSL #3]

  (23) 0x402e08 FMAD	Z1.D, P0/M, Z0.D, Z2.D

  (23) 0x402e0c MOVPRFX	Z2, Z4

  (23) 0x402e10 FMLA	Z2.D, P0/M, Z0.D, Z3.D

  (23) 0x402e14 ST1D	{Z1.D}, P0, [X25, X6,LSL #3]

  (23) 0x402e18 ST1D	{Z2.D}, P0, [X24, X6,LSL #3]

  (23) 0x402e1c INCW	X6, ALL

  (23) 0x402e20 CMP	X7, X6

  (23) 0x402e24 B.NE	402df8

(22) 0x402e28 CMP	X18, X7

(22) 0x402e2c B.EQ	402d24

(22) 0x402e30 B	402d48

0x402e34 ADRP	X0,

0x402e38 ADD	X0, X0, #1280

0x402e3c ORR	W1, WZR, W20

0x402e40 BL	4013f0

0x402e44 LDP	X20, X19, [SP, #80]

0x402e48 LDR	X25, [SP, #32]

0x402e4c LDP	X22, X21, [SP, #64]

0x402e50 LDP	X24, X23, [SP, #48]

0x402e54 LDP	X29, X30, [SP, #16]

0x402e58 ADD	SP, SP, #96

0x402e5c RET

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.01% of application time for run orig_0

Source file and lines	cg.cpp:125-131
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-118-5752/intel/TeaLeaf/build/TeaLeaf/src/omp/cg.cpp:125-131.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 8.88 to 0.50 cycles (17.75x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 43% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 8.88 to 5.81 cycles (1.53x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 8.88 to 1.00 cycles (8.87x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 112 bytes. The binary function is storing 92 bytes.

General properties

nb instructions	71
loop length	284
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

8.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	3.50	3.50	7.58	7.58	7.50	7.50	7.42	7.42	0.00	0.00	0.00	0.00	7.17	6.83	7.00	4.50	4.50
cycles	3.50	3.50	7.58	7.58	7.50	7.50	7.42	7.42	0.00	0.00	0.00	0.00	7.17	6.83	7.00	4.50	4.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	8.88
Overall L1	8.88

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 8.88 cycles. At this rate:

13% of peak load performance is reached (12.62 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
21% of peak store performance is reached (10.37 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 402c34

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
SUB SP, SP, #96	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STP X29, X30, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X25, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X24, X23, [SP, #48]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X22, X21, [SP, #64]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X20, X19, [SP, #80]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDRSW X22, [X3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W8, [X2]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SUB W8, W8, W22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W22, W8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 402e44 <_Z9cg_calc_piiidPdPKd.omp_outlined+0x210>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W20, [X0]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORN W9, WZR, W22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ORR X19, XZR, X6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X21, XZR, X4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ORR X24, XZR, X5	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ORR X23, XZR, X7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
MOVZ W10, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W25, W8, W9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ADRP X0, <42fc84>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #1256	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD X3, SP, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD X4, X29, #28	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X5, X29, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X6, X29, #4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
ORR W1, WZR, W20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
MOVZ W2, #34	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
MOVZ W7, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
STUR W10, [X29, #508]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP W25, WZR, [X29, #24]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR WZR, [SP, #8]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR W10, [SP]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 4014d0 <@plt_start@+0x100>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP W8, W9, [X29, #24]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP W8, W25	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
CSEL W8, W8, W25, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W10, W8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W9, W10	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.CS 402e34 <_Z9cg_calc_piiidPdPKd.omp_outlined+0x200>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDRSW X10, [X21]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SUB W11, W10, W22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W22, W11	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 402e34 <_Z9cg_calc_piiidPdPKd.omp_outlined+0x200>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W14, W9, W22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
LDR X12, [X24]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X13, [X23]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
UBFM X17, X22, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
MADD W4, W10, W14, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
SUB X18, X10, X22,LSL #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
PTRUE P0.D, ALL	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
ORR W11, WZR, WZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ADD X15, X19, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X16, X12, X17	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X17, X13, X17	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
CNTW X0, ALL	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	N/A
ADDVL X1, X13, #1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (50.0%)
ADDVL X2, X12, #1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	N/A
SUB X3, X22, X10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
B 402d38 <_Z9cg_calc_piiidPdPKd.omp_outlined+0x104>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <42fe34>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #1280	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ORR W1, WZR, W20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4013f0 <@plt_start@+0x20>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X20, X19, [SP, #80]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDR X25, [SP, #32]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP X22, X21, [SP, #64]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X24, X23, [SP, #48]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X29, X30, [SP, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
ADD SP, SP, #96	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.01% of application time for run orig_0

Source file and lines	cg.cpp:125-131
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-118-5752/intel/TeaLeaf/build/TeaLeaf/src/omp/cg.cpp:125-131.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 8.88 to 0.50 cycles (17.75x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 8.88 to 1.00 cycles (8.87x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 112 bytes. The binary function is storing 92 bytes.

General properties

nb instructions	71
loop length	284
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

8.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	3.50	3.50	7.58	7.58	7.50	7.50	7.42	7.42	0.00	0.00	0.00	0.00	7.17	6.83	7.00	4.50	4.50
cycles	3.50	3.50	7.58	7.58	7.50	7.50	7.42	7.42	0.00	0.00	0.00	0.00	7.17	6.83	7.00	4.50	4.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	8.88
Overall L1	8.88

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 8.88 cycles. At this rate:

13% of peak load performance is reached (12.62 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
21% of peak store performance is reached (10.37 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 402c34

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
SUB SP, SP, #96	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STP X29, X30, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X25, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X24, X23, [SP, #48]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X22, X21, [SP, #64]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X20, X19, [SP, #80]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDRSW X22, [X3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W8, [X2]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SUB W8, W8, W22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W22, W8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 402e44 <_Z9cg_calc_piiidPdPKd.omp_outlined+0x210>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W20, [X0]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORN W9, WZR, W22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ORR X19, XZR, X6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X21, XZR, X4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ORR X24, XZR, X5	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ORR X23, XZR, X7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
MOVZ W10, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W25, W8, W9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ADRP X0, <42fc84>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #1256	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD X3, SP, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD X4, X29, #28	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X5, X29, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X6, X29, #4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
ORR W1, WZR, W20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
MOVZ W2, #34	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
MOVZ W7, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
STUR W10, [X29, #508]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP W25, WZR, [X29, #24]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR WZR, [SP, #8]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR W10, [SP]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 4014d0 <@plt_start@+0x100>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP W8, W9, [X29, #24]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP W8, W25	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
CSEL W8, W8, W25, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W10, W8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W9, W10	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.CS 402e34 <_Z9cg_calc_piiidPdPKd.omp_outlined+0x200>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDRSW X10, [X21]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SUB W11, W10, W22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W22, W11	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 402e34 <_Z9cg_calc_piiidPdPKd.omp_outlined+0x200>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W14, W9, W22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
LDR X12, [X24]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X13, [X23]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
UBFM X17, X22, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
MADD W4, W10, W14, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
SUB X18, X10, X22,LSL #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
PTRUE P0.D, ALL	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
ORR W11, WZR, WZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ADD X15, X19, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X16, X12, X17	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X17, X13, X17	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
CNTW X0, ALL	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	N/A
ADDVL X1, X13, #1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (50.0%)
ADDVL X2, X12, #1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	N/A
SUB X3, X22, X10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
B 402d38 <_Z9cg_calc_piiidPdPKd.omp_outlined+0x104>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <42fe34>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #1280	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ORR W1, WZR, W20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4013f0 <@plt_start@+0x20>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X20, X19, [SP, #80]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDR X25, [SP, #32]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP X22, X21, [SP, #64]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X24, X23, [SP, #48]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X29, X30, [SP, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
ADD SP, SP, #96	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼cg_calc_p(int, int, int, double, double, double const) [clone .omp_outlined]–	16.51	26.14
▼Loop 22 - cg.cpp:127-131 - exec–	0.01	0.01
○Loop 23 - cg.cpp:128-131 - exec	16.50	25.97
○Loop 21 - cg.cpp:128-131 - exec	0.00	0.00

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code