	*************************************************
	*                                               *
	*          ONE-View report generation           *
	*                                               *
	*************************************************

[MAQAO] Info: Experiment configuration summary is available adding -dbg=1 in command line

* [MAQAO] Warning: Experiment directory /beegfs/hackathon/users/eoseret/qaas_runs_test/178-663-0009/intel/TeaLeaf/run/oneview_runs/defaults/icx/oneview_results_1786630155 already exists and is reused.
           It can be replaced using --replace in the command line.
[MAQAO] Info: 
[MAQAO] Info: START THE APPLICATION PROFILING
[MAQAO] Info: -> RUNNING THE PROFILER...
[MAQAO] Info:   LPROF has already been run
[MAQAO] Info: STOP THE APPLICATION PROFILING
[MAQAO] Info: 
[MAQAO] Info: START FUNCTIONS AND LOOPS ANALYSIS ...
[MAQAO] Info: STOP FUNCTIONS AND LOOPS ANALYSIS ...
[MAQAO] Info: 
[MAQAO] Info: START THE REPORT GENERATION
[MAQAO] Info: -> ONE-VIEW EXPERIMENT DIRECTORY: /beegfs/hackathon/users/eoseret/qaas_runs_test/178-663-0009/intel/TeaLeaf/run/oneview_runs/defaults/icx/oneview_results_1786630155


+====================================================================================================================+
+                                                    1  -  GLOBAL                                                    +
+====================================================================================================================+


+--------------------------------------------------------------------------------------------------------------------+
+                                             1.1  -  Experiment Summary                                             +
+--------------------------------------------------------------------------------------------------------------------+

  Application:			/beegfs/hackathon/users/eoseret/qaas_runs_test/178-663-0009/intel/TeaLeaf/run/oneview_runs/defaults/orig/exec
  Timestamp:			2026-08-13 16:09:15
  Universal Timestamp:		1786630155
  Experiment Type:		MPI; OpenMP; Throughput; 
  Machine:			isix06.benchmarkcenter.megware.com
  Architecture:			x86_64
  Micro Architecture:		GRANITE_RAPIDS
  Model Name:			Intel(R) Xeon(R) 6972P
  Cache Size:			491520 KB
  Number of Cores:		96
  OS Version:			Linux 5.14.0-687.31.1.el9_8.x86_64 #1 SMP PREEMPT_DYNAMIC Sat Aug 1 05:38:01 EDT 2026
  Compilation Options:		
		exec:  --driver-mode=g++ --intel -D USE_OMP -I /beegfs/hackathon/users/eoseret/qaas_runs_test/178-663-0009/intel/TeaLeaf/build/TeaLeaf/src/omp -I /beegfs/hackathon/users/eoseret/qaas_runs_test/178-663-0009/intel/TeaLeaf/build/build/generated -I /beegfs/hackathon/users/eoseret/qaas_runs_test/178-663-0009/intel/TeaLeaf/build/TeaLeaf/driver -g -fno-omit-frame-pointer -fcf-protection=none -no-pie -grecord-command-line -D NDEBUG -std=c++17 -O3 -Wall -march=native -fiopenmp -MD -MT CMakeFiles/tealeaf.dir/src/omp/cg.cpp.o -MF CMakeFiles/tealeaf.dir/src/omp/cg.cpp.o.d -o CMakeFiles/tealeaf.dir/src/omp/cg.cpp.o -c /beegfs/hackathon/users/eoseret/qaas_runs_test/178-663-0009/intel/TeaLeaf/build/TeaLeaf/src/omp/cg.cpp -I /cluster/hpcx/2.22/ompi5-ifx-mt/include -I /cluster/hpcx/2.22/ompi5-ifx-mt/include/openmpi -fveclib=SVML 
  Number of processes observed:	6
  Number of threads observed:	192
  MAQAO version:		2026.1.0
  MAQAO build:			6d1be1d51c1e63266254997eb301734a7264775d::20260810-150026




+--------------------------------------------------------------------------------------------------------------------+
+                                               1.2  -  Global Metrics                                               +
+--------------------------------------------------------------------------------------------------------------------+

  Total Time:				23.66 s
  Max (Thread Active Time):		23.04 s
  Average Active Time:			22.78 s
  Activity Ratio:			99.9 %
  Average number of active threads:	184.870
  Affinity Stability:			99.7 %
  Time spent in analyzed loops:		69.4 %
  Time spent in analyzed innermost loops: 69.2 %
  Time spent in user code:		69.4 %
  Compilation Options Score:		100
  Array Access Efficiency:		99.7 %

   Potential Speedups
  ----------------------------------------------------
  Perfect Flow Complexity:		1.00
  Perfect OpenMP/MPI/Pthread/TBB:	1.22
  Perfect OpenMP/MPI/Pthread/TBB + Load Distribution:	1.44
  If No Scalar Integer:
      Potential Speedup:		1.00
      Nb Loops to get 80%:		2
  If FP Vectorized:
      Potential Speedup:		1.28
      Nb Loops to get 80%:		2
  If Fully Vectorized:
      Potential Speedup:		1.53
      Nb Loops to get 80%:		2
  If Only FP Arithmetic:
      Potential Speedup:		1.00
      Nb Loops to get 80%:		7




+--------------------------------------------------------------------------------------------------------------------+
+                                             1.3  -  Potential Speedups                                             +
+--------------------------------------------------------------------------------------------------------------------+

  If No Scalar Integer:
      Number of loops   | 1      | 5      | 10     | 14     | 19     | 
      Cumulated Speedup | 1.0005 | 1.0010 | 1.0010 | 1.0010 | 1.0010 | 
  Top 5 loops:
    exec - 22:	1.0005
    exec - 25:	1.0009
    exec - 136:	1.001
    exec - 137:	1.001
    exec - 142:	1.001

  If FP Vectorized:
      Number of loops   | 1      | 5      | 10     | 14     | 19     | 
      Cumulated Speedup | 1.1213 | 1.2762 | 1.2762 | 1.2762 | 1.2762 | 
  Top 5 loops:
    exec - 23:	1.1213
    exec - 27:	1.24
    exec - 30:	1.2749
    exec - 22:	1.2757
    exec - 25:	1.2762

  If Fully Vectorized:
      Number of loops   | 1      | 5      | 10     | 14     | 19     | 
      Cumulated Speedup | 1.2060 | 1.5271 | 1.5313 | 1.5328 | 1.5342 | 
  Top 5 loops:
    exec - 27:	1.206
    exec - 23:	1.4409
    exec - 30:	1.524
    exec - 22:	1.5256
    exec - 155:	1.5271

  If Only FP Arithmetic:
      Number of loops   | 1      | 5      | 10     | 14     | 19     | 
      Cumulated Speedup | 1.0006 | 1.0016 | 1.0022 | 1.0023 | 1.0023 | 
  Top 5 loops:
    exec - 22:	1.0006
    exec - 361:	1.0009
    exec - 25:	1.0012
    exec - 136:	1.0015
    exec - 142:	1.0016



+====================================================================================================================+
+                                                   2  -  SUMMARY                                                    +
+====================================================================================================================+


+--------------------------------------------------------------------------------------------------------------------+
+                                             2.1  -  EXPERIMENT QUALITY                                             +
+--------------------------------------------------------------------------------------------------------------------+

  [4 / 4] Application profile is long enough (23.04 s)
To have good quality measurements, it is advised that the application profiling time is greater than 10 seconds.

  [3 / 3] Most of time spent in analyzed modules comes from functions with source/debug info
-g option gives access to debugging informations, such are source locations.

  [2.9950225907586 / 3] Most of time spent in analyzed modules (99.83%) comes from functions compiled with architecture specialization option
-march=native


  [3 / 3] Most of time spent in analyzed modules comes from functions with compilation options informations and
-fno-omit-frame-pointer is present
-fno-omit-frame-pointer improves the accuracy of callchains found during the application profiling.

  [3 / 3] Optimization level option is correctly used


  [3 / 3] Host configuration allows retrieval of all necessary metrics.


  [2 / 2] Application is correctly profiled ("Others" category represents 0.08 % of the execution time)
To have a representative profiling, it is advised that the category "Others" represents less than 20% of the execution
time in order to analyze as much as possible of the user code

  [1 / 1] Lstopo present. The Topology lstopo report will be generated.



+--------------------------------------------------------------------------------------------------------------------+
+                                                2.2  -  CODE QUALITY                                                +
+--------------------------------------------------------------------------------------------------------------------+

  [4 / 4] Enough time of the experiment time spent in analyzed loops (69.36%)
If the time spent in analyzed loops is less than 30%, standard loop optimizations will have a limited impact on
application performances.

  [4 / 4] Threads activity is good
On average, more than 96.29% of observed threads are actually active 

  [4 / 4] CPU activity is good
CPU cores are active 99.89% of time

  [4 / 4] Loop profile is not flat
At least one loop coverage is greater than 4% (34.16%), representing an hotspot for the application

  [4 / 4] Enough time of the experiment time spent in analyzed innermost loops (69.15%)
If the time spent in analyzed innermost loops is less than 15%, standard innermost loop optimizations such as
vectorisation will have a limited impact on application performances.

  [4 / 4] Affinity is good (99.70%)
Threads are not migrating to CPU cores: probably successfully pinned

  [3 / 3] Less than 10% (0.00%) is spend in BLAS1 operations
It could be more efficient to inline by hand BLAS1 operations

  [0 / 3] Too many functions do not use all threads
Functions running on a reduced number of threads (typically sequential code) cover at least 10% of application
walltime (33.28%). Check both "Max Inclusive Time Over Threads" and "Nb Threads" in Functions or Loops tabs and
consider parallelizing sequential regions or improving parallelization of regions running on a reduced number of
threads

  [3 / 3] Cumulative Outermost/In between loops coverage (0.21%) lower than cumulative innermost loop coverage (69.15%)
Having cumulative Outermost/In between loops coverage greater than cumulative innermost loop coverage will make loop
optimization more complex

  [2 / 2] Less than 10% (0.00%) is spend in BLAS2 operations
BLAS2 calls usually could make a poor cache usage and could benefit from inlining.

  [2 / 2] Less than 10% (0.00%) is spend in Libm/SVML (special functions)



+--------------------------------------------------------------------------------------------------------------------+
+                                               2.3  -  LOOPS OVERVIEW                                               +
+--------------------------------------------------------------------------------------------------------------------+

  Top 5 loops:
   + exec - 27  :
     analysis: Execution Time: 34 % - Vectorization Ratio: 100.00 % - Vector Length Use: 50.00 %
     Data Access Issues: 0
        [0] [SA] Inefficient vectorization: more than 10% of the vector loads instructions are unaligned - When
            allocating arrays, don’t forget to align them. There are 0 issues ( = arrays) costing 2 points each

   + exec - 23  :
     analysis: Execution Time: 27 % - Vectorization Ratio: 100.00 % - Vector Length Use: 50.00 %
     Data Access Issues: 0
        [0] [SA] Inefficient vectorization: more than 10% of the vector loads instructions are unaligned - When
            allocating arrays, don’t forget to align them. There are 0 issues ( = arrays) costing 2 points each

   + exec - 30  :
     analysis: Execution Time: 7 % - Vectorization Ratio: 100.00 % - Vector Length Use: 50.00 %
     Data Access Issues: 0
        [0] [SA] Inefficient vectorization: more than 10% of the vector loads instructions are unaligned - When
            allocating arrays, don’t forget to align them. There are 0 issues ( = arrays) costing 2 points each

   + exec - 22  :
     analysis: Execution Time: 0 % - Vectorization Ratio: 53.06 % - Vector Length Use: 29.59 %
     Loop Computation Issues: 2
        [2] [SA] Presence of a large number of scalar integer instructions - Simplify loop structure, perform loop
            splitting or perform unroll and jam. This issue costs 2 points.
     Control Flow Issues: 15
        [13] [SA] Too many paths (9 paths) - Simplify control structure. There are 9 issues ( = paths) costing 1 point
            each with a malus of 4 points.
        [2] [SA] Non innermost loop (Outermost) - Collapse loop with innermost ones. This issue costs 2 points.
     Data Access Issues: 5
        [0] [SA] Inefficient vectorization: more than 10% of the vector loads instructions are unaligned - When
            allocating arrays, don’t forget to align them. There are 0 issues ( = arrays) costing 2 points each
        [3] [SA] Presence of special instructions executing on a single port (INSERT/EXTRACT, SHUFFLE/PERM, BROADCAST)
            - Simplify data access and try to get stride 1 access. There are 3 issues (= instructions) costing 1
            point each.
        [2] [SA] More than 20% of the loads are accessing the stack - Perform loop splitting to decrease pressure on
            registers. This issue costs 2 points.
     Vectorization Roadblocks: 15
        [13] [SA] Too many paths (9 paths) - Simplify control structure. There are 9 issues ( = paths) costing 1 point
            each with a malus of 4 points.
        [2] [SA] Non innermost loop (Outermost) - Collapse loop with innermost ones. This issue costs 2 points.
     Inefficient Vectorization: 5
        [3] [SA] Presence of special instructions executing on a single port (INSERT/EXTRACT, SHUFFLE/PERM, BROADCAST)
            - Simplify data access and try to get stride 1 access. There are 3 issues (= instructions) costing 1
            point each.
        [2] [SA] Inefficient vectorization: use of masked instructions - Simplify control structure. The issue costs 2
            points.

   + exec - 155 :
     analysis: Execution Time: 0 % - Vectorization Ratio: 0.00 % - Vector Length Use: 12.50 %
     Loop Computation Issues: 5
        [5] [SA] Peel/tail loop, considered having a low iteration count - Perform full unroll. Force compiler to use
            masked instructions. This issue costs 5 points.
     Control Flow Issues: 5
        [5] [SA] Peel/tail loop, considered having a low iteration count - Perform full unroll. Force compiler to use
            masked instructions. This issue costs 5 points.
     Data Access Issues: 4
        [4] [SA] Presence of indirect accesses - Use array restructuring or gather instructions to lower the cost.
            There are 1 issues ( = indirect data accesses) costing 4 point each.
     Vectorization Roadblocks: 4
        [4] [SA] Presence of indirect accesses - Use array restructuring or gather instructions to lower the cost.
            There are 1 issues ( = indirect data accesses) costing 4 point each.



+====================================================================================================================+
+                                                 3  -  APPLICATION                                                  +
+====================================================================================================================+


+--------------------------------------------------------------------------------------------------------------------+
+                                               3.1  -  Categorization                                               +
+--------------------------------------------------------------------------------------------------------------------+

   Category | IO     | Exe    | System  | Others  | Memory | String | MPI   | TBB   | OMP   | Pthread | Math  |
  ----------+--------+--------+---------+---------+--------+--------+-------+-------+-------+---------+-------+
   Time (%) | 0.00   | 69.38  | 0.69    | 0.08    | 0.06   | 0.05   | 0.33  | 0.00  | 29.39 | 0.01    | 0.00  |




+--------------------------------------------------------------------------------------------------------------------+
+                                          3.2  -  Function Based Profiling                                          +
+--------------------------------------------------------------------------------------------------------------------+

   Buckets                    | Nb Functions              | Coverage                  | Cumulated Coverage        |
  ----------------------------+---------------------------+---------------------------+---------------------------+
   > 8%                       | 3                         | 87.93                     | 87.93                     |
   4% to 8%                   | 1                         | 7.58                      | 95.51                     |
   2% to 4%                   | 0                         | 0.00                      | 95.51                     |
   1% to 2%                   | 1                         | 1.20                      | 96.71                     |
   0.5% to 1%                 | 2                         | 1.17                      | 97.88                     |
   0.25% to 0.5%              | 1                         | 0.46                      | 98.34                     |
   0.125% to 0.25%            | 1                         | 0.22                      | 98.56                     |
   < 0.125%                   | 189                       | 1.44                      | 100.00                    |




+--------------------------------------------------------------------------------------------------------------------+
+                                            3.3  -  Loop Based Profiling                                            +
+--------------------------------------------------------------------------------------------------------------------+

   Buckets                    | Nb Loops                  | Coverage                  | Cumulated Coverage        |
  ----------------------------+---------------------------+---------------------------+---------------------------+
   > 8%                       | 2                         | 61.20                     | 61.20                     |
   4% to 8%                   | 1                         | 7.57                      | 68.77                     |
   2% to 4%                   | 0                         | 0.00                      | 68.77                     |
   1% to 2%                   | 0                         | 0.00                      | 68.77                     |
   0.5% to 1%                 | 0                         | 0.00                      | 68.77                     |
   0.25% to 0.5%              | 0                         | 0.00                      | 68.77                     |
   0.125% to 0.25%            | 0                         | 0.00                      | 68.77                     |
   < 0.125%                   | 25                        | 0.39                      | 69.15                     |


+====================================================================================================================+
+                                                  4  -  FUNCTIONS                                                   +
+====================================================================================================================+


+--------------------------------------------------------------------------------------------------------------------+
+                                              4.1  -  Top 10 Functions                                              +
+--------------------------------------------------------------------------------------------------------------------+

   Function                                               | Module              | Coverage (%)   | Time (s)       |
  --------------------------------------------------------+---------------------+----------------+----------------+
   cg_calc_ur(int, int, int, double, double*, double*,... | exec                | 34.21          | 7.79           |
   cg_calc_w(int, int, int, double*, double const*, do... | exec                | 27.13          | 6.18           |
   kmp_flag_64<false, true>::wait(kmp_info*, int, void*)  | libiomp5.so         | 26.59          | 6.06           |
   cg_calc_p(int, int, int, double, double*, double co... | exec                | 7.58           | 1.73           |
   kmp_flag_native<unsigned long long, (flag_type)1, t... | libiomp5.so         | 1.20           | 0.27           |
   unknown_kernel_region                                  | kernel              | 0.62           | 0.14           |
   __kmp_hyper_barrier_release(barrier_type, kmp_info*... | libiomp5.so         | 0.55           | 0.13           |
   __kmp_hyper_barrier_gather(barrier_type, kmp_info*,... | libiomp5.so         | 0.46           | 0.11           |
   hmca_bcol_basesmuma_bcast_k_nomial_knownroot_progress  | hmca_bcol_basesm... | 0.22           | 2.37           |
   kmp_flag_native<unsigned long long, (flag_type)1, t... | libiomp5.so         | 0.11           | 0.05           |


+====================================================================================================================+
+                                                    5  -  LOOPS                                                     +
+====================================================================================================================+


+--------------------------------------------------------------------------------------------------------------------+
+                                                5.1  -  Top 10 Loops                                                +
+--------------------------------------------------------------------------------------------------------------------+

   Loop Id        | Module              | Source Location                                        | Coverage (%)   |
  ----------------+---------------------+--------------------------------------------------------+----------------+
   27             | exec                | cg.cpp:108-113                                         | 34.16          |
   23             | exec                | cg.cpp:86-90                                           | 27.04          |
   30             | exec                | cg.cpp:128-131                                         | 7.57           |
   22             | exec                | cg.cpp:83-92                                           | 0.08           |
   155            | exec                | pack_halos.cpp:86-88                                   | 0.08           |
   159            | exec                | pack_halos.cpp:103-105                                 | 0.08           |
   136            | exec                | local_halos.cpp:44-47                                  | 0.06           |
   361            | exec                |                                                        | 0.04           |
   25             | exec                | cg.cpp:105-115                                         | 0.04           |
   139            | exec                | pack_halos.cpp:15-17                                   | 0.02           |





+====================================================================================================================+
+                                                     6  -  CQA                                                      +
+====================================================================================================================+


+--------------------------------------------------------------------------------------------------------------------+
+                                                   6.1  -  Loops                                                    +
+--------------------------------------------------------------------------------------------------------------------+





      6.1.1  -  Loop 27 from exec
  ==========================================================================================================

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/178-663-0009/intel/TeaLeaf/build/TeaLeaf/src/omp/cg.cpp:108-113.

It is main loop of related source loop which is unrolled by 4 (including vectorization).

      6.1.1.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

18% of peak computational performance is used (6.00 out of 32.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.1.1.1  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is vectorized, but using only 256 out of 512 bits (AVX/AVX2 instructions on AVX-512 processors).
<<image_4x64_512>>

Details
All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).


Workaround
Read the "512-bits vectorization" report at "Potential" confidence level.


      6.1.1.1.2  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Found no such bottlenecks but see expert reports for more complex bottlenecks.




      6.1.1.1.3  -  512-bits vectorization
  ----------------------------------------------------------------------------------------------------------

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.


Workaround
Recompile with -mprefer-vector-width=512


      6.1.1.1.4  -  FMA
  ----------------------------------------------------------------------------------------------------------

Detected 12 FMA (fused multiply-add) operations.




      6.1.1.1.5  -  Vector unaligned load/store instructions
  ----------------------------------------------------------------------------------------------------------

Detected 4 optimal vector unaligned load/store instructions.


Details
 - VMOVUPD: 4 occurrences<<list_path_1_vec_align_1>>


Workaround
Use vector aligned instructions:
 1) align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
 2) inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.
<<image_vec_align>>


      6.1.1.1.6  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

3 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).



      6.1.1.1.7  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 24 FP arithmetical operations:
 - 12: addition or subtraction (all inside FMA instructions)
 - 12: multiply (all inside FMA instructions)
The binary loop is loading 128 bytes (16 double precision FP elements).
The binary loop is storing 64 bytes (8 double precision FP elements).


      6.1.1.1.8  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.12 FP operations per loaded or stored byte.







      6.1.2  -  Loop 23 from exec
  ==========================================================================================================

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/178-663-0009/intel/TeaLeaf/build/TeaLeaf/src/omp/cg.cpp:86-90.

It is main loop of related source loop which is unrolled by 4 (including vectorization).

      6.1.2.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

37% of peak computational performance is used (12.00 out of 32.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.2.1.1  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is vectorized, but using only 256 out of 512 bits (AVX/AVX2 instructions on AVX-512 processors).
<<image_4x64_512>>

Details
All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).


Workaround
Read the "512-bits vectorization" report at "Potential" confidence level.


      6.1.2.1.2  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck).

By removing all these bottlenecks, you can lower the cost of an iteration from 5.00 to 4.00 cycles (1.25x speedup).


Workaround
Reduce the number of FP multiply/FMA instructions




      6.1.2.1.3  -  512-bits vectorization
  ----------------------------------------------------------------------------------------------------------

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.


Workaround
Recompile with -mprefer-vector-width=512


      6.1.2.1.4  -  FMA
  ----------------------------------------------------------------------------------------------------------

Detected 20 FMA (fused multiply-add) operations.
Presence of both ADD/SUB and MUL operations.

Workaround
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible.
Estimated speedup by perfect pairing: 1.11x.
For instance a + b*c is a valid FMA (MUL then ADD).
However (a+b)* c cannot be translated into an FMA (ADD then MUL).




      6.1.2.1.5  -  Vector unaligned load/store instructions
  ----------------------------------------------------------------------------------------------------------

Detected 6 optimal vector unaligned load/store instructions.


Details
 - VMOVUPD: 6 occurrences<<list_path_1_vec_align_1>>


Workaround
Use vector aligned instructions:
 1) align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
 2) inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.
<<image_vec_align>>


      6.1.2.1.6  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

10 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).



      6.1.2.1.7  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 60 FP arithmetical operations:
 - 36: addition or subtraction (20 inside FMA instructions)
 - 24: multiply (20 inside FMA instructions)
The binary loop is loading 288 bytes (36 double precision FP elements).
The binary loop is storing 32 bytes (4 double precision FP elements).


      6.1.2.1.8  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.19 FP operations per loaded or stored byte.







      6.1.3  -  Loop 30 from exec
  ==========================================================================================================

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/178-663-0009/intel/TeaLeaf/build/TeaLeaf/src/omp/cg.cpp:128-131.

It is main loop of related source loop which is unrolled by 4 (including vectorization).

      6.1.3.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

25% of peak computational performance is used (8.00 out of 32.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.3.1.1  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is vectorized, but using only 256 out of 512 bits (AVX/AVX2 instructions on AVX-512 processors).
<<image_4x64_512>>

Details
All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).


Workaround
Read the "512-bits vectorization" report at "Potential" confidence level.


      6.1.3.1.2  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck).

By removing all these bottlenecks, you can lower the cost of an iteration from 1.00 to 0.67 cycles (1.50x speedup).


Workaround
Reduce the number of FP multiply/FMA instructions




      6.1.3.1.3  -  512-bits vectorization
  ----------------------------------------------------------------------------------------------------------

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.


Workaround
Recompile with -mprefer-vector-width=512


      6.1.3.1.4  -  FMA
  ----------------------------------------------------------------------------------------------------------

Detected 4 FMA (fused multiply-add) operations.




      6.1.3.1.5  -  Vector unaligned load/store instructions
  ----------------------------------------------------------------------------------------------------------

Detected 2 optimal vector unaligned load/store instructions.


Details
 - VMOVUPD: 2 occurrences<<list_path_1_vec_align_1>>


Workaround
Use vector aligned instructions:
 1) align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
 2) inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.
<<image_vec_align>>


      6.1.3.1.6  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

1 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).



      6.1.3.1.7  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 8 FP arithmetical operations:
 - 4: addition or subtraction (all inside FMA instructions)
 - 4: multiply (all inside FMA instructions)
The binary loop is loading 64 bytes (8 double precision FP elements).
The binary loop is storing 32 bytes (4 double precision FP elements).


      6.1.3.1.8  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.







      6.1.4  -  Loop 22 from exec
  ==========================================================================================================

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/178-663-0009/intel/TeaLeaf/build/TeaLeaf/src/omp/cg.cpp:83-92.

Warnings:
 - Non-innermost loop: analyzing only self part (ignoring child loops).
 - Ignoring paths for analysis
 - Too many paths. Rerun with max-paths=9
 - RecMII not computed since number of paths is unknown or > max_paths
 - Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 9 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):
 - hoisting them (moving them outside the loop)
 - turning them into conditional moves, MIN or MAX


Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)


      6.1.4.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

Warnings:
The number of fused uops of the instruction [VPCMPNLEUQ	%YMM1,%YMM5,%K1] is unknown
7% of peak computational performance is used (2.26 out of 32.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.4.1.1  -  Code clean check
  ----------------------------------------------------------------------------------------------------------

Detected a slowdown caused by scalar integer instructions (typically used for address computation).
By removing them, you can lower the cost of an iteration from 28.33 to 8.67 cycles (3.27x speedup).

Workaround
 - Try to reorganize arrays of structures to structures of arrays
 - Consider to permute loops (see vectorization gain report)



      6.1.4.1.2  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is partially vectorized.
Only 29% of vector register length is used (average across all SSE/AVX instructions).


Details
53% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):
 - 81% of SSE/AVX loads are used in vector version.
 - 14% of SSE/AVX stores are used in vector version.
 - 71% of SSE/AVX addition or subtraction instructions are used in vector version.
 - 25% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.


Workaround
Read the "512-bits vectorization" report at "Potential" confidence level.


      6.1.4.1.3  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Found no such bottlenecks but see expert reports for more complex bottlenecks.




      6.1.4.1.4  -  512-bits vectorization
  ----------------------------------------------------------------------------------------------------------

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.


Workaround
Recompile with -mprefer-vector-width=512


      6.1.4.1.5  -  Masked instructions
  ----------------------------------------------------------------------------------------------------------

Detected masked instructions.

Details
Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround
If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.


      6.1.4.1.6  -  FMA
  ----------------------------------------------------------------------------------------------------------

Detected 20 FMA (fused multiply-add) operations.
Presence of both ADD/SUB and MUL operations.

Workaround
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible.
Estimated speedup by perfect pairing: 1.01x.
For instance a + b*c is a valid FMA (MUL then ADD).
However (a+b)* c cannot be translated into an FMA (ADD then MUL).




      6.1.4.1.7  -  Complex instructions
  ----------------------------------------------------------------------------------------------------------

Detected COMPLEX INSTRUCTIONS.


Details
These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.
 - OR: 1 occurrences<<list_path_1_complex_1>>
 - SETAE: 2 occurrences<<list_path_1_complex_2>>
 - SETB: 4 occurrences<<list_path_1_complex_3>>



      6.1.4.1.8  -  Vector unaligned load/store instructions
  ----------------------------------------------------------------------------------------------------------

Detected 1 suboptimal vector unaligned load/store instructions.


Details
 - VEXTRACTF128: 1 occurrences<<list_path_1_vec_align_1>>


Workaround
 - Pass to your compiler a micro-architecture specialization option:
  * use march=native
 - Use vector aligned instructions:
  1) align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
  2) inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.
<<image_vec_align>>


      6.1.4.1.9  -  Conversion instructions
  ----------------------------------------------------------------------------------------------------------

Detected expensive conversion instructions.

Details
 - MOVZX: 2 occurrences<<list_path_1_cvt_1>>


Workaround
Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.


      6.1.4.1.10  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

2 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).
1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).
10 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).



      6.1.4.1.11  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 64 FP arithmetical operations:
 - 40: addition or subtraction (20 inside FMA instructions)
 - 24: multiply (20 inside FMA instructions)
The binary loop is loading 574 bytes (71 double precision FP elements).
The binary loop is storing 83 bytes (10 double precision FP elements).


      6.1.4.1.12  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.10 FP operations per loaded or stored byte.







      6.1.5  -  Loop 155 from exec
  ==========================================================================================================

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/178-663-0009/intel/TeaLeaf/build/TeaLeaf/src/omp/pack_halos.cpp:86-88.

It is peel/tail loop of related source loop which is unrolled by 4 (including vectorization).

      6.1.5.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

0% of peak computational performance is used (0.00 out of 64.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.5.1.1  -  Unrolling/vectorization cost
  ----------------------------------------------------------------------------------------------------------

This loop is peel/tail of a unrolled/vectorized loop. If its cost is not negligible compared to the main (unrolled/vectorized) loop, unrolling/vectorization is counterproductive due to low trip count.

Details
The more iterations the main loop is processing, the higher the trip count must be to amortize peel/tail overhead.

Workaround
 - recompile with -fprofile-instr-generate, execute ,merge raw profiles with 'llvm-profdata merge -o default.profdata default.profraw' and recompile with -fprofile-instr-use (profile-guided optimization)
 - hardcode most frequent values of loop bounds by adding specialized paths.:
  *  For instance, replace for (i=0; i<n; i++) foo(i) with:
switch (n) {
  case (4): for (i=0; i<4; i++) foo(i); break;
  case (6): for (i=0; i<6; i++) foo(i); break;
  default : for (i=0; i<n; i++) foo(i); break;
}



      6.1.5.1.2  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is not vectorized.
8 data elements could be processed at once in vector registers.


Details
All SSE/AVX instructions are used in scalar version (process only one data element in vector registers).



      6.1.5.1.3  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Found no such bottlenecks but see expert reports for more complex bottlenecks.



No data for this section



      6.1.5.1.4  -  Slow data structures access
  ----------------------------------------------------------------------------------------------------------

Detected data structures (typically arrays) that cannot be efficiently read/written

Details
 - Irregular (variable stride) or indirect: 1 occurrence(s)
Non-unit stride (uncontiguous) accesses are not efficiently using data caches


Workaround
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.


      6.1.5.1.5  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.


      6.1.5.1.6  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop does not contain any FP arithmetical operations.
The binary loop is loading 8 bytes.
The binary loop is storing 8 bytes.







      6.1.6  -  Loop 159 from exec
  ==========================================================================================================

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/178-663-0009/intel/TeaLeaf/build/TeaLeaf/src/omp/pack_halos.cpp:103-105.

It is peel/tail loop of related source loop which is unrolled by 4 (including vectorization).

      6.1.6.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

0% of peak computational performance is used (0.00 out of 64.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.6.1.1  -  Unrolling/vectorization cost
  ----------------------------------------------------------------------------------------------------------

This loop is peel/tail of a unrolled/vectorized loop. If its cost is not negligible compared to the main (unrolled/vectorized) loop, unrolling/vectorization is counterproductive due to low trip count.

Details
The more iterations the main loop is processing, the higher the trip count must be to amortize peel/tail overhead.

Workaround
 - recompile with -fprofile-instr-generate, execute ,merge raw profiles with 'llvm-profdata merge -o default.profdata default.profraw' and recompile with -fprofile-instr-use (profile-guided optimization)
 - hardcode most frequent values of loop bounds by adding specialized paths.:
  *  For instance, replace for (i=0; i<n; i++) foo(i) with:
switch (n) {
  case (4): for (i=0; i<4; i++) foo(i); break;
  case (6): for (i=0; i<6; i++) foo(i); break;
  default : for (i=0; i<n; i++) foo(i); break;
}



      6.1.6.1.2  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is not vectorized.
8 data elements could be processed at once in vector registers.


Details
All SSE/AVX instructions are used in scalar version (process only one data element in vector registers).



      6.1.6.1.3  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Found no such bottlenecks but see expert reports for more complex bottlenecks.



No data for this section



      6.1.6.1.4  -  Slow data structures access
  ----------------------------------------------------------------------------------------------------------

Detected data structures (typically arrays) that cannot be efficiently read/written

Details
 - Irregular (variable stride) or indirect: 1 occurrence(s)
Non-unit stride (uncontiguous) accesses are not efficiently using data caches


Workaround
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.


      6.1.6.1.5  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.


      6.1.6.1.6  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop does not contain any FP arithmetical operations.
The binary loop is loading 8 bytes.
The binary loop is storing 8 bytes.







      6.1.7  -  Loop 136 from exec
  ==========================================================================================================

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/178-663-0009/intel/TeaLeaf/build/TeaLeaf/src/omp/local_halos.cpp:44-47.

The related source loop is not unrolled or unrolled with no peel/tail loop.

      6.1.7.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

0% of peak computational performance is used (0.00 out of 64.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.7.1.1  -  Code clean check
  ----------------------------------------------------------------------------------------------------------

Detected a slowdown caused by scalar integer instructions (typically used for address computation).
By removing them, you can lower the cost of an iteration from 1.67 to 1.33 cycles (1.25x speedup).

Workaround
 - Try to reorganize arrays of structures to structures of arrays
 - Consider to permute loops (see vectorization gain report)



      6.1.7.1.2  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is vectorized, but using only 256 out of 512 bits (AVX/AVX2 instructions on AVX-512 processors).


Details
All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).


Workaround
Read the "512-bits vectorization" report at "Potential" confidence level.


      6.1.7.1.3  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Found no such bottlenecks but see expert reports for more complex bottlenecks.




      6.1.7.1.4  -  512-bits vectorization
  ----------------------------------------------------------------------------------------------------------

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.


Workaround
Recompile with -mprefer-vector-width=512




      6.1.7.1.5  -  Slow data structures access
  ----------------------------------------------------------------------------------------------------------

Detected data structures (typically arrays) that cannot be efficiently read/written

Details
 - Irregular (variable stride) or indirect: 1 occurrence(s)
Non-unit stride (uncontiguous) accesses are not efficiently using data caches


Workaround
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.


      6.1.7.1.6  -  Vector unaligned load/store instructions
  ----------------------------------------------------------------------------------------------------------

Detected 4 optimal vector unaligned load/store instructions.


Details
 - VMOVUPD: 4 occurrences<<list_path_1_vec_align_1>>


Workaround
Use vector aligned instructions:
 1) align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
 2) inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.
<<image_vec_align>>


      6.1.7.1.7  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.


      6.1.7.1.8  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop does not contain any FP arithmetical operations.
The binary loop is loading 64 bytes.
The binary loop is storing 64 bytes.


      6.1.7.1.9  -  Unroll opportunity
  ----------------------------------------------------------------------------------------------------------

Loop is potentially data access bound.

Workaround
Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: #pragma unroll_and_jam N, unroll_and_jam(N), unroll N or unroll(N)







      6.1.8  -  Loop 361 from exec
  ==========================================================================================================



      6.1.8.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

0% of peak computational performance is used (0.00 out of 64.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.8.1.1  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is vectorized, but using only 256 out of 512 bits (AVX/AVX2 instructions on AVX-512 processors).


Details
All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).


Workaround
Read the "512-bits vectorization" report at "Potential" confidence level.


      6.1.8.1.2  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Performance is limited by writing data to caches/RAM (the store unit is a bottleneck).


Workaround
 - Write less array elements
 - Provide more information to your compiler:
  * hardcode the bounds of the corresponding 'for' loop





      6.1.8.1.3  -  512-bits vectorization
  ----------------------------------------------------------------------------------------------------------

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.





      6.1.8.1.4  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.


      6.1.8.1.5  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop does not contain any FP arithmetical operations.
The binary loop is loading 256 bytes.
The binary loop is storing 256 bytes.







      6.1.9  -  Loop 25 from exec
  ==========================================================================================================

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/178-663-0009/intel/TeaLeaf/build/TeaLeaf/src/omp/cg.cpp:105-115.

Warnings:
 - Non-innermost loop: analyzing only self part (ignoring child loops).
 - Ignoring paths for analysis
 - Too many paths. Rerun with max-paths=8
 - RecMII not computed since number of paths is unknown or > max_paths
 - Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 8 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):
 - hoisting them (moving them outside the loop)
 - turning them into conditional moves, MIN or MAX


Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)


      6.1.9.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

0% of peak computational performance is used (0.23 out of 32.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.9.1.1  -  Code clean check
  ----------------------------------------------------------------------------------------------------------

Detected a slowdown caused by scalar integer instructions (typically used for address computation).
By removing them, you can lower the cost of an iteration from 17.67 to 4.17 cycles (4.24x speedup).

Workaround
 - Try to reorganize arrays of structures to structures of arrays
 - Consider to permute loops (see vectorization gain report)



      6.1.9.1.2  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is not vectorized.
Only 13% of vector register length is used (average across all SSE/AVX instructions).


Details
16% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):
 - 0% of SSE/AVX loads are used in vector version.
 - 0% of SSE/AVX stores are used in vector version.
 - 33% of SSE/AVX addition or subtraction instructions are used in vector version.
 - 17% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.


Workaround
Read the "512-bits vectorization" report at "Potential" confidence level.


      6.1.9.1.3  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Found no such bottlenecks but see expert reports for more complex bottlenecks.




      6.1.9.1.4  -  512-bits vectorization
  ----------------------------------------------------------------------------------------------------------

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.


Workaround
Recompile with -mprefer-vector-width=512




      6.1.9.1.5  -  Complex instructions
  ----------------------------------------------------------------------------------------------------------

Detected COMPLEX INSTRUCTIONS.


Details
These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.
 - SETAE: 2 occurrences<<list_path_1_complex_1>>
 - SETB: 3 occurrences<<list_path_1_complex_2>>



      6.1.9.1.6  -  Vector unaligned load/store instructions
  ----------------------------------------------------------------------------------------------------------

Detected 1 suboptimal vector unaligned load/store instructions.


Details
 - VEXTRACTF128: 1 occurrences<<list_path_1_vec_align_1>>


Workaround
 - Pass to your compiler a micro-architecture specialization option:
  * use march=native
 - Use vector aligned instructions:
  1) align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
  2) inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.
<<image_vec_align>>


      6.1.9.1.7  -  Conversion instructions
  ----------------------------------------------------------------------------------------------------------

Detected expensive conversion instructions.

Details
 - CLTQ: 1 occurrences<<list_path_1_cvt_1>>
 - MOVZX: 1 occurrences<<list_path_1_cvt_2>>


Workaround
Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.


      6.1.9.1.8  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

2 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).
1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).



      6.1.9.1.9  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 4 FP arithmetical operations:
 - 4: addition or subtraction
The binary loop is loading 165 bytes (20 double precision FP elements).
The binary loop is storing 17 bytes (2 double precision FP elements).


      6.1.9.1.10  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.02 FP operations per loaded or stored byte.







      6.1.10  -  Loop 139 from exec
  ==========================================================================================================

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/178-663-0009/intel/TeaLeaf/build/TeaLeaf/src/omp/pack_halos.cpp:15-17.

It is peel/tail loop of related source loop which is unrolled by 4 (including vectorization).

      6.1.10.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

0% of peak computational performance is used (0.00 out of 64.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.10.1.1  -  Unrolling/vectorization cost
  ----------------------------------------------------------------------------------------------------------

This loop is peel/tail of a unrolled/vectorized loop. If its cost is not negligible compared to the main (unrolled/vectorized) loop, unrolling/vectorization is counterproductive due to low trip count.

Details
The more iterations the main loop is processing, the higher the trip count must be to amortize peel/tail overhead.

Workaround
 - recompile with -fprofile-instr-generate, execute ,merge raw profiles with 'llvm-profdata merge -o default.profdata default.profraw' and recompile with -fprofile-instr-use (profile-guided optimization)
 - hardcode most frequent values of loop bounds by adding specialized paths.:
  *  For instance, replace for (i=0; i<n; i++) foo(i) with:
switch (n) {
  case (4): for (i=0; i<4; i++) foo(i); break;
  case (6): for (i=0; i<6; i++) foo(i); break;
  default : for (i=0; i<n; i++) foo(i); break;
}



      6.1.10.1.2  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is not vectorized.
8 data elements could be processed at once in vector registers.


Details
All SSE/AVX instructions are used in scalar version (process only one data element in vector registers).



      6.1.10.1.3  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Found no such bottlenecks but see expert reports for more complex bottlenecks.



No data for this section



      6.1.10.1.4  -  Slow data structures access
  ----------------------------------------------------------------------------------------------------------

Detected data structures (typically arrays) that cannot be efficiently read/written

Details
 - Irregular (variable stride) or indirect: 1 occurrence(s)
Non-unit stride (uncontiguous) accesses are not efficiently using data caches


Workaround
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.


      6.1.10.1.5  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.


      6.1.10.1.6  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop does not contain any FP arithmetical operations.
The binary loop is loading 8 bytes.
The binary loop is storing 8 bytes.





[MAQAO] Info: STOP THE REPORT GENERATION
[MAQAO] Info: 
[MAQAO] Info: If your application produces files, they can be found in directory "/beegfs/hackathon/users/eoseret/qaas_runs_test/178-663-0009/intel/TeaLeaf/run/oneview_runs/defaults/orig/oneview_run_1786630155"
[MAQAO] Info: 
