OV - exec - Function main.extracted.50

	Function: main.extracted.50	Module: exec	Source: stream.c:330-332	Coverage (incl. loops): 94.97% \| (excl. loops): 0.00%

/beegfs/hackathon/users/eoseret/qaas_runs_test/gmz17.benchmarkcenter.megware.com/177-365-4625/stream-scale/build/stream-scale/src/stream.c: 330 - 332

--------------------------------------------------------------------------------

330: #pragma omp parallel for

331: 	for (j=0; j<STREAM_ARRAY_SIZE; j++)

332: 	    b[j] = scalar*c[j];

0x402e30 PUSH	%RBP

0x402e31 MOV	%RSP,%RBP

0x402e34 PUSH	%R14

0x402e36 PUSH	%RBX

0x402e37 SUB	$0x20,%RSP

0x402e3b MOVL	$0,-0x14(%RBP)

0x402e42 MOV	(%RDI),%EBX

0x402e44 MOVQ	$0,-0x28(%RBP)

0x402e4c MOVQ	$0x3344ffff,-0x20(%RBP)

0x402e54 MOVQ	$0x1,-0x30(%RBP)

0x402e5c SUB	$0x8,%RSP

0x402e60 LEA	-0x30(%RBP),%RAX

0x402e64 MOV	$0x4ceb87e20,%RDI

0x402e6e LEA	-0x20(%RBP),%R9

0x402e72 MOV	$0x401050,%R10

0x402e7c LEA	-0x14(%RBP),%RCX

0x402e80 LEA	-0x28(%RBP),%R8

0x402e84 MOV	%EBX,%ESI

0x402e86 MOV	$0x22,%EDX

0x402e8b PUSH	$0x1

0x402e8d PUSH	$0x1

0x402e8f PUSH	%RAX

0x402e90 CALL	%R10

0x402e93 ADD	$0x20,%RSP

0x402e97 MOV	-0x20(%RBP),%RAX

0x402e9b MOV	-0x28(%RBP),%RDI

0x402e9f MOV	%RAX,%R9

0x402ea2 SUB	%RDI,%R9

0x402ea5 JB	402f48

0x402eab INC	%R9

0x402eae MOV	$0x334905060,%RDX

0x402eb8 MOV	$0x4030d0,%R8

0x402ec2 MOV	$0x19a685060,%RSI

0x402ecc MOV	%R9,%RCX

0x402ecf AND	$0x7ffffffc,%RCX

0x402ed6 JE	402f10

0x402ed8 VBROADCASTSD	(%R8),%YMM0

0x402edd LEA	(,%RDI,8),%R10

0x402ee5 XOR	%R11D,%R11D

0x402ee8 NOPL	(%RAX,%RAX,1)

(14) 0x402ef0 LEA	(%R10,%R11,8),%R14

(14) 0x402ef4 ADD	$0x4,%R11

(14) 0x402ef8 VMULPD	(%RDX,%R14,1),%YMM0,%YMM1

(14) 0x402efe VMOVUPD	%YMM1,(%RSI,%R14,1)

(14) 0x402f04 CMP	%RCX,%R11

(14) 0x402f07 JB	402ef0

0x402f09 CMP	%RCX,%R9

0x402f0c JNE	402f12

0x402f0e JMP	402f48

0x402f10 XOR	%ECX,%ECX

0x402f12 VMOVSD	(%R8),%XMM0

0x402f17 SUB	%RCX,%RAX

0x402f1a ADD	%RDI,%RCX

0x402f1d SUB	%RDI,%RAX

0x402f20 SAL	$0x3,%RCX

0x402f24 XOR	%EDI,%EDI

0x402f26 INC	%RAX

0x402f29 NOPL	(%RAX)

(13) 0x402f30 LEA	(%RCX,%RDI,8),%R8

(13) 0x402f34 INC	%RDI

(13) 0x402f37 VMULSD	(%RDX,%R8,1),%XMM0,%XMM1

(13) 0x402f3d VMOVSD	%XMM1,(%RSI,%R8,1)

(13) 0x402f43 CMP	%RDI,%RAX

(13) 0x402f46 JNE	402f30

0x402f48 MOV	$0x4ceb87e40,%RDI

0x402f52 MOV	$0x401030,%RAX

0x402f5c MOV	%EBX,%ESI

0x402f5e ADD	$0x20,%RSP

0x402f62 POP	%RBX

0x402f63 POP	%R14

0x402f65 POP	%RBP

0x402f66 VZEROUPPER

0x402f69 JMP	%RAX

Coverage (%)	Name	Source Location	Module
►100.00+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run icx_8

Source file and lines	stream.c:330-332
Module	exec

The function is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz17.benchmarkcenter.megware.com/177-365-4625/stream-scale/build/stream-scale/src/stream.c:330-332.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 7.50 to 1.25 cycles (6.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 10% of vector register length is used (average across all SSE/AVX instructions).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz17.benchmarkcenter.megware.com/177-365-4625/stream-scale/build/stream-scale/src/stream.c:330

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 36 bytes. The binary function is storing 28 bytes.

General properties

nb instructions	61
nb uops	60
loop length	266
used x86 registers	13
used mmx registers	0
used xmm registers	1
used ymm registers	1
used zmm registers	0
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	7.50 cycles
front end	7.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	5.33	5.33	5.33	5.33	5.33	5.33	2.50	2.50	2.50	2.50	0.00	0.00	0.00	0.00	0.00	0.00
cycles	5.33	5.33	5.33	5.33	5.33	5.33	2.50	2.50	2.50	2.50	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	7.50
Dispatch	5.33
Overall L1	7.50

Vectorization ratios

INT

all	4%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	7%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	4%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

Vector efficiency ratios

INT

all	10%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	10%
load	10%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 7.50 cycles. At this rate:

1% of peak load performance is reached (4.80 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (3.73 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 7.50 to 5.33 cycles (1.41x speedup).

ASM code

In the binary file, the address of the function is: 402e30

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOVL $0,-0x14(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV (%RDI),%EBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
MOVQ $0,-0x28(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOVQ $0x3344ffff,-0x20(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOVQ $0x1,-0x30(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA -0x30(%RBP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV $0x4ceb87e20,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA -0x20(%RBP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV $0x401050,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
LEA -0x14(%RBP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA -0x28(%RBP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %EBX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV $0x22,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL %R10	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	2	N/A
ADD $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV -0x20(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV -0x28(%RBP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RAX,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
SUB %RDI,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
JB 402f48 <main.extracted.50+0x118>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0.33-1	N/A
INC %R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
MOV $0x334905060,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
MOV $0x4030d0,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV $0x19a685060,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
MOV %R9,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
AND $0x7ffffffc,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
JE 402f10 <main.extracted.50+0xe0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0.33-1	N/A
VBROADCASTSD (%R8),%YMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
LEA (,%RDI,8),%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
XOR %R11D,%R11D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
CMP %RCX,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
JNE 402f12 <main.extracted.50+0xe2>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0.33-1	N/A
JMP 402f48 <main.extracted.50+0x118>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0.50	N/A
XOR %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
VMOVSD (%R8),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
SUB %RCX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
ADD %RDI,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
SUB %RDI,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
SAL $0x3,%RCX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.33	scal (12.5%)
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
INC %RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
MOV $0x4ceb87e40,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV $0x401030,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %EBX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
ADD $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
JMP %RAX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run icx_8

Source file and lines	stream.c:330-332
Module	exec

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 7.50 to 1.25 cycles (6.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 10% of vector register length is used (average across all SSE/AVX instructions).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

Workaround

Recompile with -mprefer-vector-width=512

CALL instructions

Detected function call instructions.

Details

unknown: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz17.benchmarkcenter.megware.com/177-365-4625/stream-scale/build/stream-scale/src/stream.c:330

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 36 bytes. The binary function is storing 28 bytes.

General properties

nb instructions	61
nb uops	60
loop length	266
used x86 registers	13
used mmx registers	0
used xmm registers	1
used ymm registers	1
used zmm registers	0
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	7.50 cycles
front end	7.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	5.33	5.33	5.33	5.33	5.33	5.33	2.50	2.50	2.50	2.50	0.00	0.00	0.00	0.00	0.00	0.00
cycles	5.33	5.33	5.33	5.33	5.33	5.33	2.50	2.50	2.50	2.50	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	7.50
Dispatch	5.33
Overall L1	7.50

Vectorization ratios

INT

all	4%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	7%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	4%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

Vector efficiency ratios

INT

all	10%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	10%
load	10%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 7.50 cycles. At this rate:

1% of peak load performance is reached (4.80 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (3.73 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 402e30

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOVL $0,-0x14(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV (%RDI),%EBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
MOVQ $0,-0x28(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOVQ $0x3344ffff,-0x20(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOVQ $0x1,-0x30(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA -0x30(%RBP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV $0x4ceb87e20,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA -0x20(%RBP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV $0x401050,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
LEA -0x14(%RBP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA -0x28(%RBP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %EBX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV $0x22,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL %R10	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	2	N/A
ADD $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV -0x20(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV -0x28(%RBP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RAX,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
SUB %RDI,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
JB 402f48 <main.extracted.50+0x118>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0.33-1	N/A
INC %R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
MOV $0x334905060,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
MOV $0x4030d0,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV $0x19a685060,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
MOV %R9,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
AND $0x7ffffffc,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
JE 402f10 <main.extracted.50+0xe0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0.33-1	N/A
VBROADCASTSD (%R8),%YMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
LEA (,%RDI,8),%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
XOR %R11D,%R11D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
CMP %RCX,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
JNE 402f12 <main.extracted.50+0xe2>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0.33-1	N/A
JMP 402f48 <main.extracted.50+0x118>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0.50	N/A
XOR %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
VMOVSD (%R8),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
SUB %RCX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
ADD %RDI,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
SUB %RDI,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
SAL $0x3,%RCX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.33	scal (12.5%)
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
INC %RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
MOV $0x4ceb87e40,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV $0x401030,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %EBX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
ADD $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
JMP %RAX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A

Name	Coverage (%)	Time (s)
▼main.extracted.50–	94.97	4.15
○Loop 14 - stream.c:331-332 - exec	94.97	4.10
○Loop 13 - stream.c:331-332 - exec	0.00	0.00

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

CALL instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

CALL instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code