OV - exec - Loop 15

	Loop Id: 15	Module: exec	Source: stream.c:476-479	Coverage: 0.37%

0x2042a0 VMOVUPD	-0x60(%R14,%RAX,8),%YMM15    [2]

0x2042a7 VMOVUPD	-0x40(%R14,%RAX,8),%YMM16    [2]

0x2042af VMOVUPD	-0x20(%R14,%RAX,8),%YMM17    [2]

0x2042b7 VMOVUPD	(%R14,%RAX,8),%YMM18    [2]

0x2042be VSUBPD	%YMM1,%YMM15,%YMM15

0x2042c2 VSUBPD	%YMM1,%YMM16,%YMM16

0x2042c8 VSUBPD	%YMM1,%YMM17,%YMM17

0x2042ce VSUBPD	%YMM1,%YMM18,%YMM18

0x2042d4 VXORPD	%YMM23,%YMM15,%YMM19

0x2042da VXORPD	%YMM23,%YMM16,%YMM20

0x2042e0 VXORPD	%YMM23,%YMM17,%YMM21

0x2042e6 VXORPD	%YMM23,%YMM18,%YMM22

0x2042ec VCMPPD	$0x6,%YMM15,%YMM19,%K1

0x2042f3 VCMPPD	$0x6,%YMM16,%YMM20,%K2

0x2042fa VCMPPD	$0x6,%YMM17,%YMM21,%K3

0x204301 VCMPPD	$0x6,%YMM18,%YMM22,%K4

0x204308 VMOVAPD	%YMM19,%YMM15{%K1}

0x20430e VADDPD	%YMM0,%YMM15,%YMM0

0x204312 VMOVUPD	-0x60(%R13,%RAX,8),%YMM15    [1]

0x204319 VMOVAPD	%YMM20,%YMM16{%K2}

0x20431f VADDPD	%YMM2,%YMM16,%YMM2

0x204325 VMOVUPD	-0x40(%R13,%RAX,8),%YMM16    [1]

0x20432d VMOVAPD	%YMM21,%YMM17{%K3}

0x204333 VADDPD	%YMM3,%YMM17,%YMM3

0x204339 VMOVUPD	-0x20(%R13,%RAX,8),%YMM17    [1]

0x204341 VMOVAPD	%YMM22,%YMM18{%K4}

0x204347 VADDPD	%YMM4,%YMM18,%YMM4

0x20434d VMOVUPD	(%R13,%RAX,8),%YMM18    [1]

0x204355 VSUBPD	%YMM5,%YMM15,%YMM15

0x204359 VSUBPD	%YMM5,%YMM16,%YMM16

0x20435f VSUBPD	%YMM5,%YMM17,%YMM17

0x204365 VSUBPD	%YMM5,%YMM18,%YMM18

0x20436b VXORPD	%YMM23,%YMM15,%YMM19

0x204371 VXORPD	%YMM23,%YMM16,%YMM20

0x204377 VXORPD	%YMM23,%YMM17,%YMM21

0x20437d VXORPD	%YMM23,%YMM18,%YMM22

0x204383 VCMPPD	$0x6,%YMM15,%YMM19,%K1

0x20438a VCMPPD	$0x6,%YMM16,%YMM20,%K2

0x204391 VCMPPD	$0x6,%YMM17,%YMM21,%K3

0x204398 VCMPPD	$0x6,%YMM18,%YMM22,%K4

0x20439f VMOVAPD	%YMM19,%YMM15{%K1}

0x2043a5 VADDPD	%YMM11,%YMM15,%YMM11

0x2043aa VMOVUPD	-0x60(%R15,%RAX,8),%YMM15    [3]

0x2043b1 VMOVAPD	%YMM20,%YMM16{%K2}

0x2043b7 VADDPD	%YMM12,%YMM16,%YMM12

0x2043bd VMOVUPD	-0x40(%R15,%RAX,8),%YMM16    [3]

0x2043c5 VMOVAPD	%YMM21,%YMM17{%K3}

0x2043cb VADDPD	%YMM13,%YMM17,%YMM13

0x2043d1 VMOVUPD	-0x20(%R15,%RAX,8),%YMM17    [3]

0x2043d9 VMOVAPD	%YMM22,%YMM18{%K4}

0x2043df VADDPD	%YMM14,%YMM18,%YMM14

0x2043e5 VMOVUPD	(%R15,%RAX,8),%YMM18    [3]

0x2043ec ADD	$0x10,%RAX

0x2043f0 VSUBPD	%YMM6,%YMM15,%YMM15

0x2043f4 VSUBPD	%YMM6,%YMM16,%YMM16

0x2043fa VSUBPD	%YMM6,%YMM17,%YMM17

0x204400 VSUBPD	%YMM6,%YMM18,%YMM18

0x204406 VXORPD	%YMM23,%YMM15,%YMM19

0x20440c VXORPD	%YMM23,%YMM16,%YMM20

0x204412 VXORPD	%YMM23,%YMM17,%YMM21

0x204418 VXORPD	%YMM23,%YMM18,%YMM22

0x20441e VCMPPD	$0x6,%YMM15,%YMM19,%K1

0x204425 VCMPPD	$0x6,%YMM16,%YMM20,%K2

0x20442c VCMPPD	$0x6,%YMM17,%YMM21,%K3

0x204433 VCMPPD	$0x6,%YMM18,%YMM22,%K4

0x20443a VMOVAPD	%YMM19,%YMM15{%K1}

0x204440 VMOVAPD	%YMM20,%YMM16{%K2}

0x204446 VMOVAPD	%YMM21,%YMM17{%K3}

0x20444c VMOVAPD	%YMM22,%YMM18{%K4}

0x204452 VADDPD	%YMM7,%YMM15,%YMM7

0x204456 VADDPD	%YMM8,%YMM16,%YMM8

0x20445c VADDPD	%YMM9,%YMM17,%YMM9

0x204462 VADDPD	%YMM10,%YMM18,%YMM10

0x204468 CMP	$0x3345000c,%RAX

0x20446e JNE	2042a0

/beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-365-2841/stream/build/stream/src/stream.c: 476 - 479

--------------------------------------------------------------------------------

476: 	for (j=0; j<STREAM_ARRAY_SIZE; j++) {

477: 		aSumErr += abs(a[j] - aj);

478: 		bSumErr += abs(b[j] - bj);

479: 		cSumErr += abs(c[j] - cj);

Coverage (%)	Name	Source Location	Module
►100.00+	main	stream.c:390	exec
○	__libc_start_call_main		libc.so.6

Coverage (%)	Name	Source Location	Module
►100.00+	main	stream.c:390	exec
○	__libc_start_call_main		libc.so.6

Coverage (%)	Name	Source Location	Module
►100.00+	main	stream.c:390	exec
○	__libc_start_call_main		libc.so.6

Coverage (%)	Name	Source Location	Module
►100.00+	main	stream.c:390	exec
○	__libc_start_call_main		libc.so.6

Coverage (%)	Name	Source Location	Module
►100.00+	main	stream.c:390	exec
○	__libc_start_call_main		libc.so.6

Coverage (%)	Name	Source Location	Module
►100.00+	main	stream.c:390	exec
○	__libc_start_call_main		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.56
CQA speedup if fully vectorized	2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.09
Bottlenecks	P12, P13,
Function	checkSTREAMresults
Source	stream.c:476-479
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	12.50
CQA cycles if no scalar integer	12.50
CQA cycles if FP arith vectorized	8.00
CQA cycles if fully vectorized	6.25
Front-end cycles	9.25
P0 cycles	0.33
P1 cycles	0.33
P2 cycles	0.33
P3 cycles	0.33
P4 cycles	0.33
P5 cycles	0.33
P6 cycles	3.00
P7 cycles	3.00
P8 cycles	3.00
P9 cycles	3.00
P10 cycles	11.50
P11 cycles	11.50
P12 cycles	12.50
P13 cycles	12.50
P14 cycles	0.00
P15 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	75.00
Nb uops	74.00
Nb loads	12.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	7.68
Nb FLOP add-sub	96.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	30.72
Bytes prefetched	0.00
Bytes loaded	384.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	3.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	100.00
Vector-efficiency ratio all	50.00
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	50.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.56
CQA speedup if fully vectorized	2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.09
Bottlenecks	P12, P13,
Function	checkSTREAMresults
Source	stream.c:476-479
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	12.50
CQA cycles if no scalar integer	12.50
CQA cycles if FP arith vectorized	8.00
CQA cycles if fully vectorized	6.25
Front-end cycles	9.25
P0 cycles	0.33
P1 cycles	0.33
P2 cycles	0.33
P3 cycles	0.33
P4 cycles	0.33
P5 cycles	0.33
P6 cycles	3.00
P7 cycles	3.00
P8 cycles	3.00
P9 cycles	3.00
P10 cycles	11.50
P11 cycles	11.50
P12 cycles	12.50
P13 cycles	12.50
P14 cycles	0.00
P15 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	75.00
Nb uops	74.00
Nb loads	12.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	7.68
Nb FLOP add-sub	96.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	30.72
Bytes prefetched	0.00
Bytes loaded	384.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	3.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	100.00
Vector-efficiency ratio all	50.00
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	50.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	checkSTREAMresults
Source file and lines	stream.c:476-479
Module	exec

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-365-2841/stream/build/stream/src/stream.c:476-479.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is vectorized, but using only 256 out of 512 bits (AVX/AVX2 instructions on AVX-512 processors).

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Performance is limited by execution of FP add operations (the FP add unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 12.50 to 11.50 cycles (1.09x speedup).

Workaround

Reduce the number of FP add instructions

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

Type of elements and instruction set

36 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 96 FP arithmetical operations:

96: addition or subtraction

The binary loop is loading 384 bytes (48 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.25 FP operations per loaded or stored byte.

General properties

nb instructions	75
nb uops	74
loop length	468
used x86 registers	4
used mmx registers	0
used xmm registers	0
used ymm registers	24
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	9.25 cycles
front end	9.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.33	0.33	0.33	0.33	0.33	0.33	3.00	3.00	3.00	3.00	11.50	11.50	12.50	12.50	0.00	0.00
cycles	0.33	0.33	0.33	0.33	0.33	0.33	3.00	3.00	3.00	3.00	11.50	11.50	12.50	12.50	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	9.25
Dispatch	12.50
Data deps.	2.00
Overall L1	12.50

Vectorization ratios

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

Vector efficiency ratios

all	50%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 12.50 cycles. At this rate:

12% of peak load performance is reached (30.72 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 2042a0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	Latency	Recip. throughput	Vectorization
VMOVUPD -0x60(%R14,%RAX,8),%YMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD -0x40(%R14,%RAX,8),%YMM16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD -0x20(%R14,%RAX,8),%YMM17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD (%R14,%RAX,8),%YMM18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (50.0%)
VSUBPD %YMM1,%YMM15,%YMM15	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	vect (50.0%)
VSUBPD %YMM1,%YMM16,%YMM16	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	vect (50.0%)
VSUBPD %YMM1,%YMM17,%YMM17	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	vect (50.0%)
VSUBPD %YMM1,%YMM18,%YMM18	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	vect (50.0%)
VXORPD %YMM23,%YMM15,%YMM19	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.25	vect (50.0%)
VXORPD %YMM23,%YMM16,%YMM20	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.25	vect (50.0%)
VXORPD %YMM23,%YMM17,%YMM21	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.25	vect (50.0%)
VXORPD %YMM23,%YMM18,%YMM22	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.25	vect (50.0%)
VCMPPD $0x6,%YMM15,%YMM19,%K1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	4	0.50	vect (50.0%)
VCMPPD $0x6,%YMM16,%YMM20,%K2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	4	0.50	vect (50.0%)
VCMPPD $0x6,%YMM17,%YMM21,%K3	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	4	0.50	vect (50.0%)
VCMPPD $0x6,%YMM18,%YMM22,%K4	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	4	0.50	vect (50.0%)
VMOVAPD %YMM19,%YMM15{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VADDPD %YMM0,%YMM15,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	vect (50.0%)
VMOVUPD -0x60(%R13,%RAX,8),%YMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (50.0%)
VMOVAPD %YMM20,%YMM16{%K2}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VADDPD %YMM2,%YMM16,%YMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	vect (50.0%)
VMOVUPD -0x40(%R13,%RAX,8),%YMM16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (50.0%)
VMOVAPD %YMM21,%YMM17{%K3}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VADDPD %YMM3,%YMM17,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	vect (50.0%)
VMOVUPD -0x20(%R13,%RAX,8),%YMM17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (50.0%)
VMOVAPD %YMM22,%YMM18{%K4}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VADDPD %YMM4,%YMM18,%YMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	vect (50.0%)
VMOVUPD (%R13,%RAX,8),%YMM18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (50.0%)
VSUBPD %YMM5,%YMM15,%YMM15	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	vect (50.0%)
VSUBPD %YMM5,%YMM16,%YMM16	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	vect (50.0%)
VSUBPD %YMM5,%YMM17,%YMM17	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	vect (50.0%)
VSUBPD %YMM5,%YMM18,%YMM18	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	vect (50.0%)
VXORPD %YMM23,%YMM15,%YMM19	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.25	vect (50.0%)
VXORPD %YMM23,%YMM16,%YMM20	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.25	vect (50.0%)
VXORPD %YMM23,%YMM17,%YMM21	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.25	vect (50.0%)
VXORPD %YMM23,%YMM18,%YMM22	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.25	vect (50.0%)
VCMPPD $0x6,%YMM15,%YMM19,%K1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	4	0.50	vect (50.0%)
VCMPPD $0x6,%YMM16,%YMM20,%K2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	4	0.50	vect (50.0%)
VCMPPD $0x6,%YMM17,%YMM21,%K3	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	4	0.50	vect (50.0%)
VCMPPD $0x6,%YMM18,%YMM22,%K4	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	4	0.50	vect (50.0%)
VMOVAPD %YMM19,%YMM15{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VADDPD %YMM11,%YMM15,%YMM11	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	vect (50.0%)
VMOVUPD -0x60(%R15,%RAX,8),%YMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (50.0%)
VMOVAPD %YMM20,%YMM16{%K2}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VADDPD %YMM12,%YMM16,%YMM12	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	vect (50.0%)
VMOVUPD -0x40(%R15,%RAX,8),%YMM16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (50.0%)
VMOVAPD %YMM21,%YMM17{%K3}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VADDPD %YMM13,%YMM17,%YMM13	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	vect (50.0%)
VMOVUPD -0x20(%R15,%RAX,8),%YMM17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (50.0%)
VMOVAPD %YMM22,%YMM18{%K4}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VADDPD %YMM14,%YMM18,%YMM14	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	vect (50.0%)
VMOVUPD (%R15,%RAX,8),%YMM18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (50.0%)
ADD $0x10,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VSUBPD %YMM6,%YMM15,%YMM15	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	vect (50.0%)
VSUBPD %YMM6,%YMM16,%YMM16	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	vect (50.0%)
VSUBPD %YMM6,%YMM17,%YMM17	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	vect (50.0%)
VSUBPD %YMM6,%YMM18,%YMM18	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	vect (50.0%)
VXORPD %YMM23,%YMM15,%YMM19	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.25	vect (50.0%)
VXORPD %YMM23,%YMM16,%YMM20	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.25	vect (50.0%)
VXORPD %YMM23,%YMM17,%YMM21	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.25	vect (50.0%)
VXORPD %YMM23,%YMM18,%YMM22	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.25	vect (50.0%)
VCMPPD $0x6,%YMM15,%YMM19,%K1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	4	0.50	vect (50.0%)
VCMPPD $0x6,%YMM16,%YMM20,%K2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	4	0.50	vect (50.0%)
VCMPPD $0x6,%YMM17,%YMM21,%K3	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	4	0.50	vect (50.0%)
VCMPPD $0x6,%YMM18,%YMM22,%K4	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	4	0.50	vect (50.0%)
VMOVAPD %YMM19,%YMM15{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VMOVAPD %YMM20,%YMM16{%K2}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VMOVAPD %YMM21,%YMM17{%K3}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VMOVAPD %YMM22,%YMM18{%K4}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VADDPD %YMM7,%YMM15,%YMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	vect (50.0%)
VADDPD %YMM8,%YMM16,%YMM8	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	vect (50.0%)
VADDPD %YMM9,%YMM17,%YMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	vect (50.0%)
VADDPD %YMM10,%YMM18,%YMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	vect (50.0%)
CMP $0x3345000c,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
JNE 2042a0 <checkSTREAMresults+0x120>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.33-1	N/A

Function	checkSTREAMresults
Source file and lines	stream.c:476-479
Module	exec

gain
potential
hint
expert

Vectorization

Your loop is vectorized, but using only 256 out of 512 bits (AVX/AVX2 instructions on AVX-512 processors).

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Workaround

Reduce the number of FP add instructions

512-bits vectorization

Workaround

Recompile with -mprefer-vector-width=512

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

Type of elements and instruction set

36 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 96 FP arithmetical operations:

96: addition or subtraction

The binary loop is loading 384 bytes (48 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.25 FP operations per loaded or stored byte.

General properties

nb instructions	75
nb uops	74
loop length	468
used x86 registers	4
used mmx registers	0
used xmm registers	0
used ymm registers	24
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	9.25 cycles
front end	9.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.33	0.33	0.33	0.33	0.33	0.33	3.00	3.00	3.00	3.00	11.50	11.50	12.50	12.50	0.00	0.00
cycles	0.33	0.33	0.33	0.33	0.33	0.33	3.00	3.00	3.00	3.00	11.50	11.50	12.50	12.50	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	9.25
Dispatch	12.50
Data deps.	2.00
Overall L1	12.50

Vectorization ratios

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

Vector efficiency ratios

all	50%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 12.50 cycles. At this rate:

12% of peak load performance is reached (30.72 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 2042a0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	Latency	Recip. throughput	Vectorization
VMOVUPD -0x60(%R14,%RAX,8),%YMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD -0x40(%R14,%RAX,8),%YMM16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD -0x20(%R14,%RAX,8),%YMM17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD (%R14,%RAX,8),%YMM18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (50.0%)
VSUBPD %YMM1,%YMM15,%YMM15	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	vect (50.0%)
VSUBPD %YMM1,%YMM16,%YMM16	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	vect (50.0%)
VSUBPD %YMM1,%YMM17,%YMM17	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	vect (50.0%)
VSUBPD %YMM1,%YMM18,%YMM18	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	vect (50.0%)
VXORPD %YMM23,%YMM15,%YMM19	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.25	vect (50.0%)
VXORPD %YMM23,%YMM16,%YMM20	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.25	vect (50.0%)
VXORPD %YMM23,%YMM17,%YMM21	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.25	vect (50.0%)
VXORPD %YMM23,%YMM18,%YMM22	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.25	vect (50.0%)
VCMPPD $0x6,%YMM15,%YMM19,%K1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	4	0.50	vect (50.0%)
VCMPPD $0x6,%YMM16,%YMM20,%K2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	4	0.50	vect (50.0%)
VCMPPD $0x6,%YMM17,%YMM21,%K3	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	4	0.50	vect (50.0%)
VCMPPD $0x6,%YMM18,%YMM22,%K4	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	4	0.50	vect (50.0%)
VMOVAPD %YMM19,%YMM15{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VADDPD %YMM0,%YMM15,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	vect (50.0%)
VMOVUPD -0x60(%R13,%RAX,8),%YMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (50.0%)
VMOVAPD %YMM20,%YMM16{%K2}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VADDPD %YMM2,%YMM16,%YMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	vect (50.0%)
VMOVUPD -0x40(%R13,%RAX,8),%YMM16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (50.0%)
VMOVAPD %YMM21,%YMM17{%K3}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VADDPD %YMM3,%YMM17,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	vect (50.0%)
VMOVUPD -0x20(%R13,%RAX,8),%YMM17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (50.0%)
VMOVAPD %YMM22,%YMM18{%K4}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VADDPD %YMM4,%YMM18,%YMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	vect (50.0%)
VMOVUPD (%R13,%RAX,8),%YMM18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (50.0%)
VSUBPD %YMM5,%YMM15,%YMM15	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	vect (50.0%)
VSUBPD %YMM5,%YMM16,%YMM16	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	vect (50.0%)
VSUBPD %YMM5,%YMM17,%YMM17	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	vect (50.0%)
VSUBPD %YMM5,%YMM18,%YMM18	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	vect (50.0%)
VXORPD %YMM23,%YMM15,%YMM19	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.25	vect (50.0%)
VXORPD %YMM23,%YMM16,%YMM20	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.25	vect (50.0%)
VXORPD %YMM23,%YMM17,%YMM21	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.25	vect (50.0%)
VXORPD %YMM23,%YMM18,%YMM22	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.25	vect (50.0%)
VCMPPD $0x6,%YMM15,%YMM19,%K1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	4	0.50	vect (50.0%)
VCMPPD $0x6,%YMM16,%YMM20,%K2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	4	0.50	vect (50.0%)
VCMPPD $0x6,%YMM17,%YMM21,%K3	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	4	0.50	vect (50.0%)
VCMPPD $0x6,%YMM18,%YMM22,%K4	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	4	0.50	vect (50.0%)
VMOVAPD %YMM19,%YMM15{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VADDPD %YMM11,%YMM15,%YMM11	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	vect (50.0%)
VMOVUPD -0x60(%R15,%RAX,8),%YMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (50.0%)
VMOVAPD %YMM20,%YMM16{%K2}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VADDPD %YMM12,%YMM16,%YMM12	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	vect (50.0%)
VMOVUPD -0x40(%R15,%RAX,8),%YMM16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (50.0%)
VMOVAPD %YMM21,%YMM17{%K3}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VADDPD %YMM13,%YMM17,%YMM13	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	vect (50.0%)
VMOVUPD -0x20(%R15,%RAX,8),%YMM17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (50.0%)
VMOVAPD %YMM22,%YMM18{%K4}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VADDPD %YMM14,%YMM18,%YMM14	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	vect (50.0%)
VMOVUPD (%R15,%RAX,8),%YMM18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (50.0%)
ADD $0x10,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VSUBPD %YMM6,%YMM15,%YMM15	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	vect (50.0%)
VSUBPD %YMM6,%YMM16,%YMM16	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	vect (50.0%)
VSUBPD %YMM6,%YMM17,%YMM17	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	vect (50.0%)
VSUBPD %YMM6,%YMM18,%YMM18	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	vect (50.0%)
VXORPD %YMM23,%YMM15,%YMM19	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.25	vect (50.0%)
VXORPD %YMM23,%YMM16,%YMM20	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.25	vect (50.0%)
VXORPD %YMM23,%YMM17,%YMM21	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.25	vect (50.0%)
VXORPD %YMM23,%YMM18,%YMM22	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.25	vect (50.0%)
VCMPPD $0x6,%YMM15,%YMM19,%K1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	4	0.50	vect (50.0%)
VCMPPD $0x6,%YMM16,%YMM20,%K2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	4	0.50	vect (50.0%)
VCMPPD $0x6,%YMM17,%YMM21,%K3	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	4	0.50	vect (50.0%)
VCMPPD $0x6,%YMM18,%YMM22,%K4	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	4	0.50	vect (50.0%)
VMOVAPD %YMM19,%YMM15{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VMOVAPD %YMM20,%YMM16{%K2}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VMOVAPD %YMM21,%YMM17{%K3}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VMOVAPD %YMM22,%YMM18{%K4}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VADDPD %YMM7,%YMM15,%YMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	vect (50.0%)
VADDPD %YMM8,%YMM16,%YMM8	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	vect (50.0%)
VADDPD %YMM9,%YMM17,%YMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	vect (50.0%)
VADDPD %YMM10,%YMM18,%YMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	vect (50.0%)
CMP $0x3345000c,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
JNE 2042a0 <checkSTREAMresults+0x120>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.33-1	N/A

▶Scalability Runs Description

Run 1x8	Number processes: 1Number nodes: 1Number processes per node: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to none --report-bindings Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-365-2841/stream/run/oneview_runs/multicore/aocc_8/oneview_run_1773655287OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threadsOMP_NUM_THREADS: 8
Run 1x64	Number processes: 1Number nodes: 1Number processes per node: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to none --report-bindings Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-365-2841/stream/run/oneview_runs/multicore/aocc_8/oneview_run_1773655287OMP_NUM_THREADS: 64OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x96	Number processes: 1Number nodes: 1Number processes per node: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to none --report-bindings Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-365-2841/stream/run/oneview_runs/multicore/aocc_8/oneview_run_1773655287OMP_NUM_THREADS: 96OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x128	Number processes: 1Number nodes: 1Number processes per node: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to none --report-bindings Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-365-2841/stream/run/oneview_runs/multicore/aocc_8/oneview_run_1773655287OMP_NUM_THREADS: 128OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x160	Number processes: 1Number nodes: 1Number processes per node: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to none --report-bindings Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-365-2841/stream/run/oneview_runs/multicore/aocc_8/oneview_run_1773655287OMP_NUM_THREADS: 160OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x192	Number processes: 1Number nodes: 1Number processes per node: 1Run Command: <executable>MPI Command: mpirun -n <number_processes> --bind-to none --report-bindings Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-365-2841/stream/run/oneview_runs/multicore/aocc_8/oneview_run_1773655287OMP_NUM_THREADS: 192OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads

(1x8) Efficiency	(1x8) Potential Speed-Up (%)	(1x64) Efficiency	(1x64) Potential Speed-Up (%)	(1x96) Efficiency	(1x96) Potential Speed-Up (%)	(1x128) Efficiency	(1x128) Potential Speed-Up (%)	(1x160) Efficiency	(1x160) Potential Speed-Up (%)	(1x192) Efficiency	(1x192) Potential Speed-Up (%)
1	0	0.9	0.01	0.9	0.01	0.92	0	0.93	0	0.93	0

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
1x8	1	1	1	1	0.56000000238419	0.36857867240906
1x64	1	0.9	7.19	8	0.60500001907349	0.099344007670879
1x96	1	0.9	10.75	12	0.60500007867813	0.067984014749527
1x128	1	0.92	14.73	16	0.58999997377396	0.047531194984913
1x160	1	0.93	18.56	20	0.58500003814697	0.037349764257669
1x192	1	0.93	22.22	24	0.58500003814697	0.032405212521553

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

512-bits vectorization

Workaround

Masked instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

512-bits vectorization

Workaround

Masked instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

▶Scalability Runs Description

▼Columns Filter

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency