OV - exec - Function main.omp

	Function: main.omp_outlined.33	Module: exec	Source: stream.c:354-356	Coverage (incl. loops): 29.51% \| (excl. loops): 0.00%

/beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-365-2841/stream/build/stream/src/stream.c: 354 - 356

--------------------------------------------------------------------------------

354: #pragma omp parallel for

355: 	for (j=0; j<STREAM_ARRAY_SIZE; j++)

356: 	    a[j] = b[j]+scalar*c[j];

0x203cd0 PUSH	%RBP

0x203cd1 MOV	%RSP,%RBP

0x203cd4 PUSH	%R15

0x203cd6 PUSH	%R14

0x203cd8 PUSH	%R12

0x203cda PUSH	%RBX

0x203cdb SUB	$0x20,%RSP

0x203cdf MOV	(%RDI),%EBX

0x203ce1 LEA	-0x7(%RIP),%RAX

0x203ce8 MOV	$0x3367,%R15

0x203cf2 MOV	%RDX,%R14

0x203cf5 MOVQ	$0,-0x38(%RBP)

0x203cfd MOVQ	$0x3344ffff,-0x28(%RBP)

0x203d05 MOVQ	$0x1,-0x40(%RBP)

0x203d0d MOVL	$0,-0x2c(%RBP)

0x203d14 ADD	%RAX,%R15

0x203d17 SUB	$0x8,%RSP

0x203d1b MOV	$-0x1218,%RDI

0x203d25 LEA	-0x40(%RBP),%RAX

0x203d29 MOV	$-0x1028,%R10

0x203d33 LEA	-0x2c(%RBP),%RCX

0x203d37 LEA	-0x38(%RBP),%R8

0x203d3b LEA	-0x28(%RBP),%R9

0x203d3f MOV	%EBX,%ESI

0x203d41 MOV	$0x22,%EDX

0x203d46 ADD	%R15,%RDI

0x203d49 PUSH	$0x1

0x203d4b PUSH	$0x1

0x203d4d PUSH	%RAX

0x203d4e CALLQ	(%R15,%R10,1)

0x203d52 ADD	$0x20,%RSP

0x203d56 MOV	-0x28(%RBP),%RCX

0x203d5a MOV	-0x38(%RBP),%R12

0x203d5e MOV	$0x3344ffff,%EAX

0x203d63 CMP	$0x3344ffff,%RCX

0x203d6a CMOVL	%RCX,%RAX

0x203d6e MOV	%RAX,-0x28(%RBP)

0x203d72 CMP	%RAX,%R12

0x203d75 JG	203e7b

0x203d7b VMOVSD	(%R14),%XMM0

0x203d80 MOV	%RAX,%R8

0x203d83 SUB	%R12,%R8

0x203d86 MOV	$0x19a280028,%RCX

0x203d90 MOV	$0x334500028,%RDX

0x203d9a MOV	$0x28,%RSI

0x203da4 INC	%R8

0x203da7 CMP	$0x10,%R8

0x203dab JAE	203db5

0x203dad MOV	%R12,%RDI

0x203db0 JMP	203e4f

0x203db5 LEA	(%R15,%RCX,1),%R10

0x203db9 LEA	(%R15,%RDX,1),%R11

0x203dbd LEA	(%R15,%RSI,1),%R14

0x203dc1 MOV	%R8,%R9

0x203dc4 AND	$-0x10,%R9

0x203dc8 VBROADCASTSD	%XMM0,%YMM1

0x203dcd LEA	0x60(%R10,%R12,8),%R10

0x203dd2 LEA	0x60(%R11,%R12,8),%R11

0x203dd7 LEA	0x60(%R14,%R12,8),%R14

0x203ddc LEA	(%R12,%R9,1),%RDI

0x203de0 XOR	%R12D,%R12D

0x203de3 NOPW	%CS:(%RAX,%RAX,1)

(10) 0x203df0 VMOVUPD	-0x60(%R11,%R12,8),%YMM2

(10) 0x203df7 VMOVUPD	-0x40(%R11,%R12,8),%YMM3

(10) 0x203dfe VMOVUPD	-0x20(%R11,%R12,8),%YMM4

(10) 0x203e05 VMOVUPD	(%R11,%R12,8),%YMM5

(10) 0x203e0b VFMADD213PD	-0x60(%R10,%R12,8),%YMM1,%YMM2

(10) 0x203e12 VFMADD213PD	-0x40(%R10,%R12,8),%YMM1,%YMM3

(10) 0x203e19 VFMADD213PD	-0x20(%R10,%R12,8),%YMM1,%YMM4

(10) 0x203e20 VFMADD213PD	(%R10,%R12,8),%YMM1,%YMM5

(10) 0x203e26 VMOVUPD	%YMM2,-0x60(%R14,%R12,8)

(10) 0x203e2d VMOVUPD	%YMM3,-0x40(%R14,%R12,8)

(10) 0x203e34 VMOVUPD	%YMM4,-0x20(%R14,%R12,8)

(10) 0x203e3b VMOVUPD	%YMM5,(%R14,%R12,8)

(10) 0x203e41 ADD	$0x10,%R12

(10) 0x203e45 CMP	%R12,%R9

(10) 0x203e48 JNE	203df0

0x203e4a CMP	%R9,%R8

0x203e4d JE	203e7b

0x203e4f DEC	%RDI

0x203e52 ADD	%R15,%RCX

0x203e55 ADD	%R15,%RDX

0x203e58 ADD	%R15,%RSI

0x203e5b NOPL	(%RAX,%RAX,1)

(11) 0x203e60 VMOVSD	0x8(%RDX,%RDI,8),%XMM1

(11) 0x203e66 VFMADD213SD	0x8(%RCX,%RDI,8),%XMM0,%XMM1

(11) 0x203e6d VMOVSD	%XMM1,0x8(%RSI,%RDI,8)

(11) 0x203e73 INC	%RDI

(11) 0x203e76 CMP	%RAX,%RDI

(11) 0x203e79 JL	203e60

0x203e7b MOV	$-0x1200,%RDI

0x203e85 MOV	$-0x1018,%RAX

0x203e8f MOV	%EBX,%ESI

0x203e91 ADD	%R15,%RDI

0x203e94 VZEROUPPER

0x203e97 CALLQ	(%R15,%RAX,1)

0x203e9b ADD	$0x20,%RSP

0x203e9f POP	%RBX

0x203ea0 POP	%R12

0x203ea2 POP	%R14

0x203ea4 POP	%R15

0x203ea6 POP	%RBP

0x203ea7 RET

0x203ea8 NOPL	(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
►99.82+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run aocc_8

Source file and lines	stream.c:354-356
Module	exec

The function is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-365-2841/stream/build/stream/src/stream.c:354-356.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 11.25 to 1.25 cycles (9.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 11% of vector register length is used (average across all SSE/AVX instructions).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 2 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-365-2841/stream/build/stream/src/stream.c:354
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-365-2841/stream/build/stream/src/stream.c:354

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

CMOVL: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-365-2841/stream/build/stream/src/stream.c:355
LEA: 3 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-365-2841/stream/build/stream/src/stream.c:355
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-365-2841/stream/build/stream/src/stream.c:355
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-365-2841/stream/build/stream/src/stream.c:355

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 44 bytes. The binary function is storing 36 bytes.

General properties

nb instructions	83
nb uops	90
loop length	363
used x86 registers	15
used mmx registers	0
used xmm registers	1
used ymm registers	1
used zmm registers	0
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	11.25 cycles
front end	11.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	8.17	8.17	8.17	8.17	8.17	8.17	4.00	4.00	4.00	4.00	0.00	0.50	0.50	0.00	0.00	0.00
cycles	8.17	8.17	8.17	8.17	8.17	8.17	4.00	4.00	4.00	4.00	0.00	0.50	0.50	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	11.25
Dispatch	8.17
Overall L1	11.25

Vectorization ratios

INT

all	7%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	16%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	6%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	14%

Vector efficiency ratios

INT

all	11%
load	6%
store	7%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	14%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	11%
load	9%
store	7%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	14%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 11.25 cycles. At this rate:

1% of peak load performance is reached (3.91 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (3.20 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 11.25 to 8.17 cycles (1.38x speedup).

ASM code

In the binary file, the address of the function is: 203cd0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P11	P12	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
MOV (%RDI),%EBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	scal (6.3%)
LEA -0x7(%RIP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
MOV $0x3367,%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
MOV %RDX,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOVQ $0,-0x38(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
MOVQ $0x3344ffff,-0x28(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
MOVQ $0x1,-0x40(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
MOVL $0,-0x2c(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
ADD %RAX,%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
MOV $-0x1218,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
LEA -0x40(%RBP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
MOV $-0x1028,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
LEA -0x2c(%RBP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
LEA -0x38(%RBP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
LEA -0x28(%RBP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
MOV %EBX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x22,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
ADD %R15,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALLQ (%R15,%R10,1)	4	0	0	0	0.33	0.33	0.33	0.50	0.50	0.50	0.50	0	0	0	2.20	N/A
ADD $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
MOV -0x28(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV -0x38(%RBP),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV $0x3344ffff,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
CMP $0x3344ffff,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMOVL %RCX,%RAX	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33	N/A
MOV %RAX,-0x28(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
CMP %RAX,%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
JG 203e7b <main.omp_outlined.33+0x1ab>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0.33-1	N/A
VMOVSD (%R14),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
MOV %RAX,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
SUB %R12,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV $0x19a280028,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
MOV $0x334500028,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
MOV $0x28,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
INC %R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMP $0x10,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
JAE 203db5 <main.omp_outlined.33+0xe5>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0.33-1	N/A
MOV %R12,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 203e4f <main.omp_outlined.33+0x17f>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50	N/A
LEA (%R15,%RCX,1),%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
LEA (%R15,%RDX,1),%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
LEA (%R15,%RSI,1),%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
MOV %R8,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x10,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
VBROADCASTSD %XMM0,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
LEA 0x60(%R10,%R12,8),%R10	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	0	0	2	0.50	N/A
LEA 0x60(%R11,%R12,8),%R11	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	0	0	2	0.50	N/A
LEA 0x60(%R14,%R12,8),%R14	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	0	0	2	0.50	N/A
LEA (%R12,%R9,1),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
XOR %R12D,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
CMP %R9,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 203e7b <main.omp_outlined.33+0x1ab>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0.33-1	N/A
DEC %RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
ADD %R15,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
ADD %R15,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
ADD %R15,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
MOV $-0x1200,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
MOV $-0x1018,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
MOV %EBX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD %R15,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALLQ (%R15,%RAX,1)	4	0	0	0	0.33	0.33	0.33	0.50	0.50	0.50	0.50	0	0	0	2.20	N/A
ADD $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run aocc_8

Source file and lines	stream.c:354-356
Module	exec

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 11.25 to 1.25 cycles (9.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 11% of vector register length is used (average across all SSE/AVX instructions).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

Workaround

Recompile with -mprefer-vector-width=512

CALL instructions

Detected function call instructions.

Details

unknown: 2 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-365-2841/stream/build/stream/src/stream.c:354
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-365-2841/stream/build/stream/src/stream.c:354

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

CMOVL: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-365-2841/stream/build/stream/src/stream.c:355
LEA: 3 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-365-2841/stream/build/stream/src/stream.c:355
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-365-2841/stream/build/stream/src/stream.c:355
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gmz12.benchmarkcenter.megware.com/177-365-2841/stream/build/stream/src/stream.c:355

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 44 bytes. The binary function is storing 36 bytes.

General properties

nb instructions	83
nb uops	90
loop length	363
used x86 registers	15
used mmx registers	0
used xmm registers	1
used ymm registers	1
used zmm registers	0
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	11.25 cycles
front end	11.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	8.17	8.17	8.17	8.17	8.17	8.17	4.00	4.00	4.00	4.00	0.00	0.50	0.50	0.00	0.00	0.00
cycles	8.17	8.17	8.17	8.17	8.17	8.17	4.00	4.00	4.00	4.00	0.00	0.50	0.50	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	11.25
Dispatch	8.17
Overall L1	11.25

Vectorization ratios

INT

all	7%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	16%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	6%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	14%

Vector efficiency ratios

INT

all	11%
load	6%
store	7%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	14%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	11%
load	9%
store	7%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	14%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 11.25 cycles. At this rate:

1% of peak load performance is reached (3.91 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (3.20 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 203cd0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P11	P12	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
MOV (%RDI),%EBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	scal (6.3%)
LEA -0x7(%RIP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
MOV $0x3367,%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
MOV %RDX,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOVQ $0,-0x38(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
MOVQ $0x3344ffff,-0x28(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
MOVQ $0x1,-0x40(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
MOVL $0,-0x2c(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
ADD %RAX,%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
MOV $-0x1218,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
LEA -0x40(%RBP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
MOV $-0x1028,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
LEA -0x2c(%RBP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
LEA -0x38(%RBP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
LEA -0x28(%RBP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
MOV %EBX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x22,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
ADD %R15,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALLQ (%R15,%R10,1)	4	0	0	0	0.33	0.33	0.33	0.50	0.50	0.50	0.50	0	0	0	2.20	N/A
ADD $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
MOV -0x28(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV -0x38(%RBP),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV $0x3344ffff,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
CMP $0x3344ffff,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMOVL %RCX,%RAX	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33	N/A
MOV %RAX,-0x28(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
CMP %RAX,%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
JG 203e7b <main.omp_outlined.33+0x1ab>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0.33-1	N/A
VMOVSD (%R14),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
MOV %RAX,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
SUB %R12,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV $0x19a280028,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
MOV $0x334500028,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
MOV $0x28,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
INC %R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMP $0x10,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
JAE 203db5 <main.omp_outlined.33+0xe5>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0.33-1	N/A
MOV %R12,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 203e4f <main.omp_outlined.33+0x17f>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50	N/A
LEA (%R15,%RCX,1),%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
LEA (%R15,%RDX,1),%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
LEA (%R15,%RSI,1),%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
MOV %R8,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x10,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
VBROADCASTSD %XMM0,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
LEA 0x60(%R10,%R12,8),%R10	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	0	0	2	0.50	N/A
LEA 0x60(%R11,%R12,8),%R11	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	0	0	2	0.50	N/A
LEA 0x60(%R14,%R12,8),%R14	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	0	0	2	0.50	N/A
LEA (%R12,%R9,1),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
XOR %R12D,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
CMP %R9,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 203e7b <main.omp_outlined.33+0x1ab>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0.33-1	N/A
DEC %RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
ADD %R15,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
ADD %R15,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
ADD %R15,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
MOV $-0x1200,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
MOV $-0x1018,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
MOV %EBX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD %R15,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALLQ (%R15,%RAX,1)	4	0	0	0	0.33	0.33	0.33	0.50	0.50	0.50	0.50	0	0	0	2.20	N/A
ADD $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A

Name	Coverage (%)	Time (s)
▼main.omp_outlined.33–	29.51	5.51
○Loop 10 - stream.c:356-356 - exec	29.51	5.41
○Loop 11 - stream.c:355-356 - exec	0.00	0.00

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code