OV - exec - Function main.extracted.50

	Function: main.extracted.50	Module: exec	Source: stream.c:354-356	Coverage (incl. loops): 94.77% \| (excl. loops): 0.00%

/beegfs/hackathon/users/eoseret/qaas_runs_test/gpu04sas.benchmarkcenter.megware.com/177-374-0012/stream-triad/build/stream-triad/src/stream.c: 354 - 356

--------------------------------------------------------------------------------

354: #pragma omp parallel for

355: 	for (j=0; j<STREAM_ARRAY_SIZE; j++)

356: 	    a[j] = b[j]+scalar*c[j];

0x403100 PUSH	%RBP

0x403101 MOV	%RSP,%RBP

0x403104 PUSH	%RBX

0x403105 SUB	$0x28,%RSP

0x403109 MOVL	$0,-0xc(%RBP)

0x403110 MOV	(%RDI),%EBX

0x403112 MOVQ	$0,-0x20(%RBP)

0x40311a MOVQ	$0x3344ffff,-0x18(%RBP)

0x403122 MOVQ	$0x1,-0x28(%RBP)

0x40312a SUB	$0x8,%RSP

0x40312e LEA	-0x28(%RBP),%RAX

0x403132 LEA	-0x20(%RBP),%R8

0x403136 MOV	$0x4ceb88e20,%RDI

0x403140 MOV	$0x401050,%R10

0x40314a LEA	-0xc(%RBP),%RCX

0x40314e LEA	-0x18(%RBP),%R9

0x403152 MOV	%EBX,%ESI

0x403154 MOV	$0x22,%EDX

0x403159 PUSH	$0x1

0x40315b PUSH	$0x1

0x40315d PUSH	%RAX

0x40315e CALL	%R10

0x403161 ADD	$0x20,%RSP

0x403165 MOV	-0x20(%RBP),%RAX

0x403169 MOV	-0x18(%RBP),%R8

0x40316d CMP	%R8,%RAX

0x403170 JA	4032b1

0x403176 MOV	%R8,%R9

0x403179 SUB	%RAX,%R9

0x40317c MOV	$0x4040d0,%RCX

0x403186 MOV	$0x334906060,%RDI

0x403190 MOV	$0x19a686060,%RDX

0x40319a MOV	$0x406060,%RSI

0x4031a4 INC	%R9

0x4031a7 CMP	$0x4,%R9

0x4031ab JB	40321a

0x4031ad VMOVSD	(%RCX),%XMM0

0x4031b1 LEA	0x18(,%RAX,8),%R11

0x4031b9 MOV	%R9,%R10

0x4031bc SHR	$0x2,%R10

(13) 0x4031c0 VMOVSD	-0x18(%R11,%RDI,1),%XMM1

(13) 0x4031c7 VMOVSD	-0x10(%R11,%RDI,1),%XMM2

(13) 0x4031ce VMOVSD	-0x8(%R11,%RDI,1),%XMM3

(13) 0x4031d5 VFMADD213SD	-0x18(%R11,%RDX,1),%XMM0,%XMM1

(13) 0x4031dc VFMADD213SD	-0x10(%R11,%RDX,1),%XMM0,%XMM2

(13) 0x4031e3 VFMADD213SD	-0x8(%R11,%RDX,1),%XMM0,%XMM3

(13) 0x4031ea VMOVSD	%XMM1,-0x18(%R11,%RSI,1)

(13) 0x4031f1 VMOVSD	%XMM2,-0x10(%R11,%RSI,1)

(13) 0x4031f8 VMOVSD	(%R11,%RDI,1),%XMM2

(13) 0x4031fe VMOVSD	%XMM3,-0x8(%R11,%RSI,1)

(13) 0x403205 VFMADD213SD	(%R11,%RDX,1),%XMM0,%XMM2

(13) 0x40320b VMOVSD	%XMM2,(%R11,%RSI,1)

(13) 0x403211 ADD	$0x20,%R11

(13) 0x403215 DEC	%R10

(13) 0x403218 JNE	4031c0

0x40321a AND	$0x7ffffffc,%R9D

0x403221 ADD	%R9,%RAX

0x403224 SUB	%RAX,%R8

0x403227 JE	40329d

0x403229 CMP	$0x1,%R8

0x40322d JE	403269

0x40322f CMP	$0x2,%R8

0x403233 JNE	4032b1

0x403235 MOV	$0x334906070,%R8

0x40323f VMOVSD	(%RCX),%XMM1

0x403243 MOV	$0x19a686070,%R9

0x40324d VMOVSD	(%R8,%RAX,8),%XMM0

0x403253 MOV	$0x406070,%R8

0x40325d VFMADD213SD	(%R9,%RAX,8),%XMM0,%XMM1

0x403263 VMOVSD	%XMM1,(%R8,%RAX,8)

0x403269 MOV	$0x334906068,%R8

0x403273 VMOVSD	(%RCX),%XMM1

0x403277 MOV	$0x19a686068,%R9

0x403281 VMOVSD	(%R8,%RAX,8),%XMM0

0x403287 MOV	$0x406068,%R8

0x403291 VFMADD213SD	(%R9,%RAX,8),%XMM0,%XMM1

0x403297 VMOVSD	%XMM1,(%R8,%RAX,8)

0x40329d VMOVSD	(%RDI,%RAX,8),%XMM0

0x4032a2 VMOVSD	(%RCX),%XMM1

0x4032a6 VFMADD213SD	(%RDX,%RAX,8),%XMM0,%XMM1

0x4032ac VMOVSD	%XMM1,(%RSI,%RAX,8)

0x4032b1 MOV	$0x4ceb88e40,%RDI

0x4032bb MOV	$0x401030,%RAX

0x4032c5 MOV	%EBX,%ESI

0x4032c7 ADD	$0x28,%RSP

0x4032cb POP	%RBX

0x4032cc POP	%RBP

0x4032cd JMP	%RAX

Coverage (%)	Name	Source Location	Module
►100.00+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run icx_5

Source file and lines	stream.c:354-356
Module	exec

The function is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/gpu04sas.benchmarkcenter.megware.com/177-374-0012/stream-triad/build/stream-triad/src/stream.c:354-356.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.33 to 4.33 cycles (2.85x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 11% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 12.33 to 1.27 cycles (9.70x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Detected 3 FMA (fused multiply-add) operations.

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gpu04sas.benchmarkcenter.megware.com/177-374-0012/stream-triad/build/stream-triad/src/stream.c:354

Type of elements and instruction set

3 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 6 FP arithmetical operations:

3: addition or subtraction (all inside FMA instructions)
3: multiply (all inside FMA instructions)

The binary function is loading 100 bytes (12 double precision FP elements). The binary function is storing 52 bytes (6 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.04 FP operations per loaded or stored byte.

General properties

nb instructions	73
nb uops	74
loop length	373
used x86 registers	12
used mmx registers	0
used xmm registers	2
used ymm registers	0
used zmm registers	0
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	12.33 cycles
front end	12.33 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	9.50	9.50	9.25	9.25	3.50	7.00	7.00	7.00	1.50	1.50	0.00	0.00	1.50	1.50
cycles	9.50	9.50	9.25	9.25	3.50	7.00	7.00	7.00	1.50	1.50	0.00	0.00	1.50	1.50

Execution ports to units layout:

ALU0/BRU0: ALU, BRU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1: BRU
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	12.33
Dispatch	9.50
Overall L1	12.33

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	9%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	11%
load	11%
store	8%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.33 cycles. At this rate:

8% of peak load performance is reached (8.11 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (4.22 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 12.33 to 9.50 cycles (1.30x speedup).

ASM code

In the binary file, the address of the function is: 403100

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP4	FP5	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x28,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVL $0,-0xc(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	4	0.50	scal (6.3%)
MOV (%RDI),%EBX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33	scal (6.3%)
MOVQ $0,-0x20(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	4	0.50	scal (6.3%)
MOVQ $0x3344ffff,-0x18(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	4	0.50	scal (6.3%)
MOVQ $0x1,-0x28(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	4	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x28(%RBP),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x20(%RBP),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV $0x4ceb88e20,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV $0x401050,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
LEA -0xc(%RBP),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x18(%RBP),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %EBX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x22,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL %R10	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	2	N/A
ADD $0x20,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV -0x20(%RBP),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33	N/A
MOV -0x18(%RBP),%R8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33	N/A
CMP %R8,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JA 4032b1 <main.extracted.50+0x1b1>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %R8,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %RAX,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV $0x4040d0,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV $0x334906060,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV $0x19a686060,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV $0x406060,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
INC %R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP $0x4,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JB 40321a <main.extracted.50+0x11a>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVSD (%RCX),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	scal (12.5%)
LEA 0x18(,%RAX,8),%R11	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %R9,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
SHR $0x2,%R10	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	scal (12.5%)
AND $0x7ffffffc,%R9D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD %R9,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB %RAX,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
JE 40329d <main.extracted.50+0x19d>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x1,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 403269 <main.extracted.50+0x169>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x2,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JNE 4032b1 <main.extracted.50+0x1b1>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV $0x334906070,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
VMOVSD (%RCX),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	scal (12.5%)
MOV $0x19a686070,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
VMOVSD (%R8,%RAX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	scal (12.5%)
MOV $0x406070,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
VFMADD213SD (%R9,%RAX,8),%XMM0,%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM1,(%R8,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1	scal (12.5%)
MOV $0x334906068,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
VMOVSD (%RCX),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	scal (12.5%)
MOV $0x19a686068,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
VMOVSD (%R8,%RAX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	scal (12.5%)
MOV $0x406068,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
VFMADD213SD (%R9,%RAX,8),%XMM0,%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM1,(%R8,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1	scal (12.5%)
VMOVSD (%RDI,%RAX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD (%RCX),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	scal (12.5%)
VFMADD213SD (%RDX,%RAX,8),%XMM0,%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM1,(%RSI,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1	scal (12.5%)
MOV $0x4ceb88e40,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV $0x401030,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV %EBX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD $0x28,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
JMP %RAX	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	1	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run icx_5

Source file and lines	stream.c:354-356
Module	exec

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.33 to 4.33 cycles (2.85x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Detected 3 FMA (fused multiply-add) operations.

CALL instructions

Detected function call instructions.

Details

unknown: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gpu04sas.benchmarkcenter.megware.com/177-374-0012/stream-triad/build/stream-triad/src/stream.c:354

Type of elements and instruction set

3 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 6 FP arithmetical operations:

3: addition or subtraction (all inside FMA instructions)
3: multiply (all inside FMA instructions)

The binary function is loading 100 bytes (12 double precision FP elements). The binary function is storing 52 bytes (6 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.04 FP operations per loaded or stored byte.

General properties

nb instructions	73
nb uops	74
loop length	373
used x86 registers	12
used mmx registers	0
used xmm registers	2
used ymm registers	0
used zmm registers	0
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	12.33 cycles
front end	12.33 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	9.50	9.50	9.25	9.25	3.50	7.00	7.00	7.00	1.50	1.50	0.00	0.00	1.50	1.50
cycles	9.50	9.50	9.25	9.25	3.50	7.00	7.00	7.00	1.50	1.50	0.00	0.00	1.50	1.50

Execution ports to units layout:

ALU0/BRU0: ALU, BRU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1: BRU
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	12.33
Dispatch	9.50
Overall L1	12.33

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	9%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	11%
load	11%
store	8%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.33 cycles. At this rate:

8% of peak load performance is reached (8.11 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (4.22 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 403100

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP4	FP5	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x28,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVL $0,-0xc(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	4	0.50	scal (6.3%)
MOV (%RDI),%EBX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33	scal (6.3%)
MOVQ $0,-0x20(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	4	0.50	scal (6.3%)
MOVQ $0x3344ffff,-0x18(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	4	0.50	scal (6.3%)
MOVQ $0x1,-0x28(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	4	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x28(%RBP),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x20(%RBP),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV $0x4ceb88e20,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV $0x401050,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
LEA -0xc(%RBP),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x18(%RBP),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %EBX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x22,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL %R10	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	2	N/A
ADD $0x20,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV -0x20(%RBP),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33	N/A
MOV -0x18(%RBP),%R8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33	N/A
CMP %R8,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JA 4032b1 <main.extracted.50+0x1b1>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %R8,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %RAX,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV $0x4040d0,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV $0x334906060,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV $0x19a686060,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV $0x406060,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
INC %R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP $0x4,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JB 40321a <main.extracted.50+0x11a>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVSD (%RCX),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	scal (12.5%)
LEA 0x18(,%RAX,8),%R11	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %R9,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
SHR $0x2,%R10	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	scal (12.5%)
AND $0x7ffffffc,%R9D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD %R9,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB %RAX,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
JE 40329d <main.extracted.50+0x19d>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x1,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 403269 <main.extracted.50+0x169>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x2,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JNE 4032b1 <main.extracted.50+0x1b1>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV $0x334906070,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
VMOVSD (%RCX),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	scal (12.5%)
MOV $0x19a686070,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
VMOVSD (%R8,%RAX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	scal (12.5%)
MOV $0x406070,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
VFMADD213SD (%R9,%RAX,8),%XMM0,%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM1,(%R8,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1	scal (12.5%)
MOV $0x334906068,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
VMOVSD (%RCX),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	scal (12.5%)
MOV $0x19a686068,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
VMOVSD (%R8,%RAX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	scal (12.5%)
MOV $0x406068,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
VFMADD213SD (%R9,%RAX,8),%XMM0,%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM1,(%R8,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1	scal (12.5%)
VMOVSD (%RDI,%RAX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD (%RCX),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	scal (12.5%)
VFMADD213SD (%RDX,%RAX,8),%XMM0,%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM1,(%RSI,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1	scal (12.5%)
MOV $0x4ceb88e40,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV $0x401030,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV %EBX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD $0x28,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
JMP %RAX	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	1	N/A

Name	Coverage (%)	Time (s)
▼main.extracted.50–	94.77	7.32
○Loop 13 - stream.c:355-356 - exec	94.77	7.24

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

FMA

CALL instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

FMA

CALL instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code