OV - exec - Function main.extracted.40

	Function: main.extracted.40	Module: exec	Source: stream.c:271-276	Coverage (incl. loops): 0.98% \| (excl. loops): 0.00%

/beegfs/hackathon/users/eoseret/qaas_runs_test/gpu04sas.benchmarkcenter.megware.com/177-374-0012/stream-triad/build/stream-triad/src/stream.c: 271 - 276

--------------------------------------------------------------------------------

271: #pragma omp parallel for

272:     for (j=0; j<STREAM_ARRAY_SIZE; j++) {

273: 	    a[j] = 1.0;

274: 	    b[j] = 2.0;

275: 	    c[j] = 0.0;

276: 	}

0x402c00 PUSH	%RBP

0x402c01 MOV	%RSP,%RBP

0x402c04 PUSH	%R15

0x402c06 PUSH	%R14

0x402c08 PUSH	%R13

0x402c0a PUSH	%R12

0x402c0c PUSH	%RBX

0x402c0d SUB	$0x28,%RSP

0x402c11 MOVL	$0,-0x2c(%RBP)

0x402c18 MOV	(%RDI),%EBX

0x402c1a MOVQ	$0,-0x40(%RBP)

0x402c22 MOVQ	$0x3344ffff,-0x38(%RBP)

0x402c2a MOVQ	$0x1,-0x48(%RBP)

0x402c32 SUB	$0x8,%RSP

0x402c36 LEA	-0x48(%RBP),%RAX

0x402c3a LEA	-0x38(%RBP),%R9

0x402c3e MOV	$0x4ceb88d60,%RDI

0x402c48 MOV	$0x401050,%R10

0x402c52 LEA	-0x2c(%RBP),%RCX

0x402c56 LEA	-0x40(%RBP),%R8

0x402c5a MOV	%EBX,%ESI

0x402c5c MOV	$0x22,%EDX

0x402c61 PUSH	$0x1

0x402c63 PUSH	$0x1

0x402c65 PUSH	%RAX

0x402c66 CALL	%R10

0x402c69 ADD	$0x20,%RSP

0x402c6d MOV	-0x40(%RBP),%RAX

0x402c71 MOV	-0x38(%RBP),%R9

0x402c75 CMP	%R9,%RAX

0x402c78 JA	402ecb

0x402c7e MOV	%R9,%R10

0x402c81 SUB	%RAX,%R10

0x402c84 MOV	$0x3ff0000000000000,%RCX

0x402c8e MOV	$0x4000000000000000,%RDX

0x402c98 MOV	$0x406060,%RSI

0x402ca2 MOV	$0x19a686060,%RDI

0x402cac MOV	$0x334906060,%R8

0x402cb6 INC	%R10

0x402cb9 CMP	$0x8,%R10

0x402cbd JB	402d82

0x402cc3 LEA	0x38(,%RAX,8),%R14

0x402ccb MOV	%R10,%R11

0x402cce SHR	$0x3,%R11

0x402cd2 NOPW	%CS:(%RAX,%RAX,1)

(11) 0x402ce0 LEA	-0x38(%R14,%RSI,1),%R15

(11) 0x402ce5 LEA	-0x38(%R14,%RDI,1),%R12

(11) 0x402cea LEA	-0x38(%R14,%R8,1),%R13

(11) 0x402cef ADD	$0x40,%R14

(11) 0x402cf3 DEC	%R11

(11) 0x402cf6 MOV	%RCX,(%R15)

(11) 0x402cf9 MOV	%RDX,(%R12)

(11) 0x402cfd MOVQ	$0,(%R13)

(11) 0x402d05 MOV	%RCX,0x8(%R15)

(11) 0x402d09 MOV	%RDX,0x8(%R12)

(11) 0x402d0e MOVQ	$0,0x8(%R13)

(11) 0x402d16 MOV	%RCX,0x10(%R15)

(11) 0x402d1a MOV	%RDX,0x10(%R12)

(11) 0x402d1f MOVQ	$0,0x10(%R13)

(11) 0x402d27 MOV	%RCX,0x18(%R15)

(11) 0x402d2b MOV	%RDX,0x18(%R12)

(11) 0x402d30 MOVQ	$0,0x18(%R13)

(11) 0x402d38 MOV	%RCX,0x20(%R15)

(11) 0x402d3c MOV	%RDX,0x20(%R12)

(11) 0x402d41 MOVQ	$0,0x20(%R13)

(11) 0x402d49 MOV	%RCX,0x28(%R15)

(11) 0x402d4d MOV	%RDX,0x28(%R12)

(11) 0x402d52 MOVQ	$0,0x28(%R13)

(11) 0x402d5a MOV	%RCX,0x30(%R15)

(11) 0x402d5e MOV	%RDX,0x30(%R12)

(11) 0x402d63 MOVQ	$0,0x30(%R13)

(11) 0x402d6b MOV	%RCX,0x38(%R15)

(11) 0x402d6f MOV	%RDX,0x38(%R12)

(11) 0x402d74 MOVQ	$0,0x38(%R13)

(11) 0x402d7c JNE	402ce0

0x402d82 AND	$0x7ffffff8,%R10D

0x402d89 ADD	%R10,%RAX

0x402d8c SUB	%RAX,%R9

0x402d8f CMP	$0x6,%R9

0x402d93 JA	402ecb

0x402d99 MOV	$0x4040d8,%R10

0x402da3 JMP	(%R10,%R9,8)

0x402da7 MOV	$0x406090,%R9

0x402db1 MOV	$0x19a686090,%R11

0x402dbb MOV	$0x334906090,%R10

0x402dc5 MOV	%RCX,(%R9,%RAX,8)

0x402dc9 MOV	%RDX,(%R11,%RAX,8)

0x402dcd MOVQ	$0,(%R10,%RAX,8)

0x402dd5 MOV	$0x406088,%R9

0x402ddf MOV	$0x19a686088,%R11

0x402de9 MOV	$0x334906088,%R10

0x402df3 MOV	%RCX,(%R9,%RAX,8)

0x402df7 MOV	%RDX,(%R11,%RAX,8)

0x402dfb MOVQ	$0,(%R10,%RAX,8)

0x402e03 MOV	$0x406080,%R9

0x402e0d MOV	$0x19a686080,%R11

0x402e17 MOV	$0x334906080,%R10

0x402e21 MOV	%RCX,(%R9,%RAX,8)

0x402e25 MOV	%RDX,(%R11,%RAX,8)

0x402e29 MOVQ	$0,(%R10,%RAX,8)

0x402e31 MOV	$0x406078,%R9

0x402e3b MOV	$0x19a686078,%R11

0x402e45 MOV	$0x334906078,%R10

0x402e4f MOV	%RCX,(%R9,%RAX,8)

0x402e53 MOV	%RDX,(%R11,%RAX,8)

0x402e57 MOVQ	$0,(%R10,%RAX,8)

0x402e5f MOV	$0x406070,%R9

0x402e69 MOV	$0x19a686070,%R11

0x402e73 MOV	$0x334906070,%R10

0x402e7d MOV	%RCX,(%R9,%RAX,8)

0x402e81 MOV	%RDX,(%R11,%RAX,8)

0x402e85 MOVQ	$0,(%R10,%RAX,8)

0x402e8d MOV	$0x406068,%R9

0x402e97 MOV	$0x19a686068,%R11

0x402ea1 MOV	$0x334906068,%R10

0x402eab MOV	%RCX,(%R9,%RAX,8)

0x402eaf MOV	%RDX,(%R11,%RAX,8)

0x402eb3 MOVQ	$0,(%R10,%RAX,8)

0x402ebb MOV	%RCX,(%RSI,%RAX,8)

0x402ebf MOV	%RDX,(%RDI,%RAX,8)

0x402ec3 MOVQ	$0,(%R8,%RAX,8)

0x402ecb MOV	$0x4ceb88d80,%RDI

0x402ed5 MOV	$0x401030,%RAX

0x402edf MOV	%EBX,%ESI

0x402ee1 ADD	$0x28,%RSP

0x402ee5 POP	%RBX

0x402ee6 POP	%R12

0x402ee8 POP	%R13

0x402eea POP	%R14

0x402eec POP	%R15

0x402eee POP	%RBP

0x402eef JMP	%RAX

0x402ef1 NOPW	%CS:(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
►100.00+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run icx_5

Source file and lines	stream.c:271-276
Module	exec

The function is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/gpu04sas.benchmarkcenter.megware.com/177-374-0012/stream-triad/build/stream-triad/src/stream.c:271-276.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 9% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 17.17 to 1.25 cycles (13.73x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gpu04sas.benchmarkcenter.megware.com/177-374-0012/stream-triad/build/stream-triad/src/stream.c:271

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

JMP: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gpu04sas.benchmarkcenter.megware.com/177-374-0012/stream-triad/build/stream-triad/src/stream.c:276

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 28 bytes. The binary function is storing 196 bytes.

General properties

nb instructions	103
nb uops	103
loop length	606
used x86 registers	16
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	17.17 cycles
front end	17.17 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	12.50	12.50	12.50	12.50	3.00	10.00	10.00	10.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	12.50	12.50	12.50	12.50	3.00	10.00	10.00	10.00	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU, BRU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1: BRU
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	17.17
Dispatch	12.50
Overall L1	17.17

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	9%
load	6%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 17.17 cycles. At this rate:

1% of peak load performance is reached (1.63 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
17% of peak store performance is reached (11.42 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 17.17 to 12.50 cycles (1.37x speedup).

ASM code

In the binary file, the address of the function is: 402c00

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x28,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOVL $0,-0x2c(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (6.3%)
MOV (%RDI),%EBX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33	scal (6.3%)
MOVQ $0,-0x40(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (6.3%)
MOVQ $0x3344ffff,-0x38(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (6.3%)
MOVQ $0x1,-0x48(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LEA -0x48(%RBP),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LEA -0x38(%RBP),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOV $0x4ceb88d60,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
MOV $0x401050,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
LEA -0x2c(%RBP),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LEA -0x40(%RBP),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOV %EBX,%ESI	1	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x22,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (6.3%)
PUSH $0x1	1	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL %R10	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	2	N/A
ADD $0x20,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOV -0x40(%RBP),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33	N/A
MOV -0x38(%RBP),%R9	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33	N/A
CMP %R9,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
JA 402ecb <main.extracted.40+0x2cb>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1	N/A
MOV %R9,%R10	1	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %RAX,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOV $0x3ff0000000000000,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	scal (12.5%)
MOV $0x4000000000000000,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	scal (12.5%)
MOV $0x406060,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
MOV $0x19a686060,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
MOV $0x334906060,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
INC %R10	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
CMP $0x8,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
JB 402d82 <main.extracted.40+0x182>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1	N/A
LEA 0x38(,%RAX,8),%R14	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOV %R10,%R11	1	0	0	0	0	0	0	0	0	0	0.17	N/A
SHR $0x3,%R11	1	0	0.50	0.50	0	0	0	0	0	1	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0.09	N/A
AND $0x7ffffff8,%R10D	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
ADD %R10,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
SUB %RAX,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
CMP $0x6,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
JA 402ecb <main.extracted.40+0x2cb>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1	N/A
MOV $0x4040d8,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
JMP (%R10,%R9,8)	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	1	N/A
MOV $0x406090,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
MOV $0x19a686090,%R11	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
MOV $0x334906090,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
MOV %RCX,(%R9,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (12.5%)
MOV %RDX,(%R11,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (12.5%)
MOVQ $0,(%R10,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (6.3%)
MOV $0x406088,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
MOV $0x19a686088,%R11	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
MOV $0x334906088,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
MOV %RCX,(%R9,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (12.5%)
MOV %RDX,(%R11,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (12.5%)
MOVQ $0,(%R10,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (6.3%)
MOV $0x406080,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
MOV $0x19a686080,%R11	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
MOV $0x334906080,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
MOV %RCX,(%R9,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (12.5%)
MOV %RDX,(%R11,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (12.5%)
MOVQ $0,(%R10,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (6.3%)
MOV $0x406078,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
MOV $0x19a686078,%R11	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
MOV $0x334906078,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
MOV %RCX,(%R9,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (12.5%)
MOV %RDX,(%R11,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (12.5%)
MOVQ $0,(%R10,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (6.3%)
MOV $0x406070,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
MOV $0x19a686070,%R11	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
MOV $0x334906070,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
MOV %RCX,(%R9,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (12.5%)
MOV %RDX,(%R11,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (12.5%)
MOVQ $0,(%R10,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (6.3%)
MOV $0x406068,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
MOV $0x19a686068,%R11	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
MOV $0x334906068,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
MOV %RCX,(%R9,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (12.5%)
MOV %RDX,(%R11,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (12.5%)
MOVQ $0,(%R10,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (6.3%)
MOV %RCX,(%RSI,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (12.5%)
MOV %RDX,(%RDI,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (12.5%)
MOVQ $0,(%R8,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (6.3%)
MOV $0x4ceb88d80,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
MOV $0x401030,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
MOV %EBX,%ESI	1	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD $0x28,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	1	0.33	N/A
JMP %RAX	1	0.50	0	0	0	0.50	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run icx_5

Source file and lines	stream.c:271-276
Module	exec

gain
potential
hint
expert

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

unknown: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gpu04sas.benchmarkcenter.megware.com/177-374-0012/stream-triad/build/stream-triad/src/stream.c:271

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

JMP: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gpu04sas.benchmarkcenter.megware.com/177-374-0012/stream-triad/build/stream-triad/src/stream.c:276

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 28 bytes. The binary function is storing 196 bytes.

General properties

nb instructions	103
nb uops	103
loop length	606
used x86 registers	16
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	17.17 cycles
front end	17.17 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	12.50	12.50	12.50	12.50	3.00	10.00	10.00	10.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	12.50	12.50	12.50	12.50	3.00	10.00	10.00	10.00	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU, BRU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1: BRU
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	17.17
Dispatch	12.50
Overall L1	17.17

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	9%
load	6%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 17.17 cycles. At this rate:

1% of peak load performance is reached (1.63 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
17% of peak store performance is reached (11.42 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 402c00

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x28,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOVL $0,-0x2c(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (6.3%)
MOV (%RDI),%EBX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33	scal (6.3%)
MOVQ $0,-0x40(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (6.3%)
MOVQ $0x3344ffff,-0x38(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (6.3%)
MOVQ $0x1,-0x48(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LEA -0x48(%RBP),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LEA -0x38(%RBP),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOV $0x4ceb88d60,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
MOV $0x401050,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
LEA -0x2c(%RBP),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
LEA -0x40(%RBP),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOV %EBX,%ESI	1	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x22,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (6.3%)
PUSH $0x1	1	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL %R10	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	2	N/A
ADD $0x20,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOV -0x40(%RBP),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33	N/A
MOV -0x38(%RBP),%R9	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33	N/A
CMP %R9,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
JA 402ecb <main.extracted.40+0x2cb>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1	N/A
MOV %R9,%R10	1	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %RAX,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOV $0x3ff0000000000000,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	scal (12.5%)
MOV $0x4000000000000000,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	scal (12.5%)
MOV $0x406060,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
MOV $0x19a686060,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
MOV $0x334906060,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
INC %R10	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
CMP $0x8,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
JB 402d82 <main.extracted.40+0x182>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1	N/A
LEA 0x38(,%RAX,8),%R14	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOV %R10,%R11	1	0	0	0	0	0	0	0	0	0	0.17	N/A
SHR $0x3,%R11	1	0	0.50	0.50	0	0	0	0	0	1	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0.09	N/A
AND $0x7ffffff8,%R10D	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
ADD %R10,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
SUB %RAX,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
CMP $0x6,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
JA 402ecb <main.extracted.40+0x2cb>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1	N/A
MOV $0x4040d8,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
JMP (%R10,%R9,8)	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	1	N/A
MOV $0x406090,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
MOV $0x19a686090,%R11	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
MOV $0x334906090,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
MOV %RCX,(%R9,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (12.5%)
MOV %RDX,(%R11,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (12.5%)
MOVQ $0,(%R10,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (6.3%)
MOV $0x406088,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
MOV $0x19a686088,%R11	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
MOV $0x334906088,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
MOV %RCX,(%R9,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (12.5%)
MOV %RDX,(%R11,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (12.5%)
MOVQ $0,(%R10,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (6.3%)
MOV $0x406080,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
MOV $0x19a686080,%R11	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
MOV $0x334906080,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
MOV %RCX,(%R9,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (12.5%)
MOV %RDX,(%R11,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (12.5%)
MOVQ $0,(%R10,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (6.3%)
MOV $0x406078,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
MOV $0x19a686078,%R11	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
MOV $0x334906078,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
MOV %RCX,(%R9,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (12.5%)
MOV %RDX,(%R11,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (12.5%)
MOVQ $0,(%R10,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (6.3%)
MOV $0x406070,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
MOV $0x19a686070,%R11	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
MOV $0x334906070,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
MOV %RCX,(%R9,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (12.5%)
MOV %RDX,(%R11,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (12.5%)
MOVQ $0,(%R10,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (6.3%)
MOV $0x406068,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
MOV $0x19a686068,%R11	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
MOV $0x334906068,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
MOV %RCX,(%R9,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (12.5%)
MOV %RDX,(%R11,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (12.5%)
MOVQ $0,(%R10,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (6.3%)
MOV %RCX,(%RSI,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (12.5%)
MOV %RDX,(%RDI,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (12.5%)
MOVQ $0,(%R8,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50	scal (6.3%)
MOV $0x4ceb88d80,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
MOV $0x401030,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33	N/A
MOV %EBX,%ESI	1	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD $0x28,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	1	0.33	N/A
JMP %RAX	1	0.50	0	0	0	0.50	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼main.extracted.40–	0.98	0.08
○Loop 11 - stream.c:272-276 - exec	0.98	0.07

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code