OV - exec - Loop 7

0x203480 VMOVUPD	-0x30(%R8,%R9,8),%XMM0    [1]

0x203487 VMOVUPD	-0x20(%R8,%R9,8),%XMM1    [1]

0x20348e VMOVUPD	-0x10(%R8,%R9,8),%XMM2    [1]

0x203495 VMOVUPD	(%R8,%R9,8),%XMM3    [1]

0x20349b VADDPD	%XMM0,%XMM0,%XMM0

0x20349f VADDPD	%XMM1,%XMM1,%XMM1

0x2034a3 VADDPD	%XMM2,%XMM2,%XMM2

0x2034a7 VADDPD	%XMM3,%XMM3,%XMM3

0x2034ab VMOVUPD	%XMM0,-0x30(%R8,%R9,8)    [1]

0x2034b2 VMOVUPD	%XMM1,-0x20(%R8,%R9,8)    [1]

0x2034b9 VMOVUPD	%XMM2,-0x10(%R8,%R9,8)    [1]

0x2034c0 VMOVUPD	%XMM3,(%R8,%R9,8)    [1]

0x2034c6 ADD	$0x8,%R9

0x2034ca CMP	%R9,%RDI

0x2034cd JNE	203480

/beegfs/hackathon/users/eoseret/qaas_runs_test/gpu04sas.benchmarkcenter.megware.com/177-374-0012/stream-triad/build/stream-triad/src/stream.c: 292 - 292

--------------------------------------------------------------------------------

292: 		a[j] = 2.0E0 * a[j];

Coverage (%)	Name	Source Location	Module
►99.08+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	2.67
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.14
Bottlenecks	P5, P6, P7,
Function	main.omp_outlined.18
Source	stream.c:292-292
Source loop unroll info	unrolled by 8
Source loop unroll confidence level	max
Unroll/vectorization loop type	main
Unroll factor	8
CQA cycles	2.67
CQA cycles if no scalar integer	2.67
CQA cycles if FP arith vectorized	2.67
CQA cycles if fully vectorized	1.00
Front-end cycles	2.33
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.25
P3 cycles	0.25
P4 cycles	0.50
P5 cycles	2.67
P6 cycles	2.67
P7 cycles	2.67
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	2.00
P11 cycles	2.00
P12 cycles	2.00
P13 cycles	2.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	15.00
Nb uops	14.00
Nb loads	4.00
Nb stores	4.00
Nb stack references	0.00
FLOP/cycle	3.00
Nb FLOP add-sub	8.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	48.00
Bytes prefetched	0.00
Bytes loaded	64.00
Bytes stored	64.00
Stride 0	0.00
Stride 1	1.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	2.67
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.14
Bottlenecks	P5, P6, P7,
Function	main.omp_outlined.18
Source	stream.c:292-292
Source loop unroll info	unrolled by 8
Source loop unroll confidence level	max
Unroll/vectorization loop type	main
Unroll factor	8
CQA cycles	2.67
CQA cycles if no scalar integer	2.67
CQA cycles if FP arith vectorized	2.67
CQA cycles if fully vectorized	1.00
Front-end cycles	2.33
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.25
P3 cycles	0.25
P4 cycles	0.50
P5 cycles	2.67
P6 cycles	2.67
P7 cycles	2.67
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	2.00
P11 cycles	2.00
P12 cycles	2.00
P13 cycles	2.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	15.00
Nb uops	14.00
Nb loads	4.00
Nb stores	4.00
Nb stack references	0.00
FLOP/cycle	3.00
Nb FLOP add-sub	8.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	48.00
Bytes prefetched	0.00
Bytes loaded	64.00
Bytes stored	64.00
Stride 0	0.00
Stride 1	1.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main.omp_outlined.18
Source file and lines	stream.c:292-292
Module	exec

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/gpu04sas.benchmarkcenter.megware.com/177-374-0012/stream-triad/build/stream-triad/src/stream.c:292.

It is main loop of related source loop which is unrolled by 8 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is vectorized, but using only 128 out of 512 bits (SSE/AVX-128 instructions on AVX-512 processors).

By fully vectorizing your loop, you can lower the cost of an iteration from 2.67 to 1.00 cycles (2.67x speedup).

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers). Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 2.67 to 2.33 cycles (1.14x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop
- use the 'restrict' C99 keyword

No data for this section

Type of elements and instruction set

4 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 8 FP arithmetical operations:

8: addition or subtraction

The binary loop is loading 64 bytes (8 double precision FP elements). The binary loop is storing 64 bytes (8 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.06 FP operations per loaded or stored byte.

General properties

nb instructions	15
nb uops	14
loop length	79
used x86 registers	3
used mmx registers	0
used xmm registers	4
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	2.33 cycles
front end	2.33 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	0.50	0.50	0.25	0.25	0.50	2.67	2.67	2.67	0.00	0.00	2.00	2.00	2.00	2.00
cycles	0.50	0.50	0.25	0.25	0.50	2.67	2.67	2.67	0.00	0.00	2.00	2.00	2.00	2.00

Execution ports to units layout:

ALU0/BRU0: ALU, BRU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1: BRU
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	2.33
Dispatch	2.67
Data deps.	1.00
Overall L1	2.67

Vectorization ratios

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	25%
load	25%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 2.67 cycles. At this rate:

25% of peak load performance is reached (24.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
37% of peak store performance is reached (24.00 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 203480

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP2	FP3	FP4	FP5	Latency	Recip. throughput	Vectorization
VMOVUPD -0x30(%R8,%R9,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.50	vect (25.0%)
VMOVUPD -0x20(%R8,%R9,8),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.50	vect (25.0%)
VMOVUPD -0x10(%R8,%R9,8),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.50	vect (25.0%)
VMOVUPD (%R8,%R9,8),%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.50	vect (25.0%)
VADDPD %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (25.0%)
VADDPD %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (25.0%)
VADDPD %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (25.0%)
VADDPD %XMM3,%XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (25.0%)
VMOVUPD %XMM0,-0x30(%R8,%R9,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	4	1	vect (25.0%)
VMOVUPD %XMM1,-0x20(%R8,%R9,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	4	1	vect (25.0%)
VMOVUPD %XMM2,-0x10(%R8,%R9,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	4	1	vect (25.0%)
VMOVUPD %XMM3,(%R8,%R9,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	4	1	vect (25.0%)
ADD $0x8,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP %R9,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
JNE 203480 <main.omp_outlined.18+0xc0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1	N/A

Function	main.omp_outlined.18
Source file and lines	stream.c:292-292
Module	exec

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/gpu04sas.benchmarkcenter.megware.com/177-374-0012/stream-triad/build/stream-triad/src/stream.c:292.

It is main loop of related source loop which is unrolled by 8 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is vectorized, but using only 128 out of 512 bits (SSE/AVX-128 instructions on AVX-512 processors).

By fully vectorizing your loop, you can lower the cost of an iteration from 2.67 to 1.00 cycles (2.67x speedup).

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers). Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 2.67 to 2.33 cycles (1.14x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop
- use the 'restrict' C99 keyword

No data for this section

Type of elements and instruction set

4 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 8 FP arithmetical operations:

8: addition or subtraction

The binary loop is loading 64 bytes (8 double precision FP elements). The binary loop is storing 64 bytes (8 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.06 FP operations per loaded or stored byte.

General properties

nb instructions	15
nb uops	14
loop length	79
used x86 registers	3
used mmx registers	0
used xmm registers	4
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	2.33 cycles
front end	2.33 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	0.50	0.50	0.25	0.25	0.50	2.67	2.67	2.67	0.00	0.00	2.00	2.00	2.00	2.00
cycles	0.50	0.50	0.25	0.25	0.50	2.67	2.67	2.67	0.00	0.00	2.00	2.00	2.00	2.00

Execution ports to units layout:

ALU0/BRU0: ALU, BRU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1: BRU
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	2.33
Dispatch	2.67
Data deps.	1.00
Overall L1	2.67

Vectorization ratios

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	25%
load	25%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 2.67 cycles. At this rate:

25% of peak load performance is reached (24.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
37% of peak store performance is reached (24.00 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 203480

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP2	FP3	FP4	FP5	Latency	Recip. throughput	Vectorization
VMOVUPD -0x30(%R8,%R9,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.50	vect (25.0%)
VMOVUPD -0x20(%R8,%R9,8),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.50	vect (25.0%)
VMOVUPD -0x10(%R8,%R9,8),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.50	vect (25.0%)
VMOVUPD (%R8,%R9,8),%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.50	vect (25.0%)
VADDPD %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (25.0%)
VADDPD %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (25.0%)
VADDPD %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (25.0%)
VADDPD %XMM3,%XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	vect (25.0%)
VMOVUPD %XMM0,-0x30(%R8,%R9,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	4	1	vect (25.0%)
VMOVUPD %XMM1,-0x20(%R8,%R9,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	4	1	vect (25.0%)
VMOVUPD %XMM2,-0x10(%R8,%R9,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	4	1	vect (25.0%)
VMOVUPD %XMM3,(%R8,%R9,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	4	1	vect (25.0%)
ADD $0x8,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP %R9,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25	N/A
JNE 203480 <main.omp_outlined.18+0xc0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code