OV - exec - Function main.omp

	Function: main.omp_outlined.27	Module: exec	Source: stream.c:354-356	Coverage (incl. loops): 95.78% \| (excl. loops): 0.00%

/beegfs/hackathon/users/eoseret/qaas_runs_test/gpu04sas.benchmarkcenter.megware.com/177-374-0012/stream-triad/build/stream-triad/src/stream.c: 354 - 356

--------------------------------------------------------------------------------

354: #pragma omp parallel for

355: 	for (j=0; j<STREAM_ARRAY_SIZE; j++)

356: 	    a[j] = b[j]+scalar*c[j];

0x203520 PUSH	%RBP

0x203521 MOV	%RSP,%RBP

0x203524 PUSH	%R15

0x203526 PUSH	%R14

0x203528 PUSH	%R12

0x20352a PUSH	%RBX

0x20352b SUB	$0x20,%RSP

0x20352f MOV	(%RDI),%R14D

0x203532 LEA	0x3067(%RIP),%RBX

0x203539 MOV	%RDX,%R15

0x20353c MOVQ	$0,-0x38(%RBP)

0x203544 MOVQ	$0x3344ffff,-0x28(%RBP)

0x20354c MOVQ	$0x1,-0x40(%RBP)

0x203554 MOVL	$0,-0x2c(%RBP)

0x20355b SUB	$0x8,%RSP

0x20355f MOV	$0x1148,%RDI

0x203569 LEA	-0x40(%RBP),%RAX

0x20356d LEA	-0x2c(%RBP),%RCX

0x203571 LEA	-0x38(%RBP),%R8

0x203575 LEA	-0x28(%RBP),%R9

0x203579 MOV	%R14D,%ESI

0x20357c MOV	$0x22,%EDX

0x203581 ADD	%RBX,%RDI

0x203584 PUSH	$0x1

0x203586 PUSH	$0x1

0x203588 PUSH	%RAX

0x203589 CALL	2043a0 <@plt_start@+0x80>

0x20358e ADD	$0x20,%RSP

0x203592 MOV	-0x28(%RBP),%RCX

0x203596 MOV	-0x38(%RBP),%R12

0x20359a MOV	$0x3344ffff,%EAX

0x20359f CMP	$0x3344ffff,%RCX

0x2035a6 CMOVL	%RCX,%RAX

0x2035aa MOV	%RAX,-0x28(%RBP)

0x2035ae CMP	%RAX,%R12

0x2035b1 JG	2036ab

0x2035b7 VMOVSD	(%R15),%XMM0

0x2035bc MOV	%RAX,%R8

0x2035bf SUB	%R12,%R8

0x2035c2 MOV	$0x19a281190,%RCX

0x2035cc MOV	$0x334501190,%RDX

0x2035d6 MOV	$0x1190,%RSI

0x2035e0 INC	%R8

0x2035e3 CMP	$0x8,%R8

0x2035e7 JAE	2035f1

0x2035e9 MOV	%R12,%RDI

0x2035ec JMP	20367f

0x2035f1 LEA	(%RBX,%RCX,1),%R10

0x2035f5 LEA	(%RBX,%RDX,1),%R11

0x2035f9 LEA	(%RBX,%RSI,1),%R15

0x2035fd MOV	%R8,%R9

0x203600 AND	$-0x8,%R9

0x203604 VMOVDDUP	%XMM0,%XMM1

0x203608 LEA	0x30(%R10,%R12,8),%R10

0x20360d LEA	0x30(%R11,%R12,8),%R11

0x203612 LEA	0x30(%R15,%R12,8),%R15

0x203617 LEA	(%R12,%R9,1),%RDI

0x20361b XOR	%R12D,%R12D

0x20361e XCHG	%AX,%AX

(8) 0x203620 VMOVUPD	-0x30(%R11,%R12,8),%XMM2

(8) 0x203627 VMOVUPD	-0x20(%R11,%R12,8),%XMM3

(8) 0x20362e VMOVUPD	-0x10(%R11,%R12,8),%XMM4

(8) 0x203635 VMOVUPD	(%R11,%R12,8),%XMM5

(8) 0x20363b VFMADD213PD	-0x30(%R10,%R12,8),%XMM1,%XMM2

(8) 0x203642 VFMADD213PD	-0x20(%R10,%R12,8),%XMM1,%XMM3

(8) 0x203649 VFMADD213PD	-0x10(%R10,%R12,8),%XMM1,%XMM4

(8) 0x203650 VFMADD213PD	(%R10,%R12,8),%XMM1,%XMM5

(8) 0x203656 VMOVUPD	%XMM2,-0x30(%R15,%R12,8)

(8) 0x20365d VMOVUPD	%XMM3,-0x20(%R15,%R12,8)

(8) 0x203664 VMOVUPD	%XMM4,-0x10(%R15,%R12,8)

(8) 0x20366b VMOVUPD	%XMM5,(%R15,%R12,8)

(8) 0x203671 ADD	$0x8,%R12

(8) 0x203675 CMP	%R12,%R9

(8) 0x203678 JNE	203620

0x20367a CMP	%R9,%R8

0x20367d JE	2036ab

0x20367f DEC	%RDI

0x203682 ADD	%RBX,%RCX

0x203685 ADD	%RBX,%RDX

0x203688 ADD	%RBX,%RSI

0x20368b NOPL	(%RAX,%RAX,1)

(9) 0x203690 VMOVSD	0x8(%RDX,%RDI,8),%XMM1

(9) 0x203696 VFMADD213SD	0x8(%RCX,%RDI,8),%XMM0,%XMM1

(9) 0x20369d VMOVSD	%XMM1,0x8(%RSI,%RDI,8)

(9) 0x2036a3 INC	%RDI

(9) 0x2036a6 CMP	%RAX,%RDI

(9) 0x2036a9 JL	203690

0x2036ab MOV	$0x1160,%RAX

0x2036b5 MOV	%R14D,%ESI

0x2036b8 ADD	%RAX,%RBX

0x2036bb MOV	%RBX,%RDI

0x2036be CALL	2043c0 <@plt_start@+0xa0>

0x2036c3 ADD	$0x20,%RSP

0x2036c7 POP	%RBX

0x2036c8 POP	%R12

0x2036ca POP	%R14

0x2036cc POP	%R15

0x2036ce POP	%RBP

0x2036cf RET

Coverage (%)	Name	Source Location	Module
►99.56+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run aocc_4

Source file and lines	stream.c:354-356
Module	exec

The function is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/gpu04sas.benchmarkcenter.megware.com/177-374-0012/stream-triad/build/stream-triad/src/stream.c:354-356.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 13.50 to 1.50 cycles (9.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 10% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 13.50 to 0.93 cycles (14.51x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 2 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gpu04sas.benchmarkcenter.megware.com/177-374-0012/stream-triad/build/stream-triad/src/stream.c:354
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gpu04sas.benchmarkcenter.megware.com/177-374-0012/stream-triad/build/stream-triad/src/stream.c:354

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

LEA: 3 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gpu04sas.benchmarkcenter.megware.com/177-374-0012/stream-triad/build/stream-triad/src/stream.c:355
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gpu04sas.benchmarkcenter.megware.com/177-374-0012/stream-triad/build/stream-triad/src/stream.c:355
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gpu04sas.benchmarkcenter.megware.com/177-374-0012/stream-triad/build/stream-triad/src/stream.c:355

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 28 bytes. The binary function is storing 36 bytes.

General properties

nb instructions	78
nb uops	81
loop length	315
used x86 registers	15
used mmx registers	0
used xmm registers	2
used ymm registers	0
used zmm registers	0
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	13.50 cycles
front end	13.50 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	10.25	10.25	10.00	10.00	3.50	4.67	4.67	4.67	0.00	0.33	0.33	0.33	0.00	0.00
cycles	10.25	10.25	10.00	10.00	3.50	4.67	4.67	4.67	0.00	0.33	0.33	0.33	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU, BRU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1: BRU
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	13.50
Dispatch	10.25
Overall L1	13.50

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	10%
load	6%
store	7%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	10%
load	9%
store	7%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 13.50 cycles. At this rate:

2% of peak load performance is reached (2.07 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (2.67 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 13.50 to 10.25 cycles (1.32x speedup).

ASM code

In the binary file, the address of the function is: 203520

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP1	FP2	FP3	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x20,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
MOV (%RDI),%R14D	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	0.33	scal (6.3%)
LEA 0x3067(%RIP),%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
MOV %RDX,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOVQ $0,-0x38(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	4	0.50	scal (6.3%)
MOVQ $0x3344ffff,-0x28(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	4	0.50	scal (6.3%)
MOVQ $0x1,-0x40(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	4	0.50	scal (6.3%)
MOVL $0,-0x2c(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	4	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
MOV $0x1148,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	N/A
LEA -0x40(%RBP),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x2c(%RBP),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x38(%RBP),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x28(%RBP),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
MOV %R14D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x22,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD %RBX,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 2043a0 <@plt_start@+0x80>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0.50	N/A
ADD $0x20,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
MOV -0x28(%RBP),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	0.33	N/A
MOV -0x38(%RBP),%R12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	0.33	N/A
MOV $0x3344ffff,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
CMP $0x3344ffff,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMOVL %RCX,%RAX	1	0.50	0	0	0.50	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RAX,-0x28(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	4	0.50	scal (12.5%)
CMP %RAX,%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JG 2036ab <main.omp_outlined.27+0x18b>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50-1	N/A
VMOVSD (%R15),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	1	0.50	scal (12.5%)
MOV %RAX,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
SUB %R12,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOV $0x19a281190,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	N/A
MOV $0x334501190,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	N/A
MOV $0x1190,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	N/A
INC %R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP $0x8,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JAE 2035f1 <main.omp_outlined.27+0xd1>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50-1	N/A
MOV %R12,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 20367f <main.omp_outlined.27+0x15f>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	N/A
LEA (%RBX,%RCX,1),%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%RBX,%RDX,1),%R11	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%RBX,%RSI,1),%R15	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
MOV %R8,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x8,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
VMOVDDUP %XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
LEA 0x30(%R10,%R12,8),%R10	2	0	0	0.50	0.50	0	0.33	0.33	0.33	0	0	0	2	0.50	N/A
LEA 0x30(%R11,%R12,8),%R11	2	0	0	0.50	0.50	0	0.33	0.33	0.33	0	0	0	2	0.50	N/A
LEA 0x30(%R15,%R12,8),%R15	2	0	0	0.50	0.50	0	0.33	0.33	0.33	0	0	0	2	0.50	N/A
LEA (%R12,%R9,1),%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
XOR %R12D,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
CMP %R9,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 2036ab <main.omp_outlined.27+0x18b>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50-1	N/A
DEC %RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD %RBX,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD %RBX,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD %RBX,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV $0x1160,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	N/A
MOV %R14D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD %RAX,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 2043c0 <@plt_start@+0xa0>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0.50	N/A
ADD $0x20,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run aocc_4

Source file and lines	stream.c:354-356
Module	exec

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 13.50 to 1.50 cycles (9.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

unknown: 2 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gpu04sas.benchmarkcenter.megware.com/177-374-0012/stream-triad/build/stream-triad/src/stream.c:354
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gpu04sas.benchmarkcenter.megware.com/177-374-0012/stream-triad/build/stream-triad/src/stream.c:354

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

LEA: 3 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gpu04sas.benchmarkcenter.megware.com/177-374-0012/stream-triad/build/stream-triad/src/stream.c:355
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gpu04sas.benchmarkcenter.megware.com/177-374-0012/stream-triad/build/stream-triad/src/stream.c:355
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gpu04sas.benchmarkcenter.megware.com/177-374-0012/stream-triad/build/stream-triad/src/stream.c:355

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 28 bytes. The binary function is storing 36 bytes.

General properties

nb instructions	78
nb uops	81
loop length	315
used x86 registers	15
used mmx registers	0
used xmm registers	2
used ymm registers	0
used zmm registers	0
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	13.50 cycles
front end	13.50 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	10.25	10.25	10.00	10.00	3.50	4.67	4.67	4.67	0.00	0.33	0.33	0.33	0.00	0.00
cycles	10.25	10.25	10.00	10.00	3.50	4.67	4.67	4.67	0.00	0.33	0.33	0.33	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU, BRU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1: BRU
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	13.50
Dispatch	10.25
Overall L1	13.50

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	10%
load	6%
store	7%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	10%
load	9%
store	7%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 13.50 cycles. At this rate:

2% of peak load performance is reached (2.07 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (2.67 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 203520

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP1	FP2	FP3	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x20,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
MOV (%RDI),%R14D	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	0.33	scal (6.3%)
LEA 0x3067(%RIP),%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
MOV %RDX,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOVQ $0,-0x38(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	4	0.50	scal (6.3%)
MOVQ $0x3344ffff,-0x28(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	4	0.50	scal (6.3%)
MOVQ $0x1,-0x40(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	4	0.50	scal (6.3%)
MOVL $0,-0x2c(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	4	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
MOV $0x1148,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	N/A
LEA -0x40(%RBP),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x2c(%RBP),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x38(%RBP),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x28(%RBP),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
MOV %R14D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x22,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD %RBX,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 2043a0 <@plt_start@+0x80>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0.50	N/A
ADD $0x20,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
MOV -0x28(%RBP),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	0.33	N/A
MOV -0x38(%RBP),%R12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	0.33	N/A
MOV $0x3344ffff,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
CMP $0x3344ffff,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMOVL %RCX,%RAX	1	0.50	0	0	0.50	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RAX,-0x28(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	4	0.50	scal (12.5%)
CMP %RAX,%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JG 2036ab <main.omp_outlined.27+0x18b>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50-1	N/A
VMOVSD (%R15),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	1	0.50	scal (12.5%)
MOV %RAX,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
SUB %R12,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOV $0x19a281190,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	N/A
MOV $0x334501190,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	N/A
MOV $0x1190,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	N/A
INC %R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP $0x8,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JAE 2035f1 <main.omp_outlined.27+0xd1>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50-1	N/A
MOV %R12,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 20367f <main.omp_outlined.27+0x15f>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	N/A
LEA (%RBX,%RCX,1),%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%RBX,%RDX,1),%R11	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%RBX,%RSI,1),%R15	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
MOV %R8,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x8,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
VMOVDDUP %XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
LEA 0x30(%R10,%R12,8),%R10	2	0	0	0.50	0.50	0	0.33	0.33	0.33	0	0	0	2	0.50	N/A
LEA 0x30(%R11,%R12,8),%R11	2	0	0	0.50	0.50	0	0.33	0.33	0.33	0	0	0	2	0.50	N/A
LEA 0x30(%R15,%R12,8),%R15	2	0	0	0.50	0.50	0	0.33	0.33	0.33	0	0	0	2	0.50	N/A
LEA (%R12,%R9,1),%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
XOR %R12D,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
CMP %R9,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 2036ab <main.omp_outlined.27+0x18b>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50-1	N/A
DEC %RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD %RBX,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD %RBX,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD %RBX,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV $0x1160,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	N/A
MOV %R14D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD %RAX,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 2043c0 <@plt_start@+0xa0>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0.50	N/A
ADD $0x20,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼main.omp_outlined.27–	95.78	7.21
○Loop 8 - stream.c:356-356 - exec	95.78	7.09
○Loop 9 - stream.c:355-356 - exec	0.00	0.00

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code