OV - exec - Function main._omp

	Function: main._omp_fn.4	Module: exec	Source: stream.c:354-356	Coverage (incl. loops): 95.33% \| (excl. loops): 0.00%

/beegfs/hackathon/users/eoseret/qaas_runs_test/gpu04sas.benchmarkcenter.megware.com/177-374-0012/stream-triad/build/stream-triad/src/stream.c: 354 - 356

--------------------------------------------------------------------------------

354: #pragma omp parallel for

355: 	for (j=0; j<STREAM_ARRAY_SIZE; j++)

356: 	    a[j] = b[j]+scalar*c[j];

0x402110 PUSH	%RBP

0x402111 MOV	$0x401060,%RAX

0x40211b MOV	%RSP,%RBP

0x40211e PUSH	%R14

0x402120 PUSH	%R13

0x402122 PUSH	%R12

0x402124 PUSH	%RBX

0x402125 MOV	%RDI,%RBX

0x402128 MOV	$0x401030,%R13

0x402132 AND	$-0x40,%RSP

0x402136 CALL	%RAX

0x402138 MOVSXD	%EAX,%R12

0x40213b CALL	%R13

0x40213e MOVSXD	%EAX,%RCX

0x402141 MOV	$0x33450000,%EAX

0x402146 CQTO

0x402148 IDIV	%R12

0x40214b CMP	%RDX,%RCX

0x40214e JL	402440

0x402154 IMUL	%RAX,%RCX

0x402158 ADD	%RCX,%RDX

0x40215b LEA	(%RAX,%RDX,1),%R10

0x40215f CMP	%R10,%RDX

0x402162 JGE	40241d

0x402168 LEA	-0x1(%RAX),%RSI

0x40216c VMOVSD	(%RBX),%XMM1

0x402170 MOV	%RDX,%RBX

0x402173 CMP	$0x6,%RSI

0x402177 JBE	402450

0x40217d MOV	%RAX,%R11

0x402180 LEA	(,%RDX,8),%RSI

0x402188 MOV	$0x19a686100,%R13

0x402192 MOV	$0x406100,%R14

0x40219c SHR	$0x3,%R11

0x4021a0 VBROADCASTSD	%XMM1,%ZMM0

0x4021a6 SAL	$0x6,%R11

0x4021aa LEA	-0x40(%R11),%R9

0x4021ae MOV	$0x334906100,%R12

0x4021b8 LEA	(%R13,%RSI,1),%RDI

0x4021bd LEA	(%R14,%RSI,1),%R8

0x4021c1 SHR	$0x6,%R9

0x4021c5 INC	%R9

0x4021c8 ADD	%R12,%RSI

0x4021cb XOR	%ECX,%ECX

0x4021cd AND	$0x7,%R9D

0x4021d1 JE	4022b9

0x4021d7 CMP	$0x1,%R9

0x4021db JE	402297

0x4021e1 CMP	$0x2,%R9

0x4021e5 JE	40227e

0x4021eb CMP	$0x3,%R9

0x4021ef JE	402265

0x4021f1 CMP	$0x4,%R9

0x4021f5 JE	40224c

0x4021f7 CMP	$0x5,%R9

0x4021fb JE	402233

0x4021fd CMP	$0x6,%R9

0x402201 JE	40221a

0x402203 VMOVUPD	(%R8),%ZMM2

0x402209 MOV	$0x40,%ECX

0x40220e VFMADD213PD	(%RDI),%ZMM0,%ZMM2

0x402214 VMOVUPD	%ZMM2,(%RSI)

0x40221a VMOVUPD	(%R8,%RCX,1),%ZMM3

0x402221 VFMADD213PD	(%RDI,%RCX,1),%ZMM0,%ZMM3

0x402228 VMOVUPD	%ZMM3,(%RSI,%RCX,1)

0x40222f ADD	$0x40,%RCX

0x402233 VMOVUPD	(%R8,%RCX,1),%ZMM4

0x40223a VFMADD213PD	(%RDI,%RCX,1),%ZMM0,%ZMM4

0x402241 VMOVUPD	%ZMM4,(%RSI,%RCX,1)

0x402248 ADD	$0x40,%RCX

0x40224c VMOVUPD	(%R8,%RCX,1),%ZMM5

0x402253 VFMADD213PD	(%RDI,%RCX,1),%ZMM0,%ZMM5

0x40225a VMOVUPD	%ZMM5,(%RSI,%RCX,1)

0x402261 ADD	$0x40,%RCX

0x402265 VMOVUPD	(%R8,%RCX,1),%ZMM6

0x40226c VFMADD213PD	(%RDI,%RCX,1),%ZMM0,%ZMM6

0x402273 VMOVUPD	%ZMM6,(%RSI,%RCX,1)

0x40227a ADD	$0x40,%RCX

0x40227e VMOVUPD	(%R8,%RCX,1),%ZMM7

0x402285 VFMADD213PD	(%RDI,%RCX,1),%ZMM0,%ZMM7

0x40228c VMOVUPD	%ZMM7,(%RSI,%RCX,1)

0x402293 ADD	$0x40,%RCX

0x402297 VMOVUPD	(%R8,%RCX,1),%ZMM8

0x40229e VFMADD213PD	(%RDI,%RCX,1),%ZMM0,%ZMM8

0x4022a5 VMOVUPD	%ZMM8,(%RSI,%RCX,1)

0x4022ac ADD	$0x40,%RCX

0x4022b0 CMP	%R11,%RCX

0x4022b3 JE	402386

(2) 0x4022b9 VMOVUPD	(%R8,%RCX,1),%ZMM9

(2) 0x4022c0 VFMADD213PD	(%RDI,%RCX,1),%ZMM0,%ZMM9

(2) 0x4022c7 VMOVUPD	%ZMM9,(%RSI,%RCX,1)

(2) 0x4022ce VMOVUPD	0x40(%R8,%RCX,1),%ZMM10

(2) 0x4022d6 VFMADD213PD	0x40(%RDI,%RCX,1),%ZMM0,%ZMM10

(2) 0x4022de VMOVUPD	%ZMM10,0x40(%RSI,%RCX,1)

(2) 0x4022e6 VMOVUPD	0x80(%R8,%RCX,1),%ZMM11

(2) 0x4022ee VFMADD213PD	0x80(%RDI,%RCX,1),%ZMM0,%ZMM11

(2) 0x4022f6 VMOVUPD	%ZMM11,0x80(%RSI,%RCX,1)

(2) 0x4022fe VMOVUPD	0xc0(%R8,%RCX,1),%ZMM12

(2) 0x402306 VFMADD213PD	0xc0(%RDI,%RCX,1),%ZMM0,%ZMM12

(2) 0x40230e VMOVUPD	%ZMM12,0xc0(%RSI,%RCX,1)

(2) 0x402316 VMOVUPD	0x100(%R8,%RCX,1),%ZMM13

(2) 0x40231e VFMADD213PD	0x100(%RDI,%RCX,1),%ZMM0,%ZMM13

(2) 0x402326 VMOVUPD	%ZMM13,0x100(%RSI,%RCX,1)

(2) 0x40232e VMOVUPD	0x140(%R8,%RCX,1),%ZMM14

(2) 0x402336 VFMADD213PD	0x140(%RDI,%RCX,1),%ZMM0,%ZMM14

(2) 0x40233e VMOVUPD	%ZMM14,0x140(%RSI,%RCX,1)

(2) 0x402346 VMOVUPD	0x180(%R8,%RCX,1),%ZMM15

(2) 0x40234e VFMADD213PD	0x180(%RDI,%RCX,1),%ZMM0,%ZMM15

(2) 0x402356 VMOVUPD	%ZMM15,0x180(%RSI,%RCX,1)

(2) 0x40235e VMOVUPD	0x1c0(%R8,%RCX,1),%ZMM2

(2) 0x402366 VFMADD213PD	0x1c0(%RDI,%RCX,1),%ZMM0,%ZMM2

(2) 0x40236e VMOVUPD	%ZMM2,0x1c0(%RSI,%RCX,1)

(2) 0x402376 ADD	$0x200,%RCX

(2) 0x40237d CMP	%R11,%RCX

(2) 0x402380 JNE	4022b9

0x402386 MOV	%RAX,%RDI

0x402389 AND	$-0x8,%RDI

0x40238d ADD	%RDI,%RDX

0x402390 CMP	%RDI,%RAX

0x402393 JE	402430

0x402399 SUB	%RDI,%RAX

0x40239c LEA	-0x1(%RAX),%RSI

0x4023a0 CMP	$0x2,%RSI

0x4023a4 JBE	4023cf

0x4023a6 ADD	%RBX,%RDI

0x4023a9 MOV	%RAX,%RBX

0x4023ac VBROADCASTSD	%XMM1,%YMM0

0x4023b1 AND	$-0x4,%RBX

0x4023b5 VMOVUPD	(%R13,%RDI,8),%YMM3

0x4023bc VFMADD132PD	(%R14,%RDI,8),%YMM3,%YMM0

0x4023c2 VMOVUPD	%YMM0,(%R12,%RDI,8)

0x4023c8 ADD	%RBX,%RDX

0x4023cb TEST	$0x3,%AL

0x4023cd JE	402430

0x4023cf LEA	0x1(%RDX),%RAX

0x4023d3 VMOVSD	(%R14,%RDX,8),%XMM4

0x4023d9 VFMADD213SD	(%R13,%RDX,8),%XMM1,%XMM4

0x4023e0 VMOVSD	%XMM4,(%R12,%RDX,8)

0x4023e6 CMP	%RAX,%R10

0x4023e9 JLE	402430

0x4023eb ADD	$0x2,%RDX

0x4023ef VMOVSD	(%R14,%RAX,8),%XMM5

0x4023f5 VFMADD213SD	(%R13,%RAX,8),%XMM1,%XMM5

0x4023fc VMOVSD	%XMM5,(%R12,%RAX,8)

0x402402 CMP	%RDX,%R10

0x402405 JLE	402430

0x402407 VMOVSD	(%R13,%RDX,8),%XMM6

0x40240e VFMADD132SD	(%R14,%RDX,8),%XMM6,%XMM1

0x402414 VMOVSD	%XMM1,(%R12,%RDX,8)

0x40241a VZEROUPPER

0x40241d LEA	-0x20(%RBP),%RSP

0x402421 POP	%RBX

0x402422 POP	%R12

0x402424 POP	%R13

0x402426 POP	%R14

0x402428 POP	%RBP

0x402429 RET

0x40242a NOPW	(%RAX,%RAX,1)

0x402430 VZEROUPPER

0x402433 LEA	-0x20(%RBP),%RSP

0x402437 POP	%RBX

0x402438 POP	%R12

0x40243a POP	%R13

0x40243c POP	%R14

0x40243e POP	%RBP

0x40243f RET

0x402440 INC	%RAX

0x402443 XOR	%EDX,%EDX

0x402445 JMP	402154

0x40244a NOPW	(%RAX,%RAX,1)

0x402450 XOR	%EDI,%EDI

0x402452 MOV	$0x19a686100,%R13

0x40245c MOV	$0x406100,%R14

0x402466 MOV	$0x334906100,%R12

0x402470 JMP	402399

0x402475 NOPW	%CS:(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
○98.94	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○1.06	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	stream.c:354-356
Module	exec

The function is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/gpu04sas.benchmarkcenter.megware.com/177-374-0012/stream-triad/build/stream-triad/src/stream.c:354-356.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 25.83 to 16.00 cycles (1.61x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is poorly vectorized. Only 46% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your function, you can lower the cost of an iteration from 25.83 to 20.45 cycles (1.26x speedup).

Details

44% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

69% of SSE/AVX loads are used in vector version.
72% of SSE/AVX stores are used in vector version.
0% of SSE/AVX addition or subtraction instructions are used in vector version.
72% of SSE/AVX fused multiply-add instructions are used in vector version.
0% of SSE/AVX divide and square root instructions are used in vector version.
9% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Detected 63 FMA (fused multiply-add) operations.

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 2 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gpu04sas.benchmarkcenter.megware.com/177-374-0012/stream-triad/build/stream-triad/src/stream.c:354
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gpu04sas.benchmarkcenter.megware.com/177-374-0012/stream-triad/build/stream-triad/src/stream.c:354

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

IDIV: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gpu04sas.benchmarkcenter.megware.com/177-374-0012/stream-triad/build/stream-triad/src/stream.c:354
VMOVUPD: 7 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gpu04sas.benchmarkcenter.megware.com/177-374-0012/stream-triad/build/stream-triad/src/stream.c:356
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gpu04sas.benchmarkcenter.megware.com/177-374-0012/stream-triad/build/stream-triad/src/stream.c:356
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gpu04sas.benchmarkcenter.megware.com/177-374-0012/stream-triad/build/stream-triad/src/stream.c:356
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gpu04sas.benchmarkcenter.megware.com/177-374-0012/stream-triad/build/stream-triad/src/stream.c:356
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gpu04sas.benchmarkcenter.megware.com/177-374-0012/stream-triad/build/stream-triad/src/stream.c:356
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gpu04sas.benchmarkcenter.megware.com/177-374-0012/stream-triad/build/stream-triad/src/stream.c:356
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gpu04sas.benchmarkcenter.megware.com/177-374-0012/stream-triad/build/stream-triad/src/stream.c:356

Vector unaligned load/store instructions

Detected 2 optimal vector unaligned load/store instructions.

Details

VMOVUPD: 2 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gpu04sas.benchmarkcenter.megware.com/177-374-0012/stream-triad/build/stream-triad/src/stream.c:356
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gpu04sas.benchmarkcenter.megware.com/177-374-0012/stream-triad/build/stream-triad/src/stream.c:356

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Conversion instructions

Detected expensive conversion instructions.

Details

CQTO: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gpu04sas.benchmarkcenter.megware.com/177-374-0012/stream-triad/build/stream-triad/src/stream.c:354

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

3 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 1 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time). 7 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 126 FP arithmetical operations:

63: addition or subtraction (all inside FMA instructions)
63: multiply (all inside FMA instructions)

The binary function is loading 1016 bytes (127 double precision FP elements). The binary function is storing 504 bytes (63 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.

General properties

nb instructions	149
nb uops	155
loop length	675
used x86 registers	15
used mmx registers	0
used xmm registers	4
used ymm registers	2
used zmm registers	8
nb stack references	1

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	25.83 cycles
front end	25.83 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	18.00	18.00	18.00	18.00	12.00	12.00	12.00	12.00	6.00	5.50	1.50	0.00	9.00	9.00
cycles	18.00	18.00	18.00	18.00	12.00	16.67	16.67	16.67	10.00	8.50	1.50	0.00	9.00	9.00

Execution ports to units layout:

ALU0/BRU0: ALU, BRU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1: BRU
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

7.00-12.00

Cycles summary

Front-end	25.83
Dispatch	18.00
DIV/SQRT	7.00-12.00
Overall L1	25.83

Vectorization ratios

INT

all	9%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	9%

all	66%
load	69%
store	72%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	72%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	44%
load	69%
store	72%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	72%
div/sqrt	0%
other	9%

Vector efficiency ratios

INT

all	13%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	13%

all	66%
load	69%
store	71%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	71%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	46%
load	69%
store	71%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	71%
div/sqrt	12%
other	13%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 25.83 cycles. At this rate:

40% of peak load performance is reached (39.33 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
30% of peak store performance is reached (19.51 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 25.83 to 18.00 cycles (1.44x speedup).

ASM code

In the binary file, the address of the function is: 402110

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV $0x401060,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x401030,%R13	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
AND $-0x40,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CALL %RAX	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	2	N/A
MOVSXD %EAX,%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CALL %R13	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	2	N/A
MOVSXD %EAX,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV $0x33450000,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CQTO																		scal (12.5%)
IDIV %R12	2	2	0	0	0	0	0	0	0	0	0	0	0	0	0	9-19	7-12	scal (12.5%)
CMP %RDX,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JL 402440 <main._omp_fn.4+0x330>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
IMUL %RAX,%RCX	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %RCX,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%RAX,%RDX,1),%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP %R10,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JGE 40241d <main._omp_fn.4+0x30d>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
LEA -0x1(%RAX),%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVSD (%RBX),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV %RDX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP $0x6,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JBE 402450 <main._omp_fn.4+0x340>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %RAX,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (,%RDX,8),%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV $0x19a686100,%R13	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV $0x406100,%R14	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
SHR $0x3,%R11	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
VBROADCASTSD %XMM1,%ZMM0	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
SAL $0x6,%R11	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LEA -0x40(%R11),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV $0x334906100,%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
LEA (%R13,%RSI,1),%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%R14,%RSI,1),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SHR $0x6,%R9	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	scal (12.5%)
INC %R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD %R12,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
XOR %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
AND $0x7,%R9D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
JE 4022b9 <main._omp_fn.4+0x1a9>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x1,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 402297 <main._omp_fn.4+0x187>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x2,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 40227e <main._omp_fn.4+0x16e>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x3,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 402265 <main._omp_fn.4+0x155>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x4,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 40224c <main._omp_fn.4+0x13c>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x5,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 402233 <main._omp_fn.4+0x123>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x6,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 40221a <main._omp_fn.4+0x10a>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVUPD (%R8),%ZMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1	vect (100.0%)
MOV $0x40,%ECX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VFMADD213PD (%RDI),%ZMM0,%ZMM2	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1	vect (100.0%)
VMOVUPD %ZMM2,(%RSI)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2	vect (100.0%)
VMOVUPD (%R8,%RCX,1),%ZMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1	vect (100.0%)
VFMADD213PD (%RDI,%RCX,1),%ZMM0,%ZMM3	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1	vect (100.0%)
VMOVUPD %ZMM3,(%RSI,%RCX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2	vect (100.0%)
ADD $0x40,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVUPD (%R8,%RCX,1),%ZMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1	vect (100.0%)
VFMADD213PD (%RDI,%RCX,1),%ZMM0,%ZMM4	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1	vect (100.0%)
VMOVUPD %ZMM4,(%RSI,%RCX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2	vect (100.0%)
ADD $0x40,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVUPD (%R8,%RCX,1),%ZMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1	vect (100.0%)
VFMADD213PD (%RDI,%RCX,1),%ZMM0,%ZMM5	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1	vect (100.0%)
VMOVUPD %ZMM5,(%RSI,%RCX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2	vect (100.0%)
ADD $0x40,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVUPD (%R8,%RCX,1),%ZMM6	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1	vect (100.0%)
VFMADD213PD (%RDI,%RCX,1),%ZMM0,%ZMM6	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1	vect (100.0%)
VMOVUPD %ZMM6,(%RSI,%RCX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2	vect (100.0%)
ADD $0x40,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVUPD (%R8,%RCX,1),%ZMM7	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1	vect (100.0%)
VFMADD213PD (%RDI,%RCX,1),%ZMM0,%ZMM7	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1	vect (100.0%)
VMOVUPD %ZMM7,(%RSI,%RCX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2	vect (100.0%)
ADD $0x40,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVUPD (%R8,%RCX,1),%ZMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1	vect (100.0%)
VFMADD213PD (%RDI,%RCX,1),%ZMM0,%ZMM8	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1	vect (100.0%)
VMOVUPD %ZMM8,(%RSI,%RCX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2	vect (100.0%)
ADD $0x40,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP %R11,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 402386 <main._omp_fn.4+0x276>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x8,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD %RDI,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP %RDI,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 402430 <main._omp_fn.4+0x320>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
SUB %RDI,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x1(%RAX),%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP $0x2,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JBE 4023cf <main._omp_fn.4+0x2bf>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
ADD %RBX,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %RAX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VBROADCASTSD %XMM1,%YMM0	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
AND $-0x4,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVUPD (%R13,%RDI,8),%YMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50	vect (50.0%)
VFMADD132PD (%R14,%RDI,8),%YMM3,%YMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VMOVUPD %YMM0,(%R12,%RDI,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1	vect (50.0%)
ADD %RBX,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
TEST $0x3,%AL	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
JE 402430 <main._omp_fn.4+0x320>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
LEA 0x1(%RDX),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVSD (%R14,%RDX,8),%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (12.5%)
VFMADD213SD (%R13,%RDX,8),%XMM1,%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM4,(%R12,%RDX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1	scal (12.5%)
CMP %RAX,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JLE 402430 <main._omp_fn.4+0x320>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
ADD $0x2,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVSD (%R14,%RAX,8),%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (12.5%)
VFMADD213SD (%R13,%RAX,8),%XMM1,%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM5,(%R12,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1	scal (12.5%)
CMP %RDX,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JLE 402430 <main._omp_fn.4+0x320>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVSD (%R13,%RDX,8),%XMM6	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (12.5%)
VFMADD132SD (%R14,%RDX,8),%XMM6,%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM1,(%R12,%RDX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1	scal (12.5%)
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x20(%RBP),%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x20(%RBP),%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
INC %RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 402154 <main._omp_fn.4+0x44>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV $0x19a686100,%R13	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV $0x406100,%R14	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV $0x334906100,%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
JMP 402399 <main._omp_fn.4+0x289>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	stream.c:354-356
Module	exec

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

44% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

69% of SSE/AVX loads are used in vector version.
72% of SSE/AVX stores are used in vector version.
0% of SSE/AVX addition or subtraction instructions are used in vector version.
72% of SSE/AVX fused multiply-add instructions are used in vector version.
0% of SSE/AVX divide and square root instructions are used in vector version.
9% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Detected 63 FMA (fused multiply-add) operations.

CALL instructions

Detected function call instructions.

Details

unknown: 2 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gpu04sas.benchmarkcenter.megware.com/177-374-0012/stream-triad/build/stream-triad/src/stream.c:354
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gpu04sas.benchmarkcenter.megware.com/177-374-0012/stream-triad/build/stream-triad/src/stream.c:354

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

IDIV: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gpu04sas.benchmarkcenter.megware.com/177-374-0012/stream-triad/build/stream-triad/src/stream.c:354
VMOVUPD: 7 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gpu04sas.benchmarkcenter.megware.com/177-374-0012/stream-triad/build/stream-triad/src/stream.c:356
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gpu04sas.benchmarkcenter.megware.com/177-374-0012/stream-triad/build/stream-triad/src/stream.c:356
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gpu04sas.benchmarkcenter.megware.com/177-374-0012/stream-triad/build/stream-triad/src/stream.c:356
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gpu04sas.benchmarkcenter.megware.com/177-374-0012/stream-triad/build/stream-triad/src/stream.c:356
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gpu04sas.benchmarkcenter.megware.com/177-374-0012/stream-triad/build/stream-triad/src/stream.c:356
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gpu04sas.benchmarkcenter.megware.com/177-374-0012/stream-triad/build/stream-triad/src/stream.c:356
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gpu04sas.benchmarkcenter.megware.com/177-374-0012/stream-triad/build/stream-triad/src/stream.c:356

Vector unaligned load/store instructions

Detected 2 optimal vector unaligned load/store instructions.

Details

VMOVUPD: 2 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gpu04sas.benchmarkcenter.megware.com/177-374-0012/stream-triad/build/stream-triad/src/stream.c:356
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gpu04sas.benchmarkcenter.megware.com/177-374-0012/stream-triad/build/stream-triad/src/stream.c:356

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Conversion instructions

Detected expensive conversion instructions.

Details

CQTO: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gpu04sas.benchmarkcenter.megware.com/177-374-0012/stream-triad/build/stream-triad/src/stream.c:354

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

The binary function is composed of 126 FP arithmetical operations:

63: addition or subtraction (all inside FMA instructions)
63: multiply (all inside FMA instructions)

The binary function is loading 1016 bytes (127 double precision FP elements). The binary function is storing 504 bytes (63 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.

General properties

nb instructions	149
nb uops	155
loop length	675
used x86 registers	15
used mmx registers	0
used xmm registers	4
used ymm registers	2
used zmm registers	8
nb stack references	1

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	25.83 cycles
front end	25.83 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	18.00	18.00	18.00	18.00	12.00	12.00	12.00	12.00	6.00	5.50	1.50	0.00	9.00	9.00
cycles	18.00	18.00	18.00	18.00	12.00	16.67	16.67	16.67	10.00	8.50	1.50	0.00	9.00	9.00

Execution ports to units layout:

ALU0/BRU0: ALU, BRU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1: BRU
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

7.00-12.00

Cycles summary

Front-end	25.83
Dispatch	18.00
DIV/SQRT	7.00-12.00
Overall L1	25.83

Vectorization ratios

INT

all	9%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	9%

all	66%
load	69%
store	72%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	72%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	44%
load	69%
store	72%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	72%
div/sqrt	0%
other	9%

Vector efficiency ratios

INT

all	13%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	13%

all	66%
load	69%
store	71%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	71%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	46%
load	69%
store	71%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	71%
div/sqrt	12%
other	13%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 25.83 cycles. At this rate:

40% of peak load performance is reached (39.33 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
30% of peak store performance is reached (19.51 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 402110

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV $0x401060,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x401030,%R13	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
AND $-0x40,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CALL %RAX	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	2	N/A
MOVSXD %EAX,%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CALL %R13	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	2	N/A
MOVSXD %EAX,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV $0x33450000,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CQTO																		scal (12.5%)
IDIV %R12	2	2	0	0	0	0	0	0	0	0	0	0	0	0	0	9-19	7-12	scal (12.5%)
CMP %RDX,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JL 402440 <main._omp_fn.4+0x330>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
IMUL %RAX,%RCX	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %RCX,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%RAX,%RDX,1),%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP %R10,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JGE 40241d <main._omp_fn.4+0x30d>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
LEA -0x1(%RAX),%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVSD (%RBX),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV %RDX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP $0x6,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JBE 402450 <main._omp_fn.4+0x340>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %RAX,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (,%RDX,8),%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV $0x19a686100,%R13	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV $0x406100,%R14	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
SHR $0x3,%R11	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
VBROADCASTSD %XMM1,%ZMM0	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
SAL $0x6,%R11	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LEA -0x40(%R11),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV $0x334906100,%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
LEA (%R13,%RSI,1),%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%R14,%RSI,1),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SHR $0x6,%R9	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	scal (12.5%)
INC %R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD %R12,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
XOR %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
AND $0x7,%R9D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (6.3%)
JE 4022b9 <main._omp_fn.4+0x1a9>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x1,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 402297 <main._omp_fn.4+0x187>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x2,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 40227e <main._omp_fn.4+0x16e>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x3,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 402265 <main._omp_fn.4+0x155>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x4,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 40224c <main._omp_fn.4+0x13c>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x5,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 402233 <main._omp_fn.4+0x123>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x6,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 40221a <main._omp_fn.4+0x10a>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVUPD (%R8),%ZMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1	vect (100.0%)
MOV $0x40,%ECX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VFMADD213PD (%RDI),%ZMM0,%ZMM2	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1	vect (100.0%)
VMOVUPD %ZMM2,(%RSI)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2	vect (100.0%)
VMOVUPD (%R8,%RCX,1),%ZMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1	vect (100.0%)
VFMADD213PD (%RDI,%RCX,1),%ZMM0,%ZMM3	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1	vect (100.0%)
VMOVUPD %ZMM3,(%RSI,%RCX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2	vect (100.0%)
ADD $0x40,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVUPD (%R8,%RCX,1),%ZMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1	vect (100.0%)
VFMADD213PD (%RDI,%RCX,1),%ZMM0,%ZMM4	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1	vect (100.0%)
VMOVUPD %ZMM4,(%RSI,%RCX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2	vect (100.0%)
ADD $0x40,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVUPD (%R8,%RCX,1),%ZMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1	vect (100.0%)
VFMADD213PD (%RDI,%RCX,1),%ZMM0,%ZMM5	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1	vect (100.0%)
VMOVUPD %ZMM5,(%RSI,%RCX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2	vect (100.0%)
ADD $0x40,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVUPD (%R8,%RCX,1),%ZMM6	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1	vect (100.0%)
VFMADD213PD (%RDI,%RCX,1),%ZMM0,%ZMM6	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1	vect (100.0%)
VMOVUPD %ZMM6,(%RSI,%RCX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2	vect (100.0%)
ADD $0x40,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVUPD (%R8,%RCX,1),%ZMM7	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1	vect (100.0%)
VFMADD213PD (%RDI,%RCX,1),%ZMM0,%ZMM7	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1	vect (100.0%)
VMOVUPD %ZMM7,(%RSI,%RCX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2	vect (100.0%)
ADD $0x40,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVUPD (%R8,%RCX,1),%ZMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1	vect (100.0%)
VFMADD213PD (%RDI,%RCX,1),%ZMM0,%ZMM8	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1	vect (100.0%)
VMOVUPD %ZMM8,(%RSI,%RCX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2	vect (100.0%)
ADD $0x40,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP %R11,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 402386 <main._omp_fn.4+0x276>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x8,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD %RDI,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP %RDI,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 402430 <main._omp_fn.4+0x320>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
SUB %RDI,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x1(%RAX),%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP $0x2,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JBE 4023cf <main._omp_fn.4+0x2bf>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
ADD %RBX,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %RAX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VBROADCASTSD %XMM1,%YMM0	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
AND $-0x4,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVUPD (%R13,%RDI,8),%YMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50	vect (50.0%)
VFMADD132PD (%R14,%RDI,8),%YMM3,%YMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VMOVUPD %YMM0,(%R12,%RDI,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1	vect (50.0%)
ADD %RBX,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
TEST $0x3,%AL	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
JE 402430 <main._omp_fn.4+0x320>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
LEA 0x1(%RDX),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVSD (%R14,%RDX,8),%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (12.5%)
VFMADD213SD (%R13,%RDX,8),%XMM1,%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM4,(%R12,%RDX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1	scal (12.5%)
CMP %RAX,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JLE 402430 <main._omp_fn.4+0x320>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
ADD $0x2,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVSD (%R14,%RAX,8),%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (12.5%)
VFMADD213SD (%R13,%RAX,8),%XMM1,%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM5,(%R12,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1	scal (12.5%)
CMP %RDX,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JLE 402430 <main._omp_fn.4+0x320>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVSD (%R13,%RDX,8),%XMM6	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	scal (12.5%)
VFMADD132SD (%R14,%RDX,8),%XMM6,%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM1,(%R12,%RDX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1	scal (12.5%)
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x20(%RBP),%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x20(%RBP),%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
INC %RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 402154 <main._omp_fn.4+0x44>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV $0x19a686100,%R13	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV $0x406100,%R14	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV $0x334906100,%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
JMP 402399 <main._omp_fn.4+0x289>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼main._omp_fn.4–	95.33	7.21
○Loop 2 - stream.c:356-356 - exec	95.33	7.12

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Vector unaligned load/store instructions

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Type of elements and instruction set

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