OV - exec - Function main.extracted.50

	Function: main.extracted.50	Module: exec	Source: stream.c:354-356	Coverage (incl. loops): 94.86% \| (excl. loops): 0.00%

/beegfs/hackathon/users/eoseret/qaas_runs_test/gpu04sas.benchmarkcenter.megware.com/177-374-0012/stream-triad/build/stream-triad/src/stream.c: 354 - 356

--------------------------------------------------------------------------------

354: #pragma omp parallel for

355: 	for (j=0; j<STREAM_ARRAY_SIZE; j++)

356: 	    a[j] = b[j]+scalar*c[j];

0x4032b0 PUSH	%RBP

0x4032b1 MOV	%RSP,%RBP

0x4032b4 PUSH	%R14

0x4032b6 PUSH	%RBX

0x4032b7 SUB	$0x20,%RSP

0x4032bb MOVL	$0,-0x14(%RBP)

0x4032c2 MOV	(%RDI),%EBX

0x4032c4 MOVQ	$0,-0x28(%RBP)

0x4032cc MOVQ	$0x3344ffff,-0x20(%RBP)

0x4032d4 MOVQ	$0x1,-0x30(%RBP)

0x4032dc SUB	$0x8,%RSP

0x4032e0 LEA	-0x30(%RBP),%RAX

0x4032e4 LEA	-0x20(%RBP),%R9

0x4032e8 MOV	$0x4ceb88e20,%RDI

0x4032f2 MOV	$0x401050,%R10

0x4032fc LEA	-0x14(%RBP),%RCX

0x403300 LEA	-0x28(%RBP),%R8

0x403304 MOV	%EBX,%ESI

0x403306 MOV	$0x22,%EDX

0x40330b PUSH	$0x1

0x40330d PUSH	$0x1

0x40330f PUSH	%RAX

0x403310 CALL	%R10

0x403313 ADD	$0x20,%RSP

0x403317 MOV	-0x28(%RBP),%RAX

0x40331b MOV	-0x20(%RBP),%R9

0x40331f CMP	%R9,%RAX

0x403322 JA	4033f3

0x403328 SUB	%RAX,%R9

0x40332b MOV	$0x334906060,%RSI

0x403335 MOV	$0x19a686060,%RDI

0x40333f MOV	$0x4040d0,%RCX

0x403349 MOV	$0x406060,%RDX

0x403353 INC	%R9

0x403356 MOV	%R9,%R8

0x403359 AND	$0x7ffffff8,%R8

0x403360 JE	4033af

0x403362 VBROADCASTSD	(%RCX),%ZMM0

0x403368 LEA	(,%RAX,8),%R10

0x403370 XOR	%R11D,%R11D

0x403373 NOPW	%CS:(%RAX,%RAX,1)

(13) 0x403380 LEA	(%R10,%R11,8),%R14

(13) 0x403384 ADD	$0x8,%R11

(13) 0x403388 VMOVUPD	(%RSI,%R14,1),%ZMM1

(13) 0x40338f VFMADD213PD	(%RDI,%R14,1),%ZMM0,%ZMM1

(13) 0x403396 VMOVUPD	%ZMM1,(%RDX,%R14,1)

(13) 0x40339d CMP	%R8,%R11

(13) 0x4033a0 JB	403380

0x4033a2 CMP	%R8,%R9

0x4033a5 JE	4033f3

0x4033a7 VPBROADCASTQ	%R9,%ZMM0

0x4033ad JMP	4033b8

0x4033af VPBROADCASTQ	%R9,%ZMM0

0x4033b5 XOR	%R8D,%R8D

0x4033b8 VPBROADCASTQ	%R8,%ZMM1

0x4033be MOV	$0x404180,%R9

0x4033c8 ADD	%R8,%RAX

0x4033cb VPSUBQ	%ZMM1,%ZMM0,%ZMM0

0x4033d1 VPCMPNLEUQ	(%R9),%ZMM0,%K1

0x4033d8 VMOVUPD	(%RSI,%RAX,8),%ZMM0{%K1}{z}

0x4033df VMOVUPD	(%RDI,%RAX,8),%ZMM1{%K1}{z}

0x4033e6 VFMADD231PD	(%RCX){1to8},%ZMM0,%ZMM1

0x4033ec VMOVUPD	%ZMM1,(%RDX,%RAX,8){%K1}

0x4033f3 MOV	$0x4ceb88e40,%RDI

0x4033fd MOV	$0x401030,%RAX

0x403407 MOV	%EBX,%ESI

0x403409 ADD	$0x20,%RSP

0x40340d POP	%RBX

0x40340e POP	%R14

0x403410 POP	%RBP

0x403411 VZEROUPPER

0x403414 JMP	%RAX

Coverage (%)	Name	Source Location	Module
►100.00+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run icx_0

Source file and lines	stream.c:354-356
Module	exec

The function is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/gpu04sas.benchmarkcenter.megware.com/177-374-0012/stream-triad/build/stream-triad/src/stream.c:354-356.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 11.33 to 3.50 cycles (3.24x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is poorly vectorized. Only 33% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your function, you can lower the cost of an iteration from 11.33 to 9.32 cycles (1.22x speedup).

Details

30% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

66% of SSE/AVX loads are used in vector version.
20% of SSE/AVX stores are used in vector version.
15% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your function is irregular or mixes elements of different sizes.

Workaround

If your function is irregular, try to remove or hoist conditional structures out of your function. If it mixes elements of different sizes, try to uniformize them.

FMA

Detected 8 FMA (fused multiply-add) operations.

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gpu04sas.benchmarkcenter.megware.com/177-374-0012/stream-triad/build/stream-triad/src/stream.c:354

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VMOVUPD: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gpu04sas.benchmarkcenter.megware.com/177-374-0012/stream-triad/build/stream-triad/src/stream.c:356
VPBROADCASTQ: 3 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gpu04sas.benchmarkcenter.megware.com/177-374-0012/stream-triad/build/stream-triad/src/stream.c:355
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gpu04sas.benchmarkcenter.megware.com/177-374-0012/stream-triad/build/stream-triad/src/stream.c:355
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gpu04sas.benchmarkcenter.megware.com/177-374-0012/stream-triad/build/stream-triad/src/stream.c:354

Type of elements and instruction set

1 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 16 FP arithmetical operations:

8: addition or subtraction (all inside FMA instructions)
8: multiply (all inside FMA instructions)

The binary function is loading 228 bytes (28 double precision FP elements). The binary function is storing 92 bytes (11 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.05 FP operations per loaded or stored byte.

General properties

nb instructions	65
nb uops	68
loop length	324
used x86 registers	13
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	2
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	11.33 cycles
front end	11.33 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	7.00	7.00	7.00	7.00	3.00	4.33	4.33	4.33	1.00	3.50	3.50	1.00	1.00	1.00
cycles	7.00	7.00	7.00	7.00	3.00	5.33	5.33	5.33	2.00	3.50	3.50	1.00	1.00	1.00

Execution ports to units layout:

ALU0/BRU0: ALU, BRU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1: BRU
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	11.33
Dispatch	7.00
Overall L1	11.33

Vectorization ratios

INT

all	16%
load	50%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	16%

all	80%
load	75%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	30%
load	66%
store	20%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	15%

Vector efficiency ratios

INT

all	20%
load	53%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	19%

all	82%
load	78%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	33%
load	69%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	19%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each call to the function takes 11.33 cycles. At this rate:

20% of peak load performance is reached (20.12 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
12% of peak store performance is reached (8.12 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 11.33 to 7.00 cycles (1.62x speedup).

ASM code

In the binary file, the address of the function is: 4032b0

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x20,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVL $0,-0x14(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOV (%RDI),%EBX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33	scal (6.3%)
MOVQ $0,-0x28(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOVQ $0x3344ffff,-0x20(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOVQ $0x1,-0x30(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x30(%RBP),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x20(%RBP),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV $0x4ceb88e20,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV $0x401050,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
LEA -0x14(%RBP),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x28(%RBP),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %EBX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x22,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL %R10	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	2	N/A
ADD $0x20,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV -0x28(%RBP),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33	N/A
MOV -0x20(%RBP),%R9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33	N/A
CMP %R9,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JA 4033f3 <main.extracted.50+0x143>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
SUB %RAX,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV $0x334906060,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV $0x19a686060,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV $0x4040d0,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV $0x406060,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
INC %R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %R9,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
AND $0x7ffffff8,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 4033af <main.extracted.50+0xff>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VBROADCASTSD (%RCX),%ZMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0.50	0.50	0	0	0	5	1	scal (12.5%)
LEA (,%RAX,8),%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
XOR %R11D,%R11D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
CMP %R8,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 4033f3 <main.extracted.50+0x143>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VPBROADCASTQ %R9,%ZMM0	2	0	0	0	0	0	0	0	0	0	1	1	0	0	0	1	1	scal (12.5%)
JMP 4033b8 <main.extracted.50+0x108>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1	N/A
VPBROADCASTQ %R9,%ZMM0	2	0	0	0	0	0	0	0	0	0	1	1	0	0	0	1	1	scal (12.5%)
XOR %R8D,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
VPBROADCASTQ %R8,%ZMM1	2	0	0	0	0	0	0	0	0	0	1	1	0	0	0	1	1	scal (12.5%)
MOV $0x404180,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
ADD %R8,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VPSUBQ %ZMM1,%ZMM0,%ZMM0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	vect (100.0%)
VPCMPNLEUQ (%R9),%ZMM0,%K1																		vect (100.0%)
VMOVUPD (%RSI,%RAX,8),%ZMM0{%K1}{z}	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1	vect (100.0%)
VMOVUPD (%RDI,%RAX,8),%ZMM1{%K1}{z}	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1	vect (100.0%)
VFMADD231PD (%RCX){1to8},%ZMM0,%ZMM1	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1	vect (100.0%)
VMOVUPD %ZMM1,(%RDX,%RAX,8){%K1}	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2	vect (100.0%)
MOV $0x4ceb88e40,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV $0x401030,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV %EBX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD $0x20,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
JMP %RAX	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run icx_0

Source file and lines	stream.c:354-356
Module	exec

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 11.33 to 3.50 cycles (3.24x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

30% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

66% of SSE/AVX loads are used in vector version.
20% of SSE/AVX stores are used in vector version.
15% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your function is irregular or mixes elements of different sizes.

Workaround

If your function is irregular, try to remove or hoist conditional structures out of your function. If it mixes elements of different sizes, try to uniformize them.

FMA

Detected 8 FMA (fused multiply-add) operations.

CALL instructions

Detected function call instructions.

Details

unknown: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gpu04sas.benchmarkcenter.megware.com/177-374-0012/stream-triad/build/stream-triad/src/stream.c:354

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VMOVUPD: 1 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gpu04sas.benchmarkcenter.megware.com/177-374-0012/stream-triad/build/stream-triad/src/stream.c:356
VPBROADCASTQ: 3 occurrences►
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gpu04sas.benchmarkcenter.megware.com/177-374-0012/stream-triad/build/stream-triad/src/stream.c:355
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gpu04sas.benchmarkcenter.megware.com/177-374-0012/stream-triad/build/stream-triad/src/stream.c:355
- /beegfs/hackathon/users/eoseret/qaas_runs_test/gpu04sas.benchmarkcenter.megware.com/177-374-0012/stream-triad/build/stream-triad/src/stream.c:354

Type of elements and instruction set

1 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 16 FP arithmetical operations:

8: addition or subtraction (all inside FMA instructions)
8: multiply (all inside FMA instructions)

The binary function is loading 228 bytes (28 double precision FP elements). The binary function is storing 92 bytes (11 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.05 FP operations per loaded or stored byte.

General properties

nb instructions	65
nb uops	68
loop length	324
used x86 registers	13
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	2
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	11.33 cycles
front end	11.33 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	7.00	7.00	7.00	7.00	3.00	4.33	4.33	4.33	1.00	3.50	3.50	1.00	1.00	1.00
cycles	7.00	7.00	7.00	7.00	3.00	5.33	5.33	5.33	2.00	3.50	3.50	1.00	1.00	1.00

Execution ports to units layout:

ALU0/BRU0: ALU, BRU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1: BRU
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	11.33
Dispatch	7.00
Overall L1	11.33

Vectorization ratios

INT

all	16%
load	50%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	16%

all	80%
load	75%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	30%
load	66%
store	20%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	15%

Vector efficiency ratios

INT

all	20%
load	53%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	19%

all	82%
load	78%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	33%
load	69%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	19%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each call to the function takes 11.33 cycles. At this rate:

20% of peak load performance is reached (20.12 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
12% of peak store performance is reached (8.12 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 4032b0

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x20,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVL $0,-0x14(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOV (%RDI),%EBX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33	scal (6.3%)
MOVQ $0,-0x28(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOVQ $0x3344ffff,-0x20(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOVQ $0x1,-0x30(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x30(%RBP),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x20(%RBP),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV $0x4ceb88e20,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV $0x401050,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
LEA -0x14(%RBP),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x28(%RBP),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %EBX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x22,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL %R10	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	2	N/A
ADD $0x20,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV -0x28(%RBP),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33	N/A
MOV -0x20(%RBP),%R9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33	N/A
CMP %R9,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JA 4033f3 <main.extracted.50+0x143>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
SUB %RAX,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV $0x334906060,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV $0x19a686060,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV $0x4040d0,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV $0x406060,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
INC %R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %R9,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
AND $0x7ffffff8,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 4033af <main.extracted.50+0xff>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VBROADCASTSD (%RCX),%ZMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0.50	0.50	0	0	0	5	1	scal (12.5%)
LEA (,%RAX,8),%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
XOR %R11D,%R11D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
CMP %R8,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 4033f3 <main.extracted.50+0x143>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VPBROADCASTQ %R9,%ZMM0	2	0	0	0	0	0	0	0	0	0	1	1	0	0	0	1	1	scal (12.5%)
JMP 4033b8 <main.extracted.50+0x108>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1	N/A
VPBROADCASTQ %R9,%ZMM0	2	0	0	0	0	0	0	0	0	0	1	1	0	0	0	1	1	scal (12.5%)
XOR %R8D,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
VPBROADCASTQ %R8,%ZMM1	2	0	0	0	0	0	0	0	0	0	1	1	0	0	0	1	1	scal (12.5%)
MOV $0x404180,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
ADD %R8,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VPSUBQ %ZMM1,%ZMM0,%ZMM0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	vect (100.0%)
VPCMPNLEUQ (%R9),%ZMM0,%K1																		vect (100.0%)
VMOVUPD (%RSI,%RAX,8),%ZMM0{%K1}{z}	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1	vect (100.0%)
VMOVUPD (%RDI,%RAX,8),%ZMM1{%K1}{z}	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1	vect (100.0%)
VFMADD231PD (%RCX){1to8},%ZMM0,%ZMM1	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1	vect (100.0%)
VMOVUPD %ZMM1,(%RDX,%RAX,8){%K1}	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2	vect (100.0%)
MOV $0x4ceb88e40,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV $0x401030,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV %EBX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD $0x20,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
JMP %RAX	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1	N/A

Name	Coverage (%)	Time (s)
▼main.extracted.50–	94.86	7.35
○Loop 13 - stream.c:355-356 - exec	94.86	7.27

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Masked instructions

Details

Workaround

FMA

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Masked instructions

Details

Workaround

FMA

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code